Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs

Digital Design-for-Diagnosis Method for Error Identification

of Pipelined ADCs

Jin-Fu Lin&Hsin-Wen Ting

Received: 28 December 2010 / Accepted: 30 August 2011 / Published online: 9 September 2011 # Springer Science+Business Media, LLC 2011

Abstract This paper presents a design-for-diagnosis method to identify error sources in pipelined analog-to-digital con-verters (ADCs). In the proposed method, the stage under test (SUT) is configured to separate each error effect contained in its output residual signal. Two stages after the SUT are configured as a cyclic ADC to digitize the residual output voltage of the SUT. Critical circuit parameters, namely, op-amp gain, capacitor mismatch, op-op-amp offset, and comparator offset, are identified in the digital domain. Accurate analog test input signals are not necessary for the proposed design-for-diagnosis scheme. A simple digital decoder is employed to generate test control signals. Several additional switches are used to perform SUT re-configuration, which induce minor area overhead. Behavioral and circuit simulations are performed to show the effectiveness of the proposed method.

Keywords Pipelined analog-to-digital converter (ADC) . Design-for-diagnosis . Error identification . Stage under test (SUT)

1 Introduction

The high-performance analog-to-digital converter (ADC) is an important block in modern electronic devices and systems.

Therefore, characterizing the performance of ADCs is an important concern [14, 15]. In many communication and video applications, the pipelined ADC is a commonly used ADC architecture. Many error sources, such as op-amp gain error, capacitor mismatch error, comparator offset, and op-amp offset, degrade the performance of a pipelined ADC. In a practical chip, the difficulty of debugging a pipelined ADC is increased because fault effects induced by these error sources would simultaneously appear in pipelined ADCs.

In [1,2,15], integrated nonlinearity (INL) and differen-tial nonlinearity (DNL) are employed as diagnosis tools to identify error sources of ADC performance degradation. In [15], the relationships among the transmission parameter and static one are analyzed at the expense of on-chip reference sine-wave histograms calculation. In [1] and [2], DNL and INL are used to estimate error sources in ADCs but only combined error effects are obtained and the individual error effect cannot be determined. In [7], authors discuss many error sources and their corresponding INL and DNL features. Typical and individual error effects can be determined from profiles of INLs and DNLs. However, fault masking occurs when critical errors simultaneously appear in practical cases. As a result, critical errors are difficult to be identified from complex and irregular INL/ DNL error features.

In [6], a voltage controlled oscillator (VCO) is employed to digitize the analog output of the stage under test (SUT). The identification of error sources can be performed in the digital domain. However, the high-frequency noise of the VCO would couple to the critical analog signal, which reduces the test accuracy. Moreover, an accurate sample-and-hold amplifier (SHA) is necessary to provide a stable voltage to VCO input for a long time. This SHA is usually power-hungry for high-resolution applications. In [11], authors propose a structure-based diagnosis method to effectively Responsible Editor: M. Margala

J.-F. Lin

Himax Technologies, Inc., Tainan, Taiwan

H.-W. Ting (*)

Department of Electronics Engineering,

National Kaohsiung University of Applied Sciences, Kaohsiung, Taiwan

e-mail: hwting@cc.kuas.edu.tw DOI 10.1007/s10836-011-5252-5

identify error sources. However, this method requires precise input signals and an accurate analog window comparator, which makes this method difficult to use.

In this paper, a digital design-for-diagnosis method is proposed. The topology of SUT in a pipelined ADC is properly configured to avoid the effect of fault masking. The back-end stages, i.e. the stages after the SUT, serve as a digitizer which converts the SUT’s output residual voltage into its digital representation. The resultant digital codes are exploited to identify individual critical circuit parameters. Additional switches and the corresponding digital control circuits are necessary to configure the SUT, which only induces minor area overhead. Particularly, precise analog test signals and accurate analog circuits are not required in the proposed method.

The rest of the paper is organized as follows. Section2 briefly introduces the error mechanism of a pipelined ADC with a switched-capacitor (SC) circuit implementation. Details of the proposed diagnosis method for identifying gain errors and offset errors of pipelined ADCs are given in Section3and4, respectively. The identification accuracy of the proposed method is discussed in Section 5. The considerations of circuit implementations of the proposed method are introduced in Section6. Simulation results that verify the effectiveness of the proposed method are shown in Section7. Finally, conclusions are given in Section8.

2 Error Mechanism of Pipelined ADCs

The general architecture of a conventional pipelined ADC with digital error correction (DEC) technique is shown in Fig.1. A pipelined ADC usually consists of a front-end SHA followed by several cascaded pipelined stages which are realized by the same architecture. Digital logic circuits are required to

perform the time alignment and the offset error correction. Each pipelined stage processes ni-bit coarse quantization of

the input signal Vi and produces the corresponding residual

output Vi+1 to the next stage. With the help of stage

amplification, accuracy requirements of the latter stages can be gradually relaxed. Functions of each pipelined stage, such as SHA, sub-DAC, subtraction, and stage amplification, are usually implemented together with a multiplying digital-to-analog converter (MDAC) circuit [4,8].

The 1.5-bit/stage architecture is commonly used for constructing high-speed pipelined ADCs because it has a simple circuit implementation, high-speed operation, and capability of tolerating large comparator offset with the help of DEC. Hence, a 1.5-bit/stage pipelined ADC is selected as an example to illustrate the proposed method in this paper. The proposed method can also be applied to other architectures (1-bit/stage, 2-bit/stage, 2.5-bit/stage, etc.) at the expense of additional modifications.

The ideal transfer curve of a 1.5-bit/stage pipelined stage is shown in Fig. 2. The reference voltages, which define the operating range of a pipelined ADC, are ±Vref.

The ideal decision levels of comparators in the sub-ADC are set to ±Vref/4 as shown in Fig.2.

With the help of DEC, a comparator offset which is up to ±Vref/4 can be tolerated. A typical single-ended SC

MDAC for a 1.5-bit/stage pipelined stage is illustrated in Fig. 3 [4, 8]. In practice, a fully-differential topology is preferred for better noise immunity and signal to noise ratio (SNR). The DAC output Vdac is one of three

voltages (−Vref, 0, +Vref) that are determined by digital

outputs of the sub-ADC. In ϕ1/ϕ1a, the input signal is

sampled by Csand Cf. Inϕ2, the MDAC circuit produces

a residual output for the subsequent stage. Early falling clock ϕ1a is used to avoid signal-dependent charge

injection. Sub-DAC Sub-ADC S/H Vout nibit − + MDAC Front-end S/H Vin Residure

Stage 1 Stage 2 Stage i

n1 n2 ni

Digital Error Correction(DEC) Logic

N bits

V1 V2 V3

1 2ni−

Vin

Fig. 1 Block diagram of an N-bit pipelined ADC with DEC

Considering the finite open-loop operational-amplifier (op-amp) gain and capacitor mismatch (Cs ≠ Cf), the

practical transfer function of a 1.5-bit/stage MDAC is given by (1) and (2). Vout¼ Vin 1þ Cs Cf
 þ Vref Cs Cf    K; Vin< Vref=4 Vin 1 þ Cs Cf
  K;  Vref=  V4 in< Vref=4 Vin 1þ Cs Cf
  Vref Cs Cf    K; Vin Vref=4 8 > > > > > > > < > > > > > > > : ð1Þ K¼ 1 1þCsþCfþCp ACf ð2Þ where A is the finite open-loop op-amp gain and Cpis the

parasitic capacitance at op-amp inverting input node. Critical static error sources existed intrinsically in an SC MDAC circuit can be categorized into two groups and summarized in Table1.

3 Identifying Gain Error Sources

3.1 Concept

Figure 4a shows the concept of the proposed diagnosis method. The SUT is configured as an SHA. When a dc input test signal Vtest is applied to the SUT, the corresponding

output voltage Vout, which contains additional error

compo-nents compared with Vtest, is generated. Then, Voutand Vtest

are converted into digital codes Dout,errand Dout,ideal by the

back-end stages, respectively. Circuit errors of the SUT can thus be determined using Dout,errand Dout,ideal.

However, gain errors and offset errors of the back-end stages and the SUT are included in Dout,ideal and Dout,err. To

remove the offset effects of the SUT and the backend stages, Vtest and–Vtest are individually applied to the SUT and the

back-end stages. When applying Vtest, the corresponding

digital outputs are Doutp,err and Doutp,ideal by observing

Fig. 4b. When applying −Vtest, the corresponding digital

outputs are Doutn,errand Doutn,idealalso by observing Fig.4b.

Differences between positive and negative digital codes are employed to identify gain error:

Ddiff out;err ¼ Doutp;err Doutn;err ð3Þ

Ddiff out;ideal¼ Doutp;ideal Doutn;ideal ð4Þ

The gain effect of the back-end stages is therefore removed using: Vdiff out Vdiff test ¼ Voutp Voutn Vtest Vð testÞ ¼ Ddiff out;err D_{diff out;ideal}
 ð5Þ where Voutpand Voutnare outputs of the SUT corresponding

to input test signals Vtestand −Vtest, respectively. The ratio

expressed in (5) represents the actual gain of the SUT configured as an SHA. The accuracy of Vtest is not critical

because ratio is concerned by observing (5). In other words, the accuracy of Vtest does not induce additional estimated

error for identifying individual circuit parameters. The nonlinearity of the back-end stages may induce additional identification error. To reduce this error, the dc test signal Vtest should be properly assigned. Details on Vtest selection

φ

φ

φ

φ

φ

φ

Fig. 3 Typical switched-capacitor MDAC circuit Residual

+Vref

Vin

−Vref

−Vref −Vref/4 +Vref/4 +Vref

−Vref

Ddiff_tran, ideal

Ddiff_tran, real

+Vref

Fig. 2 Transfer curves of a 1.5-bit/stage MDAC circuit

Table 1 Summary of critical static error sources of an SC MDAC circuit

Error source Item

Gain error source Finite open-loop op-amp gain

Capacitor mismatch

Offset error source Comparator offset

Op-amp offset

are addressed latter. Another critical issue is to separate individual error effects on the SUT output signal. This issue can be solved by properly configuring the SUT. In the following sections, we describe the practical operation of identifying individual error sources in detail.

3.2 Op-Amp Gain

Finite op-amp gain and capacitor mismatch are the main static gain error sources in pipelined ADCs. To retain the finite op-amp error effect while removing the capacitor mismatch between Cf and Cs, SUT is configured as the

topology shown in Fig.5. In sampling phase (ϕ1/ϕ1a), only

Cfsamples the test input signal Vtest, while Csis reset. In the

amplifying phase (ϕ2), Cfis connected to the output, but Cs

is connected to zero voltage. The SUT is configured as an SHA circuit without error effect of capacitor mismatch. The transfer function of this circuit is derived as follows:

Vout¼ KVtestþ KVoff

Cf þ Csþ Cp

Cf



ð6Þ where Voffis the input offset voltage induced by the op amp

and switches and parameter K is defined in (2). Capacitor mismatch (Cs ≠ Cf) does not affect Vout because only Cf

participates in the charge transfer process between sampling

phase and amplifying phase. In addition, digital code differences are employed, as shown in (3) and (4) to eliminate the error effect induced by the output offset, i.e., the second term in (6). Therefore, the offset of SUT does not affect the amp gain identification. The estimated op-amp gain can be derived by using (3)-(6) as follow:

Aest ¼

D_{diff out;A err} CfþCsþCp Cf

 

Ddiff out;ideal Ddiff out;A err ð7Þ

where Ddiff_out,A_errand Ddiff_out,ideal represent digital codes

corresponding to Vdiff_outand Vdiff_test, respectively. The

op-amp gain identification is affected by the ratio of Cs, Cf, and

Cp. Nominal values of Csand Cfare used to identify the

op-amp gain. Cp can be estimated roughly from circuit

simulations. Practical capacitor variation only induces minor identification error.

3.3 Capacitor Mismatch

To identify the capacitor mismatch, the SUT is configured as the topology shown in Fig.6. The SUT is configured as an inverted SHA circuit and Voutis composed of capacitor

mismatch and finite op-amp gain errors. In the sampling phase (ϕ1/ϕ1a), Csand Cfare both reset. In the amplifying

phase (ϕ2), Cs is connected to Vtest but Cf is connected to

φ2 Cf φ1 Vout Cs φ1 Vdac{0, ±Vref} − + φ2 φ1 φ1a Cp Vtest

Vtest Back-end stage

Back-end stage Stage Under Test(SUT)

Dout,err Dout,ideal (a) Step 1 Back-end stage Back-end stage Doutp,err Doutp,ideal SUT Vtest Vout Step 2 Back-end stage Back-end stage Doutn,err Doutn,ideal SUT −Vtest Vout

Ddiff_out,err= Doutp,err − Doutn,err

Ddiff_out,ideal= Doutp,ideal − Doutn,ideal

(b) Fig. 4 a Concept of the

pro-posed diagnosis method and b The testing variables and con-ceptual testing procedures

Vout. The transfer function of this circuit is derived as follows: Vout¼ K Vtest Cs Cf
 þ Voff  Cf þ Csþ Cp Cf
   ð8Þ where K is also define in (2). After the op-amp gain is identified using the method mentioned in Section3.2, the capacitor ratio can be derived using (3)-(5) and (8), as follow:

Cs

Cf



¼  Ddiff out;cap err Ddiff out;ideal

 = 1 1þCfþCsþCp AestCf 0 @ 1 A _ð9Þ

The ratio of Cs/Cfis deviates from the ideal value of one

if capacitor mismatch exists. Nominal values of Cs, Cf, and

Cpare used to identify the capacitor ratio. It is notable that

the capacitor ratio must be identified after the identification of op-amp gain.

3.4 Test Signal Considerations

In the proposed diagnosis method, an ADC comprising back-end stages (called as back-end ADC) is employed to digitize the outputs of the SUT. However, this back-end

ADC could have large nonlinearity, which may cause large identification error. Interestingly, the identification error induced by the back-end ADC can be reduced by carefully choosing Vtest.

We conclude that gain errors in each pipelined stage only induce nonlinearity to their corresponding transition codes in our previous works [9,10]. Figure7shows DNL results of a typical 10-bit 1.5-bit/stage pipelined ADC which each stage has the same and negative gain error (stage gain <2). Large negative DNL values only appear at specific codes, i.e. transition codes [9, 10]. The gain errors in stage 1 only induce high nonlinearity for two specific transition codes, that are 3/8×210 and 5/8×210 when comparator offset does not be considered. The latter stages have more corresponding transition codes and less DNL values.

Figure8shows a concept diagram for the distribution of transition codes corresponding to the first three 1.5-bit stages. (1’, 1”), (2’, 2”), and (3’, 3”) represent the ideal transition codes of the first three stages, respectively.

The comparator offset shifts transition codes of each stage. The gray and black double-arrow lines represent the possible variation ranges for two transition codes of each stage without degrading the ADC linearity, respectively. The tolerable variation ranges for transition codes of the

φ2 ON Cf Vout Cs − + Cp Voff Vout φ1& φ1a ON Cf Cs Vtest − + Cp φ2 Cf φ1 Vout Cs φ1 − + φ2 φ1 φ1a Cp Vtest

Fig. 5 Circuit topology for identifying op-amp gain

φ2 ON Cf Vout Cs − + Cp Voff Vtest Vout φ1& φ1a ON Cf Cs − + Cp φ2 Cf φ1 Vout Cs φ1 − + φ2 φ1 φ1a Cp Vtest

Fig. 6 Circuit topology for identifying capacitor mismatch

required. Therefore, we need 38 switches (8 + 10 + 10 + 10). In practice, we can use I2C interface to upload the corresponding control signal of each switch and store the series-in data. Therefore, we can assume one D flip-flop and four logic gates are required for one switch. In summary, we require 38 switches, 38 D-flipflops, and 152 logic gates. The required die area is determined by specific process. If the proposed method is applied to more stages, the required additional circuits will be increased linearly. In addition, we require test signal generator, as shown in Fig.14. Table4is listed to compare the required hardware of the proposed method with that required in other works [6, 11]. We can find our proposed method only requires switches, digital logic, and simple analog circuits. These circuits are easily implemented in a silicon chip compared with other works.

8 Conclusion

This paper presented a systematic design-for-diagnosis method which can accurately identify the actual values of op-amp gain, capacitor mismatch, op-amp offset, and comparator offset, in each pipelined stage for a pipelined ADC. The stage configuration and response analysis are mainly carried out in the digital domain. Accurate analog test input signals are not necessary. Therefore, the proposed method can be easily applied in realizing built-in self-test/ diagnosis (BIST/BISD). The proposed method can also be applied for various architectures of pipelined ADCs.

Acknowledgment This work was supported in part by the grant of NSC-99-2221-E-151-064- from National Science Council (NSC), Taiwan.

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Hsin-Wen Ting was born in Yunlin, Taiwan, in 1979. He received the B.S., M.S., and Ph.D. degrees all in Electrical Engineering from the National Cheng Kung University (NCKU), Tainan, Taiwan, in 2002, 2004, and 2008, respectively. From 2008 to 2009, he made his military service in CGA. Currently, he is an Assistant Professor in the Department of Electronics Engineering, National Kaohsiung Univer-sity of Applied Sciences (KUAS). His research interests include integrated circuit design and testability design for analog and mixed-signal circuits. In 2006, Dr. Ting received the Macronix Golden Silicon Award. In 2010, Dr. Ting is the co-recipient of the Best Paper Award of VLSI Design/CAD Symposium, Taiwan.

Jin-Fu Lin was born in Changhua, Taiwan, in 1981. He received BS degree from the Department of Electrical Engineering, National Chi Nan University (NCNU), Taiwan, in 2003. He obtained his M.S. degree and Ph.D. degree in Electrical Engineering from National Cheng Kung University (NCKU), Taiwan, in 2005 and 2010. Currently, he is an engineer in the Himax Technologies, Inc., Taiwan. His research interests include low-power ADC design and test.