Discrete dopant fluctuated 20nm/15nm-gate planar CMOS

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208

978-4-900784-03-1 2007 Symposium on VLSI Technology Digest of Technical Papers

11B-3

Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS

Fu-Liang Yang, Jiunn-Ren Hwang, Hung-Ming Chen, Jeng-Jung Shen, Shao-Ming Yu, Yiming Li, and Denny D. Tang

Taiwan Semiconductor Manufacturing Company (TSMC), No. 8, Li-Hsin Rd. 6, Hsinchu Science Park, Hsinchu City, Taiwan, ROC

*Department of Communication Engineering, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu City, Taiwan, ROC

Phone: +886-3-6665152, Fax: +886-3-5637525, e-mail: [email protected]

Abstract

We have, for the first time, experimentally quantified random dopant distribution (RDD) induced Vt standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced Vt variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.

INTRODUCTION

So far, gate length scaling is still the most effective way to continue Moore’s Law for transistor density increase and chip performance enhancement. However, as planar CMOS advances to sub-20nm gates, double-digit channel dopants make transistor behaviors more complicated to be characterized with conventional “continuum modeling”, due to every “discrete” dopant has its significant weight to impact the resulted transistor performance. We herein developed a systematic method to experimentally extract the random dopant distribution (RDD) induced Vt fluctuation. Furthermore, a “discrete-dopant simulation", in good agreement with the experimental data, has been carried out to realize statistical analysis and to feature solutions for reducing the RDD induced Vt variation upon Lg scaling.

EXPERIMENTAL and CHARACTERIZATION

As gate length deviation (GLD), line edge roughness (LER), and random dopant distribution (RDD) are the major variation sources of threshold voltage [1-3], we thus can extract RDD induced

standard Vt deviation,

V

Vt,RDD, from the following approximated

equation as

V

Vt,total,

V

Vt,GLD, and

V

Vt,LER can be directly measured

from experimental data:

(

V

Vt,total)2 § (

V

Vt,GLD) 2+(

V

Vt,LER) 2+(

V

Vt,RDD) 2 (1)

In this work, excellent short-channel-effect control down to 20nm-gate has been experimentally realized (Fig. 1) with advanced shallow junction technology. We achieve junction depth around one half of gate length to maintain subthreshold leakage at 100nA/Pm with channel doping ~5×1018_cm-3_{and gate dielectric of 12Å EOT} (equivalent oxide thickness). Furthermore, to have the insights of random-dopants-distribution effects, quantum mechanical transport simulation is performed and compared with experimental data (Fig. 3) by solving a set of calibrated 3D density-gradient equation coupling with Poisson equation as well as electron-hole current continuity equations [4]. All statistically generated discrete dopants, as shown in Fig. 5 (details in next paragraph), are advanced and incorporated into the 3D device simulation under our parallel computing system. Such large-scale simulation approach allows us to explore the electrical characteristic fluctuations induced by randomness of dopant number and position in the channel region concurrently. The mobility model, shown in Fig. 4, used in the 3D device simulation is quantified with our device measurements for the best accuracy. Fig. 5 illustrates how to generate discrete-dopant channel for aforementioned simulation, concurrently capturing randomness of dopant number and dopant position. Fig. 5(a) shows the discrete dopants randomly distributed in (100nm)3_{cube with average} concentration of 5×1018_cm-3_{. There will be 5000 dopants within the} (100nm)3_{cube, but dopants vary from 24 to 56 (average number is 40)} within its 125 sub-cubes of (20nm)3_{, as shown in Fig. 5(b), (c) and (e).} These 125 sub-cubes are then equivalently mapped into channel region for the discrete dopant simulation (Fig. 5(d)). In principle, device simulation with the 125 channel structures almost covers ±3

V

cases, shown in Fig. 5(e), and thus will be fairly meaningful to reflect statistic randomness of dopant number/position in channel region.

RESULTS and DISCUSSION

x 20nm-Gate Planar CMOS. Fig. 1 and Fig. 2 show the experimental Vt fluctuation and Ion-Ioff characteristics of NMOS transistors down to 20nm gates. As expected, the Vt roll-off characteristics of 20nm-wide devices are much more scattered than that of 200nm-wide devices.

V

Vt,RDD has then been experimentally

extracted following the formula (1), as shown in Fig. 3. Discrete-dopant simulation for Lg = W = 20nm (data represented with symbol

*

in Fig. 3) is in good agreement with the experimental data, which confirms the channel doping is randomly distributed as statistically modeled. Fig. 4(a) shows extracted mobility versus doping concentration from samples of Figs. 3(a) and (b). The low-field electron mobility at 0.3 MV/cm is greatly reduced with increasing doping concentration. That is why we limit our channel doping concentration at 5×1018_cm-3_{, which corresponding to average} 40 dopants in (20nm)3_{cubes and 17 dopants in (15nm)}3_{cubes, as} shown in Fig. 5 and Fig. 8, respectively. Less channel doping concentration may reduce

V

Vt,RDD, but channel dopants will quickly

approach to single-digit number, as shown in Fig. 4(b). Figs. 6(a)-(c) show Ion, Ioff, and Vt,sat distributions versus channel dopants of these 125 cases. Fig. 7(a) shows its Ion-Ioff characteristics. Figs. 7(b)-(d) disclose 3 different discrete-dopant channels which have similar values of Ion or Ioff but with various dopant distributions. Their corresponding cross-sectional off-state electrostatic potential and on-state current density at 1nm below gate oxide are also presented (Figs. 7(b’)-(d’), and 7(b”)-(d”)), which clearly shows that distributions of the electrostatic potential and current density are closely related to the dopant arrangements within the cross-sectional area beside source side (Figs. 7(b)-(d)).

x 15nm-Gate Planar CMOS. Based on experimental data and discrete modeling of 20nm gate with 12Å EOT, 8 Å EOT seems a “must” for 15nm-gate CMOS to mitigate the increase of the RDD induced Vt variation. With the same approach shown in Fig. 5 for generating discrete-dopant channels, Fig. 8(a) shows 343 sub-cubes of (15nm)3_{derived from (105nm)}3_{cube with 5×10}18_cm-3 _doping. Fig. 9 shows the Ion-Ioff characteristics and Vt distribution of these cases with 12Å and 8Å EOT. 8Å EOT shows tighter Vt scattering. Furthermore, as channel dopants could be only 7 at 3

V

edge (Fig. 8(c)), we herein propose using higher work-function gate to increase its intrinsic electrostatic potential barrier height (Fig. 10(c)) to prevent source-to-drain punchthrough at off state (Fig. 10(b)). Thus

V

Vt,RDD can be maintained while Lg scaling down to 15nm from 20nm, as summarized in Table I.

CONCLUSIONS

Random dopant distribution (RDD) induced

V

Vt for 20nm gate has been experimentally extracted and in good agreement with newly developed 3D discrete-dopant characterization. Average 40 dopants randomly distributed in the channel region give rise to

V

Vt,RDD of

40mV. The developed scheme outlooks that 7 dopants under 15nm gate at 3

V

edge will occur and 8Å EOT in addition to work-function-modulated metal gate can suppress the increase of the

V

Vt,RDD for realizing manufacture with such gate length scaling.

Acknowledgements

The authors gratefully acknowledge the managerial support from Jack Y.-C. Sun, Y.-J. Mii, C.-H. Yu, Mong-Song Liang, and Wei-Jen Lo for their instrumental supervision to deploy the development work. This work was also supported in part by National Science Council of Taiwan under Contract NSC-95-2221-E-009-336, Contract NSC-95-2752-E-009-003-PAE, and by the MoE ATU Program under a 2006-2007 grant.

References

[1] F.-L. Yang, et al., Proc. of IEEE CICC 2006, pp. 691. [2] A. Asenov, et al., IEEE Trans. Electron Devices, 2003, pp. 1837. [3] H. Fukutome, et al., IEDM Tech. Digest, 2006, pp. 281. [4] Y. Li, et al., IEEE Trans. Nanotech., 2005, pp. 510.

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2007 Symposium on VLSI Technology Digest of Technical Papers

Fig. 1 Experimental saturation threshold voltage, Vts, of NMOS transistors

with Lg down to 20nm for (a) width=200nm and (b) width=20nm at Vd=1.0V.

0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 (WL)-0.5_(Pm-1₎ V Vt,R D D (m V) : experimental data

*

: discrete-dopant simulation

*

a. b. c. d. EOT

(Å) Doping (cmChannel-3₎ Nom inal_L

g(nm) Width (nm) a. 24 ~1E18 55 1000 b. 18 ~3E18 35 1000 c. 12 ~5E18 20 200 d. 12 ~5E18 20 20 EOT

(Å) Doping (cmChannel-3₎ Nom inal_L

g(nm) Width (nm) a. 24 ~1E18 55 1000 b. 18 ~3E18 35 1000 c. 12 ~5E18 20 200 d. 12 ~5E18 20 20 0 100 200 300 400 500

1E+160 1E+17 1E+18 1E+19 100 200 300 400 500 Doping Concentration (cm-3₎ El ec tr on M ob ili ty (a .u .) Eeff = 0.3MV/cm Eeff = 1MV/cm

EOT = 12 Å, On-State Current Density (Vd= 1.0 V, Vg= 1.0 V)

S D S D S D

EOT = 12 Å, Off-State Potential Contours (Vd= 1.0 V, Vg= 0.0 V)

S D S D S D

47 dopants 37 dopants 35 dopants

27 dopants in a 15 nm cube

7 dopants in a 15 nm cube

5u1018_cm-3_{for 105nm cube}

0 10 20 30 40 50 5 10_{Channel Dopants}15 20 25 30 H is to gr am (n um be r) Average = 17 Standard deviation = 4 29 - 3V + 3V 105nm 15nm 105nm 105nm 5 15nm 24 dopants in a 20nm cube 5u1018_cm-3 5000 dopants in a 100nm cube ~ 40 dopants in a 20nm cube 56 dopants in a 20nm cube 0 2 4 6 8 10 20 30 40 50 60 Dopants in (20nm)3_cube H is to gr am (n um be r) 40 21 59 -3V 40 +3V -3 +3V 100nm 100nm 100nm 20nm Source Extension Gate 20nm Channel doping 5x1018_cm-3 average 40 dopants Channel doping 5x1018_cm-3 average 40 dopants 20nm 20nm Drain Extension EOT=12Å 20nm 0.0 0.1 0.2 0.3 Vts (V ) 0 10 20 30 Channel Dopants EOT = 12Å EOT = 8Å 0.0 0.1 0.2 0.3 Vts (V ) 0 10 20 30 Channel Dopants EOT = 12Å EOT = 8Å 1E+1 1E+2 1E+3 1E+4 0.4 0.6 0.8 1 1.2 1.4 Normalized Ion(a.u.) Ioff (n A/ Pm ) EOT= 12 Å EOT= 8 Å 1E+1 1E+2 1E+3 1E+4 0.4 0.6 0.8 1 1.2 1.4 Normalized Ion(a.u.) Ioff (n A/ Pm ) EOT= 12 Å EOT= 8 Å Lg=W=15 nm, EOT=8 Å

Off-State Potential Contour (Vd= 1.0 V, Vg= 0.0 V)

7 dopants 27 dopants

)N= 4.05eV )N= 4.05eV )N= 4.22eV

7 dopants S D S D S D 0.7 0.8 0.9 1.0 1.1 1.2 1.3 20 30 40 50 60 Channel Dopants N or m aliz ed Ion (a .u .) 0.7 0.8 0.9 1.0 1.1 1.2 1.3 20 30 40 50 60 Channel Dopants N or m aliz ed Ion (a .u .) 1E+1 1E+2 1E+3 1E+4 20 30 40 50 60 Channel Dopants Ioff (n A /P m ) 1E+1 1E+2 1E+3 1E+4 20 30 40 50 60 Channel Dopants Ioff (n A /P m ) 0.0 0.1 0.2 0.3 0.4 20 _{Channel Dopants}30 40 50 60 Vts (V ) 0.0 0.1 0.2 0.3 0.4 20 _{Channel Dopants}30 40 50 60 Vts (V ) 35 dopants 37 dopants 47 dopants S D S D S D 1E+1 1E+2 1E+3 1E+4 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) Ioff (n A /P m ) Dopants < 40 Dopants > 40 35 dopants 37 dopants 47 dopants S D S D S D 1E+1 1E+2 1E+3 1E+4 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) Ioff (n A /P m ) Dopants < 40 Dopants > 40 8 2440 320 (40nm)3 Channel Size D op an t N um be r Na=5E18 Na=3E18 Na=1E18 (30nm)3(20nm)_(15nm)3 3(10nm)3 8 2440 320 (40nm)3 Channel Size D op an t N um be r Na=5E18 Na=3E18 Na=1E18 (30nm)3(20nm)_(15nm)3 3(10nm)3 0 0.1 0.2 0.3 0 50 _L100 150 200 g(nm) Vts (V ) W=200nm 0 0.1 0.2 0.3 0 50 _L100 150 200 g(nm) Vts (V ) W=200nm 0 0.1 0.2 0.3 0 50 100 150 200 Lg(nm) Vts (V ) W=20nm 0 0.1 0.2 0.3 0 50 100 150 200 Lg(nm) Vts (V ) W=20nm (a)

Fig. 6 Distributions of (a) Ion, (b) Ioff, and (c) Vts versus

channel dopants for the 125 discrete-dopant 20nm-gate transistors (Lg=W=20nm)

shown in Fig. 5(e).

Fig. 7 (a) Ion-Ioff characteristics of the 125 discrete-dopant 20nm-gate transistors (Lg=W=20nm).

(b) and (d) represent two cases of channel doping with similar Ion but different Ioff; (c) and (d) represent

two cases of channel doping with similar Ioff but different Ion. The corresponding off-state potential

contours and on-state current density of (b), (c), and (d) are shown in (b’), (c’), (d’) and (b”), (c”), (d”), respectively. All cross-sectional figures of off-state potential contours and on-state current density distributions are extracted at 1nm below 12Å EOT gate oxide.

Table I Summary of discrete dopant fluctuated 20nm/15nm-gate planar CMOS transistors.

Fig. 5 (a) Discrete dopants randomly distributed in (100nm)3_{cube with average}

concentration of 5×1018_cm-3_{. There will be 5000 dopants within the (100nm)}3_cube,

but dopants vary from 24 to 56 (average number is 40) within its 125 sub-cubes of (20nm)3_{, ((b), (c), and (e)). These 125 sub-cubes are then equivalently mapped into}

channel region for dopant position/number-sensitive simulation ((d)). In principle, device simulation with the 125 channel structures almost covers ±3V cases ((e)), and thus will be fairly meaningful to reflect statistic randomness of dopant

number/position.

Fig. 8 5×1018_cm-3_{doped (105nm)}3_{cube, (a), with 343}

sub-cubes of (15nm)3_{. Dopants inside the sub-cubes are}

ranged from 7, (c), to 27, (b), with average number of 17 and one standard deviation of 4, (d).

Fig. 9 (a) Ion-Ioff characteristics and

(b) Vts versus channel dopants of

discrete doped 15nm-gates with EOT=12Å (solid triangle) and 8Å (open circle). Gate work function is 4.22eV in the simulation.

(a) (b) (a) (b) (b) (a) (c) (b) (d) (c) (b) (d) (c) (a) (b) (e) (b) (a) (c’) (b) (a) (d) (c) (a) (b)

Fig. 10 Cross-sectional off-state electrostatic potential contours of two extreme cases in 15nm channels (EOT=8Å, Fig. 8 (b) and (c)) with (a) 27 dopants/)N=4.05eV, (b) 7 dopants /)N=4.05eV, and (c) 7 dopants/)N=

4.22eV; all at 1nm below gate oxide. (a)

(c) (b’) (d’)

(c”) (d”) (b”)

Fig. 3 Experimentally extracted VVt,RDD (random

dopant distribution), and discrete-dopant simulation (

*

, Lg =W=20nm, EOT=12Å) for various devices

with nominal Lg from 55nm down to 20nm.

Fig. 2 Experimental Ion-Ioff characteristics of NMOS transistors with Lg down

to 20nm for (a) width=200nm and (b) width=20nm at Vd=1.0V.

Fig. 4 (a) Extracted non-strain mobility versus doping concentration at 0.3 and 1 MV/cm vertical field, and (b) scaling of average channel dopant numbers versus channel size.

W=200nm 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 Ioff (n A /P m ) 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) W=200nm 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 Ioff (n A /P m ) 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) Ioff (n A /P m ) W=20nm 1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Normalized Ion(a.u.) Ioff (n A /P m ) W=20nm

Lg Width Data Source Gate WorkFunction Doping (cmChannel-3_{) EOT} VVt,RDD

200nm experimental 5E+18 12Å 17mV

20nm discrete simulation 5E+18 12Å 39mV

15nm discrete simulation 5E+18 8Å 41mV

15nm

20nm band-edge

)N= 4.22eV )P= 4.98eV