Modeling and design of the high performance step SOI-LIGBT power devices by partition mid-point method

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Modeling and design of the high performance step

SOI-LIGBT power devices by partition mid-point method

Fang-Long Chang

a,*

, Ming-Jang Lin

a

, Gwo-Yann Lee

a

, Young-Shying Chen

b

,

C.W. Liaw

c

, Huang-Chung Cheng

a

Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC

b_{Industrial Technology Research Institute, Hsinchu, Taiwan, ROC}

c_{Department of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan, ROC}

Received 11 September 2001; received in revised form 12 February 2002; accepted 16 April 2003

Abstract

In this paper, a partition method is proposed to study the high voltage devices with the step doping profile for the first time. It has been proposed that its breakdown voltage can be approached to that of the linearly graded devices with similar forward voltage drop (Vce). In addition, by this method, the breakdown voltage can be deduced and its cor-responding issue location is also fingered out in the step drift region. Furthermore, in order to reduce the undesirable additional masks, the degraded factor (D) is developed to obtain better performance with the least number of frames. Eventually, a 660 V step analytical results are compared with a 606.6 V MEDICI simulation and this shows that the partition method is very effective.

Keywords: Step drift doping proﬁle; Linearly graded doping; SOI-LIGBT

1. Introduction

In recent years, Silicon-on-Chip (SOC) has been de-voted to develop. In respect of the high power applica-tions, Silicon-on-Insulation (SOI) is the promising candidate in this field, because of its superior isolation characteristic to the Junction Isolation (JI) devices, re-ducing the LIGBT turn-off time with thin SOI layer, and increasing the blocking voltage under well-RESURF design. For low power SOI applications, it provides immunizing from the ionization via radiations, reducing parasitic capacitances, short-channel effects, hot-carrier effects, and static power consumption.

The SOI devices have two main problems, which must be addressed significantly, such as self-heating ef-fect and lower breakdown than JI devices. The latter problem is even greater concern. This is due to the native ineffective RESURF effect in SOI layer. To achieve high breakdown voltage, a linear doping profile in the drift region is necessary to provide a more uniform electrical field distribution along the drift region and so to opti-mize the RESURF condition [1].

Using a Variation in Lateral Doping (VLD) tech-nology in a sequence of small opening oxide slits, which can achieve the linearly graded doping profile to relax the two-dimension electrical-field effect and bring lower on-resistance with high breakdown voltage in the drift region. Unfortunately, there are two drawbacks of this structure: Firstly, the linearly graded doping profile needs complicated mask layout to be fabricated. Fur-thermore, it is difficult to know whether the doping profile is certainly satisfied [2]; Secondly, the local self-heating is arose near the lightly doping side and it

*

Corresponding author. Address: Department of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan, ROC. Tel.: +886-3-5712121-54218; fax: +886-3-5738343.

E-mail address:[email protected](F.-L. Chang).

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influences the reliability of surrounding low power cells on the same chip [3]. At present, when replacing the linear profile by the distinct doping region along lateral direction [4], the separated uniform doping can effec-tively avoid the former descriptions and can be easily realized by different implant dosages. Nevertheless, the additional mask of the step doping case is a serious problem in the cost aspect. Hence, this paper is to offer a choice of either increasing the masks with step doping or longer thermal process with linearly graded doping for designs.

2. Modeling descriptions and veriﬁcations

While deriving an n-separate frames in drift region, as shown in Fig. 1, the neighborhood frame with a previous frame is conjugated to ﬁnd its individual boundary parameters. Assuming that the SOI layer is completely depleted and the buried oxide is charge-free, the frame 2-D Poisson equation is given with a parabolic approximation approach [5] o2_w o2_xþ o2_w o2_y ¼ qN esi ; ð1Þ and

wðx; yÞ ¼ uðxÞ þ u1ðxÞy þ u2ðxÞy2; ð2Þ

Eyðx; 0Þ ¼ owðx; yÞ oy y¼0 ¼ 0; ð3Þ Eyðx; tsÞ ¼ owðx; yÞ oy y¼ts ; ð4Þ

where uðxÞ is the surface potential at y ¼ 0 and ‘‘N ’’ is the concentration of each frame. From Eqs. (1)–(4) and the continuity of the displacement vector at the Si/SiO2 surface, the potential can be simpliﬁed to be

wðx; yÞ ¼ 1 0 B B @ y2 2ts ts 2þ esi eox tox 1 C C AuðxÞ; ð5Þ

where the diﬀerential of Eq. (5) is its electrical ﬁeld. Substituting Eq. (5) into Eq. (1), the surface potential equation can be expressed as

1 0 B B @ y2 2ts ts 2þ esi eox tox 1 C C Ao 2_uðxÞ ox2 uðxÞ ts ts 2þ esi eox tox ¼ qN esi ; ð6Þ

where the top of SOI layer is set at y¼ 0. Assuming that mth frame (m) has existed at n-separate (n) frames. Each frame concentration (N ) is the mean value of the linearly graded slope (a), which is spread into the individual frame. The relationship of its position and concentration (N ) are mL=n, að2m 1ÞL=2n, respectively. According to the quasi-neutral drift region under low-level injection condition, the surface potential of the mth frame in reach and non-reach boundary condition is given um ðm 1ÞL n ¼ Vm1; um mL n ¼ Vm; ð7Þ umw ðm 1ÞL n ¼ Vm1; u0mwðwmÞ ¼ 0; ð8Þ where ‘‘w’’is presented as the non-reach through length. The corresponding voltage is called the non-reach through voltage umw. Hence, combining Eqs. (7) and (8) with Eq. (6), the surface potential uðxÞ will be solved while the value of y¼ 0 is substituted. As the applied voltage increases, the impact ionization rate will deter-mine whether the non-reach through of the mth frame can eventually deplete to the end. With deducing its ionization integral over the horizontal and vertical sur-face path, the mth frameÕs breakdown testing equation deﬁned as [6]

IHorimðwÞ¼ Z mL=n

½ðm1ÞL=n

½AðjExðwÞðx; 0ÞjÞ7 dx; ð9Þ

Fig. 1. Corresponding structure and frame architecture of step SOI-LIGBT device. The concentration of the ﬁrst frame is equal to the background doping which is also replicated from p-well to gate edge.

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IVertmðwÞ¼ Z ts

0

½AðjEyðwÞðK; yÞjÞ7 dy þ Z mL=n ½ðm1ÞL=n ½AðjExðwÞðx; tsÞjÞ7 dx; ð10Þ where K¼mL n or w; ð11Þ

A¼ 1:8 1035 _{when Eðx; yÞ is expressed in V/cm [7].} ‘‘IHori’’ and ‘‘IVert’’ is the lateral and vertical impact ionization rates. To simplify the analysis, only consider the two high-field locations are considered: (1) the first frames along y¼ 0, where ‘‘IHori’’ is high and (2) the last frame at point (x¼ K; y ¼ ts), where ‘‘IVert’’ is high. Moreover, the critical electrical field and potential of the mth frame are obtained as one of the value ‘‘I’’ approaches to the value 1. To make a summary, the mth frame-testing flowchart described above is illustrated in Fig. 2.

In order to achieve higher breakdown voltage, the diﬀerence between maximum and minimum electrical ﬁelds must be eliminated in each frame. For this reason,

a degraded factor ‘‘D’’ is provided to ensure near ideal-breakdown voltage as expected. It can be written as D¼ Exp½x=t þ Exp½ðx L_Þ=t; _ð12Þ where t¼ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ts ts 2þ esi eox tox s ; ð13Þ L¼L n; ð14Þ

this factor ‘‘D’’ include SOI layer thickness (ts), buried oxide thickness (tox), frame length (L_{), and the number} of frames (n). Among these the optimum structure pa-rameters will be found at approaching D¼ 1. To sim-plify the mathematics in solving Eq. (10), it is convenient to assume the minimum electrical ﬁeld is located in the coordinate of x¼ L_{=2. In place of the x-coordinate, the} general solution is D¼ 2 Exp L 2nt 6_1; _ð15Þ nP L 2 t ln 2; ð16Þ

where the number of frames (n) is proportional to drift length (L) and inversely proportional to the term ‘‘t’’–– associated with the buried oxide and SOI layer thickness. It is apparent that the thicker buried oxide and shorter drift length will promote smaller number of frames, es-pecially if the SOI layer thickness is large enough. This makes it possible to reduce production cost. A relation-ship of breakdown voltage and degraded factor is demo-nstrated in Fig. 3. The value 0.6 is corresponding to the

Fig. 2. Illustration of the partition method with a testing ﬂowchart and single frame diagram. The key point is to de-termine whether the applied voltage will attain reach-through-out for each frame.

Fig. 3. Dependence of the breakdown voltage and frame number with degraded factor. The improvement of breakdown voltage is enough to use three frames in the drift region.

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‘‘three frames’’, which is chosen under economical con-sideration.

In this methodology, an algorithm is developed to obtain systematic n-separate frames cogitation. In the first part, the user is demanded to offer some funda-mental parameters that comprise the drift length (L) with respond to linearly graded slope definition (a) [8]. Then, the algorithm works are listed as follows: (1) Set up the structure parameter from the degraded

factor (D).

(2) By dint of the ﬂowchart in Fig. 2. Each frame elec-trical and potential function can be obtained step by step. The n-separate frames will donate 2n states that include reach and non-reach through case. If some frame breaks down during examination, the program will be claimed to stop.

(3) Be sure that each frameÕs electrical and potential function comprises not only device dimension pa-rameters but also its neighbor boundary value. (4) Start from the left side zero point and equalize its

in-dividual functional equation with its neighbor frame equation. Substitute all derivational boundary value into the next unknown frame equation to evaluate its unknown electrical and potential value in turn. Then these frames boundary values are functions of V1eventually (xm¼ xmþ1; xmþ1¼ xmþ2; . . .). (5) Substitute the desired breakdown voltage into the

ﬁ-nal value ‘‘V ’’. Then the value ‘‘V1’’ will be gained, so every boundary condition value can be discovered from the right-side to left-side.

In the following, the breakdown voltage, weak-point, optimum design parameters, and low-cost way are taken systematically.

3. Results and discussion

In this section, a numerical example of this analysis is demonstrated. The data of the example is 600 V linearly graded SOI devices, whose specification is as follows: ts¼ 1:5 lm, tox ¼ 5 lm, L ¼ 36 lm, slope ðaÞ ¼ 5:05 1018_cm4_{. As the result of statistics, the required} degraded factor (D), ranging from 0.5 to 0.7, is enough to achieve high breakdown voltage. So the value 0.6 is chosen such that three frames can be obtained under this economical mode. Fig. 4 shows the electricity of various partition frames, linearly graded, and uniform type for comparison. In this figure, the breakdown voltage of three-frame (607 V) is indeed nearly close to the linearly graded device (617 V) at similar Vceof 12 V-gate bias at 100 A/cm2_{. However, the deviation of the graded doping} Vceis caused by the different concentration between the p-well and the gate edge.

Moreover, for further comprehension, the three frameÕs electrical and potential-matching curves are il-lustrated in Fig. 5(a) and (b) with the fully reach through case. Its general equations for the electrical ﬁeld are gi-ven below: ExI¼ a ðb 6V1esiÞ cosh x t b cosh L=3 x t ; ð17Þ ExII¼ 3a ðb 2V2esiÞ cosh L=3 x t þ ð2V1esi bÞ cosh 2L=3 x t ; ð18Þ ExIII¼ a ð5b 6V esiÞ cosh 2L=3 x t þ ð6V2esi 5bÞ cosh L x t ; ð19Þ where 0 6 I 6L 3; L 36II 6 2L 3 ; 2L 3 6III 6 L; ð20Þ and a¼ð2f 2_y2_Þ 12t3_e si cosh L 3t ; ð21Þ b¼ aqt2 L; ð22Þ

where the relationship between V1 and V2can be found from the algorithm in the fourth item. As pictured in

Fig. 4. Investigation of the optimum device characteristics in respect of breakdown voltage and forward voltage drop with various number of frames. Its SOI layer thickness, buried oxide thickness, and the drift length are 1.5 lm, 5 lm and 36 lm respectively.

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Fig. 5(a), the step doping devices exhibit 3 times im-provement of the middle electrical ﬁeld with the uniform doping type and 0.75 times less than that of the linearly graded doping devices. These simulated results are compared to analytic data, that showing good qualita-tive and quantitaqualita-tive agreement in Fig. 5(a) and (b). In these veriﬁcation regulations, the highest impact ion-ization rate is found at the third (last) frame, where the value ‘‘IVert’’ is about 0.9 while substituting the voltage 660 into the value of ‘‘V ’’. The breakdown voltage is over the prediction with only about 8.9% of the ME-DICI simulation value.

In respect of step doping device reliability, the devi-ation percentages would be provided between analytical

model and MEDICI simulation, illustrated in Fig. 6(a) and (b). As presented in these figures, the ranges of data variation are available from)5% to 5% in surface po-tential part and)20% to 20% in surface electrical field part. The deviation of surface electrical field become more severe than that of potential exhibition due to the differential at the corner of each frame, where exists the transitional tangent lines relative to high peak electrical value. Moreover, the positions of frame boundary are located accurately in each frame with this method.

It should be emphasized that the point of 20 lm distance indicates a large surface potential deviation in Fig. 6(b). The reason is that initial solution of the ana-lytical model is set up the zero voltage value at the poly

Fig. 6. (a) Percentage of the surface electrical ﬁeld deviation as a function of the distance in three frames. Each neighbor frame at their boundary exist a higher error value. (b) Percentage of the surface potential deviation as a function of the distance in three frames. It is worth to mention that the maximum error value is occurred on the outset.

Fig. 5. (a) The different kinds of surface electrical field distri-bution are shown in each drift region before the breakdown voltage happens. The step doping type exhibits a significant electrical improvement compared to the uniformly doping type. (b) Comparison of the surface potential distribution with ana-lytical model and MEDICI simulation. The anaana-lytical result is most in agreement with the data generated by MEDICI simu-lation.

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gate edge (20 lm). But in the MEDICI simulation, the zero value of the origin point is situated at the p-well edge (15 lm). It is allowed to modify the initial solution if you prefer to obtain less deviation at the origin point, but the modiﬁed initial solutionð0 V ) 6 VÞ would not aﬀect the previous consequence of this paper more se-riously.

4. Conclusion

In this paper, the use of partition method is successful to explain the underlying reverse-bias performance, at-tain 50.7% improvement of the breakdown voltage compared with the uniform doping, and decrease the undesirable additional masks in the step doping SOI devices. It can also be implemented in the vertical devices by multi-epitaxy or multi-implanted technology without any additional masks, and superior device characteristics can be achieved as well. In summary, this method oﬀer the designers with a choice between the step doping quired more mask and the linearly graded doping re-quired longer thermal process ﬂexibly.

Acknowledgements

This research has been supported by the National Science Council of Taiwan under Contract NSC 90-2215-E-009-074. The authors thank National Center for

High Performance Computing (NCHC) for providing MEDICI software and the Industrial Technology Re-search Institute (ITRI) for helpful discussions.

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