Shu-Yu Hsu, Jui-Yuan Yu, and Chen-Yi Lee
Abstract—This brief presents an all digitally controlled
oscilla-tor (DCO) design with two newly proposed hysteresis delay cells (HDCs) for wireless body area network applications. According to circuit topologies, the two HDCs are defined as on–off and cas-caded HDCs that provide various propagation delay values. These HDCs form a simple oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture. Each delay stage pro-vides half of the delay of the previous delay stage in descending order, enabling low-power and small-area features. The P2-DCO is verified in a 90-nm CMOS technology for wide operating fre-quencies with area of 80 μm× 80 μm and least significant bit resolution of 2.05 ps. With a supply voltage of 1.0 V, the measured dynamic power values are 5.4 and 166 μW at 3.4 and 163.2 MHz, respectively.
Index Terms—Digitally controlled oscillator (DCO), hysteresis
delay cell (HDC).
I. INTRODUCTION
R
APID wakeup time reduces wasted system power during the settling period, particularly for power and low-system duty-cycle applications. The wireless personal area network [1] and wireless body area network (WBAN) [2] applications typically perform a system duty < 1% that requires fast wakeup for burst data transmission and goes to sleep right away for best power savings. Accordingly, the settling time of a clock generator or a phase-locked loop (PLL) that determines the time from system sleeping to the active state becomes a critical parameter in system power optimization.The reference frequency fREF to a PLL, however, is a tradeoff between its settling time and system power reduction. A tens-of-kilohertz quartz crystal as a frequency reference may result in 100 μs to even 1 ms to enable the system from sleeping to operation [1], [12], which can be equal to the duration of a system’s active period. This problem can be solved by using a megahertz-scale frequency fREF, because the settling time is inversely proportional to fREF [12]. Although higher fREF effectively reduces the settling time, this frequency reference
Manuscript received June 11, 2010; revised August 22, 2010; accepted October 11, 2010. Date of publication December 3, 2010; date of current version December 15, 2010. This work was supported in part by the Ministry of Economic Affairs of Taiwan under Grant 97-EC-17-A-03-S1-005. This paper was recommended by Associate Editor P.-I. Mak.
The authors are with the Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: fishya@si2lab.org).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2010.2087991
leads to increased and continuous operation power, even in the sleeping state.
Accordingly, this brief is to develop a digitally controlled oscillator (DCO) in a megahertz-scale frequency (e.g., 5 MHz) with sub-10 μW that minimizes both the system sleeping power by a low-power clock source and the system wakeup power by the reduced settling time.
The DCO, which is widely applied for all-digital clock generation and frequency synthesis [3]–[5], has become an appropriate clock source for low-power and highly integrated WBAN applications [2]. Instead of the utilization of a con-ventional voltage-controlled oscillator, the DCO possesses the merits of easier porting between different process and voltage scaling with a lower supply voltage. Meanwhile, the all-digital approach minimizes the test, control, and integration efforts. Nevertheless, the DCO power dissipation with a megahertz-scale frequency is still the major bottleneck.
There have been several DCO architectures proposed in the literature. The LC-tank DCO achieves excellent phase noise performance, whereas the wireless sensor node often relaxes the phase noise requirement for more power reduction [14]. The current-starved DCO [6] provides fine delay resolution but features high static power consumption. The standard-cell-based DCO [2], [5] with straightforward delay elements, buffer/inverters, or or-and-inverter logic cells presents high power and poor linearity with insufficient delay resolution. The digitally controlled varactor [7] improves delay resolution but with similar power scale. Therefore, a hysteresis delay cell (HDC) [8] was first proposed for trading off between power and delay resolution. This HDC consists of several standard cells with delay range as multiple inverters, but the resulting power saving is still limited. In addition, all the aforementioned DCOs consume more than 100 μW power, resulting in higher system sleeping power and confining use to low-power WBAN applications.
Consequently, this brief presents two novel HDC circuit topologies (on–off and cascade) and a power-of-2 delay stage DCO (P2-DCO) architecture for power-restricted WBAN ap-plications. Both features possess high power and area efficiency and accordingly overcome the challenge in DCO power reduc-tion, particularly in a sub-10-MHz design.
This brief is organized as follows. Section II gives an overview of the proposed DCO design. Section III presents the proposed HDC cells designed for coarse- and fine-tuning stages. Section IV shows the experimental results and compar-isons. Finally, Section V concludes the results.
Fig. 1. P2-DCO architecture.
II. DCO ARCHITECTURE
A. Overview
Fig. 1 illustrates the architecture of the proposed P2-DCO, which includes one coarse-tuning stage and two fine-tuning stages. In each tuning stage, the delay segment is designed in power-of-2 descending order. Therefore, each delay segment generates half of the delay of the previous delay segment. This power-of-2 approach is modeled as
Delayk = 2· Delayk−1 (1)
where Delaykis the propagation delay of the kth delay segment within a tuning stage. Moreover, this architecture exempts the need for an additional codeword decoder, which is conventional in the state-of-the-art DCO designs.
The coarse-tuning stage and the first fine-tuning stage are cascaded together based on the ring oscillator structure, whereas the second fine-tuning stage is appended to delay segments’ inputs in the coarse-tuning stage. The cascaded HDC (CHDC) and the on–off HDC (OHDC) are utilized in the coarse-tuning stage and the first fine-tuning stage, respectively. Furthermore, in the second fine-tuning stage, the MOS gate capacitance (MGC) is applied for further fine-tuning.
B. Coarse-Tuning Stage
The coarse-tuning stage defines the DCO operation range with multiple delay segments. Each segment comprises CHDCs for delay purposes and the multiplexers for signal propagation path selection. The power-of-2 behavior is accomplished by cascading CHDCs in different numbers or using CHDCs with different delay values. Furthermore, AND gates are used for CHDC input isolation when the CHDC is not in the signal propagation path. Consequently, the redundant power dissipa-tion can be effectively cut down through this isoladissipa-tion.
C. Fine-Tuning Stage
The fine-tuning stage is applied for DCO resolution en-hancement. In order to achieve finer resolution, AND gates and multiplexers are eliminated in the first fine-tuning stage. Instead, two topologies of OHDCs with switch capability are performed as the delay elements.
Fig. 2. CHDC.
The second fine-tuning stage utilizes the MGC to generate a picosecond-scale delay from a variant combination of output capacitance loading. The gate capacitance is also arranged in a power-of-2 order by increasing the transistor gate width or combining transistors in multiple.
III. PROPOSEDHDCS
The Boolean function of HDCs is the same as that of a normal inverter, except that HDCs have the hysteresis property. This hysteresis phenomenon induced by a Schmitt trigger has been discussed for low-power operations [9], [10]. Based on the basic structure, this brief further utilizes the low-power property and proposes two HDC topologies to get higher power efficiency and a wide delay range for DCO design.
A. CHDC
The CHDC provides a delay that is tens of times larger than the delay of a minimum-sized inverter in the same manufactur-ing technology. Meanwhile, a large short current is avoided for low-power purposes.
A general form of the CHDC can be regarded as a chain of internal inverters with a header, a footer transistor, and feedback connections, as shown in Fig. 2. This combination results in a hysteresis effect that the header and the footer are barely turned on at the same time. Because of the hysteresis phenomena, the internal voltages Vpand Vnare deduced from [9]
Vn|MPhA=ON= [Vin+Vtn·(Rn− 1)+VSS· Rn] /(Rn+ 1)
Vp|MNfA=ON= [Vin−|Vtp|·(Rp− 1)+VDD·Rp] /(Rp+1)
(2) where Rn= (βMNfA/βMNi1)1/2, and Rp= (βMPhA/
βMPi1)1/2, with the transconductance β. Vtn and Vtp denote
the NMOS and PMOS threshold voltages. In addition, Vpand
Vn are equal to VDD and VSS when MPhA and MNfA are turned on in the linear region, respectively. As a result, voltage scaling is equivalently applied on the internal inverter chain with a lower experienced supply voltage VDD |MPhA=ON=
VDD− Vn or VDD |MNfA=ON= Vp− VSS. This voltage
scaling not only reduces power consumption but also contributes to a longer propagation delay. The average propagation delay tDwith a lower experienced supply voltage,
therefore, can be approximated to
tD≈ S r=1 CL 2VDD 1 βMPir + 1 βMNir (3)
Fig. 3. (a) OHDC-LD. (b) OHDC-SD.
where r, S, and CLare the index, total number, and output
load-ing of inverters within the internal inverter chain, respectively. Because of lower VDD induced by the hysteresis phenomenon, a sufficient long delay is generated with a constrained low short-circuit current.
B. OHDC
The OHDC generates a delay resolution that is several times the delay of a minimum-sized inverter. In addition, the OHDCs with hysteresis on–off switch capability eliminate the use of path-selection elements and perform a tradeoff between power and resolution.
Fig. 3 illustrates two general forms of the OHDC, which are the long-delay OHDC (OHDC-LD) and the short-delay OHDC (OHDC-SD) with different delay ranges. By adding two controlling transistors MPcB and MNcB, the OHDC can be switched as a normal inverter chain or a hysteresis delay chain. Therefore, the OHDC generates finer resolution from the delay difference between these two modes and benefits from the power reduction in the hysteresis mode.
Both OHDCs operate as normal inverter chains with a similar propagation delay value when controlling transistors MPcB and MNcB are turned on. Meanwhile, this higher internal voltage
implies that Vpand Vnare close to VDDand VSS, respectively. On the other hand, the OHDCs remain as Schmitt triggers while the transistors MPcB and MNcB are off. The internal voltages
Vpand Vn of the OHDC-LD can be found in (2); in addition,
Vpand Vnof the OHDC-SD are expressed as [10]
⎧ ⎪ ⎪ ⎨ ⎪ ⎪ ⎩ Vn|MPhA=ON = VDD−Vtn−Rn(Vin−VSS−Vtn), Vp|MPhA=ON≈VDD Vp|MNfA=ON = Rp(VDD+Vtp−Vin)+(VSS−Vtp), Vn|MNfA=ON≈VSS (4) where Rn= (βMNfA/βMNfC)1/2, and Rp= (βMPhA/
βMPhC)1/2. This produces a smaller propagation delay than
the delay of the OHDC-LD. Furthermore, the additional transistors MPcD and MNcD prevent the potential short current paths and balance the rise and fall time currents, resulting in improved jitter performance.
Consequently, the delay resolution of both OHDCs is equal to the delay difference tDiff between the ON- andOFF- states
and can be approximated to
tDiff≈ S r=1 CL 2 1 βMPir + 1 βMNir 1 VDD − 1 VDD− VSS (5) where VDD and VDD− VSS are the experienced supply volt-ages in the hysteresis and normal inverter modes, respectively. As a result, the OHDC provides finer delay resolution than (3) that the hysteresis cell is simply used as a delay element.
IV. EXPERIMENTALRESULTS ANDCOMPARISON
The proposed P2-DCO with novel HDCs is evaluated and fabricated in a 90-nm 1-poly 9-metal CMOS technology. The published approaches are also rebuilt in the same technology for performance comparison.
The P2-DCO power performance can be analyzed by the power and delay characteristics of delay cells. The output period T is synthesized by the turned-on delay cells, which implies that the DCO dynamic power Pd,DCOis proportional to
the total consumed energy within the used delay cells(Dk·
Pd,k) divided by the total delay
Dk. A general expression is given by Pd,DCO∝ k (Dk· Pd,k) k Dk = k (Dk· Pd,k) T /2 = 2 k (Rk· Pd,k) (6) where the delay ratio Rk = Dk/T . Note that Pd,DCO is not a
function of its operating frequency because only part of cells in the delay chain are activated to accumulate the required delay value. Thus, Table I further summarizes the HDCs in this design based on simulation results and compared with [8] with standard cells. The HDCs consist of different numbers of internal inverters and show various delay values. In addition, the proposed cells reduce power consumption to a minimum of 10%, 29%, and 89% of the original power in the coarse-tuning stage and the two fine-coarse-tuning stages, respectively. To evaluate the proposed cells, Fig. 4 illustrates the measured P2-DCO power dissipations. Power consumption tremendously decreases with longer output period as the largest delay time is dominated by the most power-to-delay efficient HDCs (larger
Rk with smaller Pd,k) in the delay path. In contrast with the
Fig. 4. DCO power comparison.
Fig. 5. Comparison of power-to-delay and area-to-delay ratios. TABLE II
COMPARISONSBETWEENLINEAR ANDPOWER-OF-2 APPROACHES
simulated for comparison. The simulation result shows that its power consumption is fixed at the same power level with different periods due to the use of identical delay cells.
Generally, the most DCO area is occupied by the coarse-tuning stage to provide a sufficient long delay duration. As a result, Fig. 5 further emphasizes the area and power savings compared with standard cells used in [8]. The proposed CHDCs maximally reduce to a 79% area-to-delay ratio, resulting in smaller DCO area occupation. Some OHDCs exhibit a lower area-to-delay ratio; however, power reduction is the prior con-cern. On the other hand, the power-of-2 feature minimizes the usage of delay cells and path-selection units in each delay segment, thus implying less area and also less power. For instance, Table II compares the simulation results between the linear DCO approach [8] and the proposed P2-DCO approach at a 5-MHz target frequency. The delay line in the linear DCO requires 2047 AND gates to achieve the target delay D (half-period) and 2047 multiplexers for delay path selection. Contrarily, the P2-DCO requires only eight delay segments, eight multiplexers, and eight AND gates used in the
coarse-tuning stage. In addition, the required delay stages and multi-plexers are proportional to O(D) and O(2D) in the linear DCO case, respectively. However, both required delay segments and multiplexers are proportional to O(log2(D)) in the P2-DCO case. Accordingly, the required W/L is summarized, and the
Fig. 6. Microphotograph and layout of the P2-DCO test chip. TABLE III
MEASUREMENTRESULTS OF THESTEP/RANGE OF THETUNINGSTAGE
Fig. 7. Measured P2-DCO period in the coarse-tuning stage.
Fig. 8. Jitter histogram of the P2-DCO at 5 MHz.
P2-DCO approach shows a 79.7% area saving and a 94.7% power reduction, as compared with the linear approach.
A test chip is designed based on the required frequency range and resolution. The coarse-tuning stage includes eight delay segments with the DCO delay step from 1 to 128 ns. Each delay segment is a combination of three CHDCs with a power-of-2 or-der. To ensure the functionality in various design corners, each fine-tuning stage covers at least 1–2 least significant bits (LSBs) of the previous tuning stage. The overlapped range depends on the cell sensitivities to the process–voltage–temperature variation. The first fine-tuning stage, containing combinations of four OHDCs, are utilized to generate the delay step from 64 ps to 2 ns. The second fine-tuning stage produces the DCO delay step from 2 to 64 ps with MGCs.
Fig. 6 shows the microphotograph and layout of the test chip. The P2-DCO occupies an area of 80 μm× 80 μm and is integrated for WBAN applications. The DCO output signal is measured using a LeCroy SDA4000A oscilloscope at 1.0 V/ 25◦C (with 3.3-V input/output pad supply voltage) to evaluate
the performance. Table III lists the measured least delay tuning step and operation range of each tuning stage in the proposed P2-DCO. The controllable range of each tuning stage is larger than the least DCO delay step of the previous stage; thus, the functionality is guaranteed. In addition, Fig. 7 shows the measurement result in the coarse-tuning stage to analyze the linearity and operation range of the proposed P2-DCO. Fig. 8 shows that the root-mean-square (RMS) phase jitter is 49.30 ps at 5 MHz under 1-V and 40-mV supply noise. This RMS phase jitter is equivalent to−105 dBc/Hz phase noise performance with a 100-kHz offset frequency [13] and complies with WBAN requirements.
Table IV lists the comparison results of the P2-DCO with the state-of-the-art oscillator designs. The P2-DCO provides the least dynamic power consumption (5.4 μW at 3.4 MHz, 166 μW at 163.2 MHz, measured by the difference of the DCO
ONandOFFcurrents) with the least area occupation.
Addition-ally, the proposed HDCs designed in the format of standard cells are compatible with automated computer-aided design tools and, therefore, save design efforts in system integration.
V. CONCLUSION
This brief proposes the on–off and CHDC circuit topolo-gies for low-power DCO design. Accompanied with the power-of-2 structure designed in all-digital methodology, these features demonstrate the feasibility of improved power-to-delay and area-to-power-to-delay ratios compared with the state-of-the-art designs. Accordingly, the proposed P2-DCO achieves a megahertz-scale frequency with sub-10-μW power con-sumption, which minimizes both the system sleeping power and wakeup power. As a result, this brief provides an area/ power-efficient solution for a clock source in low-power WBAN applications.
ACKNOWLEDGMENT
The authors would like to thank their colleagues within the SI2 Group, National Chiao Tung University, for fruitful
discussions. The authors would also like to thank UMC for test chip fabrication.
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