A Fully Integrated BIST
ADC Using the
In-Phase and Quadrature Waves Fitting Procedure
Shao-Feng Hung, Student Member, IEEE, and Hao-Chiao Hong, Senior Member, IEEE
Abstract— This paper demonstrates a fully integrated
built-in self-test (BIST) analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response ana-lyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST ADC has been fabricated in 0.18-μm CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs.
Index Terms— modulation, ADC test, analog and
mixed-signal (AMS) test, analog-to-digital converter (ADC), built-in self-test (BIST), design-for-self-testability (DfT).
I. INTRODUCTION
MODULATION is a very popular technique for implementing high-resolution analog-to-digital con-verters (ADCs). With its oversampling and noise-shaping capability, the ADC provides a high signal-to-noise-and-distortion ratio (SNDR) with the robustness against process, voltage, and temperature variations. Conventionally, testing such a high-resolution ADC is very costly and troublesome because it requires high-end analog and mixed-signal (AMS) automatic test equipment (ATE) and a low-noise test environ-ment [1], [2]. However, the required external test resources are not available in various applications. 3-D ICs are examples.
Manuscript received September 26, 2013; revised January 22, 2014; accepted March 24, 2014. Date of current version November 6, 2014. This work was supported by the Ministry of Science and Technology, Taiwan, under Grant NSC 102-2221-E-009-186. The Associate Editor coordinating the review process was Dr. Niclas Bjorsell.
The authors are with the Department of Electrical and Computer Engi-neering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: sfhung.ece96g@g2.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIM.2014.2322714
3-D ICs are considered one of the emerging techniques for implementing the next-generation ICs [3] because of increased functional density, decreased power, more compact volume, reduced signal latency, and so on. [4]. However, the 3-D structure also leads to new test challenges [5], [6]. The main issues of testing 3-D ICs are the reduced controllability and observability due to the lack of accessible I/O pads. From this testing point of view, the circuits under test incorporated with some on-chip design-for-testability (DfT) or built-in self-test (BIST) functions are highly demanded.
Many BIST techniques for memory and digital circuits have been proposed and adopted in industry [7]–[9], yet those for ADCs are fewer. Among various BIST designs for ADCs [10]–[14], the functional-test-based BIST approaches are very appealing because they are promising to provide standard ADC characteristics as conventional test methods do. The functional-test-based BIST scheme generally consists of two substantial blocks: an analog stimulus generator (ASG) and an output response analyzer (ORA). The success of a BIST design heavily relies on high test accuracy and a low hardware cost.
Converting a pulse-density-modulated (PDM) bit-stream to an analog stimulus is a cost-effective approach for imple-menting the highly accurate ASG [15]–[21]. Reference [15] proposed such an ASG that provides high-quality and well-controlled analog stimuli with a small hardware. The ASG is composed of a digital oscillator, a one-bit DAC, and a passive anti-aliasing filter (AAF). The digital oscillator embedded with a digital modulator generates a PDM bit-stream output, which is converted to a continuous-time analog stimulus by the one-bit DAC and the AAF. However, the discrete-time to continuous-discrete-time conversion asks for a bulky AAF to provide steep and high stopband attenuation. Implementation with passive components also limits its driving capability. References [18]–[21] used an alternative way to implement the ASG. Although their inputs are also PDM bit-streams, these designs adopted the one-bit digital-to-charge converters (DCCs) to convert the PDM bit-streams into discrete-time analog stimuli instead of continuous-time ones to eliminate the bulky AAF. For example, the experimental results of a second-order modulator in [18] depicted the design-for-digital-testability (DfDT) scheme was able to test for a 84.4-dB dynamic range (DR) at an oversampling ratio (OSR) of 128 while the hardware overhead is negligible.
On the other hand, conventional ORA designs are fast Fourier transform (FFT) or histogram analysis-based [22]–[26]. However, the hardware requirements of both
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Fig. 1. Block diagram of the proposed BIST ADC.
analysis methods are too high to integrate the whole BIST system on the same chip. It is because the FFT algorithm needs a lot of memory to store all the samples and the histogram analysis method needs a large counter array for analysis. To the best of our knowledge, reference [21] presented the first fully integrated BIST ADC, which is based on the modified controlled sine wave fitting (CSWF) procedure. The DfDT scheme combined with the digital oscillator in [15] imple-mented the ASG. The modified CSWF procedure processes the ADCs output samples in real time without storing all of them. Therefore, the ORA consists of just 13.3 k gates. Experimental results demonstrated that the BIST design achieved a good test accuracy for low stimulus frequencies, but had larger SNDR errors at higher stimulus frequencies. The reason is that the design assumed the modulator under test (MUT) has a fixed phase shift regardless of the stimulus frequency to simplify the BIST hardware. In practice, the phase shift of modulators varies with the stimulus frequency. The inaccurate phase information at high stimulus frequencies leads to significant SNDR errors and thus limits the BIST bandwidth. For the case in [21], the test bandwidth was 17 kHz out of a 20-kHz rated bandwidth.
This paper proposes a novel in-phase and quadrature waves fitting (IQWF) BIST procedure to address the limited test bandwidth issue in [21]. The IQWF procedure enables accurately measuring the phases and amplitudes of the test responses so as to enhance the test accuracy of the BIST circuitry. Like the conventional FFT-based test method, the IQWF procedure aims at testing for the SNDR, which is the major parameter revealing the performance of an oversampling ADC. The other parameters that can be tested by the IQWF procedure include the DR, frequency response, input-referred
offset, and gain error. The main achievement of this paper is achieving a BIST bandwidth as wide as the ADCs rated bandwidth with high test accuracy by the proposed IQWF procedure. Compared with the conventional FFT-based test method requiring lots of memory to store N output samples and a CPU/DSP to conduct the N -point FFT, the IQWF proce-dure benefits from its real-time low-complexity computation to save the hardware overhead and thus the test cost. The total gate count of the all-digital BIST implementation is only 16.6 k. In addition, a highly accurate ASG is cost-effectively implemented by making the low-cost digital signal generator (DSG) in [17] cooperating with the D3T input stage in [20].
A test chip containing the fully integrated BIST ADC has been fabricated in 0.18-μm CMOS. Experimental results show that the proposed BIST circuitry successfully achieves a test bandwidth as wide as the ADCs rated bandwidth. In addition, the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding results of the conventional FFT-based analog tests are 88.8 and 94.1 dB, respectively.
This paper is organized as follows. Section II depicts the circuit design of the ADC under test (AUT). The proposed IQWF procedure and the circuit implementation are illustrated in Section III. Section IV demonstrates the experimental results. Finally, Section V draws our conclusion.
II. DESIGN OF THE AUT
Fig. 1 shows the block diagram of the AUT. It con-sists of an analog second-order switched-capacitor (SC) modulator equipped with a decorrelating design-for-digital-testability (D3T) input stage [20] and a digital decimation filter. The AUT operates at an oversampling frequency fOS
Fig. 2. Schematic of the D3T second-order MUT [20].
of 12.288 MHz and an OSR of 256, providing a rated 20-kHz bandwidth for audio applications.
A. D3T Modulator
To conduct functional tests, an ASG is essential for generat-ing flexible and high-quality stimuli. For the built-in considera-tion, the area overhead of the ASG must be small enough to be embedded on chip. As has been discussed in Section I, using the PDM bit-streams as the stimuli is an appealing approach to testing ADCs. Therefore, we adopted the D3T scheme in [20], which can precisely convert the PDM bit-streams into the required analog stimuli, to implement the input stage of the MUT. In addition, the D3T scheme is very cost-effective
since it only adds a few switches to the original MUT design and reuses most of the original circuits.
Fig. 2 shows the schematic of the D3T MUT. It consists of two cascaded integrators and a comparator as a single-bit quantizer in addition to a built-in reference voltage generator. 1 and2are two nonoverlapped clock phases derived from
the oversampling clock fOS. The D3T structure, indicated by the shaded area in Fig. 2, provides the MUT with two
operation modes including the normal operation mode and the digital test mode. The test-mode control pin T switches the operation mode of the D3T MUT. Setting T to 0 and fixing the stimulus inputs Di j, j ∈ {0, 1}, at 1 turn off the switches S1j to S5j and make the MUT operate in the normal operation mode. In this mode, the D3T MUT samples the primary analog input Vi and converts it into a PDM output
DO as a conventional second-order modulator does.
The D3T MUT operates in the digital test mode if we set T to 1. The switches S Aj, S Bj, and S Ej are turned off due to the setup. The sampling capacitors CS0+, CS0−, CS1+, and CS1− now sample the dc reference voltage VREF instead of the primary analog input in1. During the successive2,
the two digital stimuli Di j control the switches S3j, S4j,
SCj, and S Dj, and decide which integration capacitor (either
CI 1+or CI 1−) the sampled charges are transferred to. In other words, the D3T SC input stage behaves as two differential single-bit DCCs to provide the MUT with two inherently linear discrete-time analog stimuli. Hence, the D3T MUT achieves high test accuracy in the digital test mode as well as in the normal mode.
Let CS0 = CS1 and the two digital stimuli Di j be the same PDM bit-stream Di but with a relative delay of K oversampling cycles. The I/O relationship of the D3T
MUT was shown to be
DO(z) = ST FMUT(z) 1+ z−K 2 Di(z) + NT FMUT(z)EMUT(z) (1) where DO(z), ST FMUT(z), NT FMUT(z), and EMUT(z) are the
PDM output, the signal transfer function (STF), the noise transfer function (NTF), and the quantization noise of the MUT, respectively [20]. Equation (1) shows a unique feature of the D3T scheme: it has an additional low-pass filtering
(LPF) term (1 + z−K)/2 associated with Di(z), which can attenuate the undesired shaped noise of the digital stimulus
Di(z). This LPF capability makes the stimuli generated by the DCCs more similar to their purely analog counterparts used in conventional analog tests. Thus, the D3T scheme effectively improves the test accuracy and alleviates the premature over-loading issue when using the PDM bit-streams to test modulators [20].
The operational amplifiers (OPAMPs) used in the MUT are realized with the conventional folded-cascode structure. Simulation results show the OPAMPs nominally have an open-loop gain of 80 dB, a unit-gain bandwidth of 300 MHz, and a phase margin of 63°.
B. Decimation Filter
The AUT also contains a digital decimation filter to remove the out-of-band shaped noise from the MUTs output and to decimate the output to a conversion rate of 48 kHz. Fig. 1 shows the block diagram of the decimation filter. The MUTs output is first filtered by a third-order comb filter and then decimated by a factor of 128. A following finite-impulse-response compensation filter is used to compensate for the amplitude distortion introduced by the comb filter so that the passband ripple of the decimation filter is within
±0.05 dB. Finally, the output of the compensation filter is
decimated by a factor of 2 to provide a 48-kHz conversion rate.
III. BIST DESIGNBASED ON THEPROPOSED
IQWF PROCEDURE
The all-digital BIST circuitry conducts single-tone func-tional tests based on the IQWF procedure and can test for SNDR, DR, frequency response, input-referred offset, and gain error of the AUT. Contrary to the conventional FFT-based analog test methods, the IQWF procedure benefits form its real-time computation and therefore does not need huge memory to save all the analyzed output samples. Hence, the required hardware is small enough to be integrated on chip.
Recall that a single-tone functional test applies a pure sine wave with a stimulus amplitude of AT and a stimulus
frequency of fT to the AUT. Note that the stimulus
fre-quency fT must be carefully chosen to fulfill the coherent
sampling criterion [27]. The resulted output of the AUT can be expressed as yADC(n) = a0+ a1sin 2π fT fS n+ φ1 ytone(n) + ∞ k=2 aksin 2πk fT fS n+ φk + e(n) thdn(n) (2)
where a0, ytone(n), and thdn(n) are the offset, the
stimulus-tone response, and the total-harmonic-distortion-plus-noise (THD+ N) signal of the AUTs output yADC(n), respectively. The term thdn(n) includes the harmonic distortion induced by the nonlinearity of the AUT and an additive noise e(n). e(n) represents the total noise at the AUTs output, which comprises the quantization noise of the AUT, the jitter noise introduced by the sampling clock source, the thermal and flicker noise of the circuits, and so on. fS is the conversion rate of the AUTs
decimated output, i.e., fS = fOS/OSR.
If we can generate a digital fitted sine wave, yfit(n) that best
fits the stimulus-tone response, i.e., ytone(n) ∼= yfit(n) for all n, and also test for the constant offset a0, the digital THD+ N
signal can be derived according to
thdn(n) ∼= yADC(n) − a0− yfit(n) (3) which is then used to compute the THD+ N power of the test. Meanwhile, the estimated amplitude a1 of the stimulus-tone
response can be used to compute the signal power and the gain error of the test. The ratio of the signal power and the THD+ N power reveals the SNDR value of the test.
To generate the digital fitted sine wave that best fits the stimulus-tone response, it is necessary to accurately acquire the amplitude, frequency, and phase shift of the stimulus-tone response. Since the stimulus frequency fT is a controlled factor, the amplitude a1 and the phase shift φ1 are what
we need to test for. Reference [21] already showed how to accurately test for the amplitude a1on chip, yet conventional
methods of testing for and generating the phase shift φ1 are
too complicated for BIST implementation.
The IQWF procedure simplifies the estimation and com-pensation of the AUTs phase response as follows. Let us first decompose the fitted sine wave into two orthogonal parts
yfit(n) = AIsin 2π fT fSn + AQcos 2π fT fSn (4) where AI ≡ a1cosφ1 (5) AQ ≡ a1sinφ1. (6)
The former term AIsin(2π fT/ fSn) is referred to the
in-phase component, which has the same in-phase as that of the stimulus, and the latter term AQcos(2π fT/ fSn) is referred to
the quadrature component, which is alwaysπ/2 out of phase of the stimulus. The amplitude of the stimulus-tone response can be calculated by a1= A2 I + A 2 Q. (7)
Equation (4) indicates that we can accurately synthesize
yfit(n) by measuring the two amplitudes AI and AQ instead
of directly measuring the phase shift φ1. The latter case is
much more difficult. Once the amplitudes AI and AQ are tested for and the two IQ reference signals sin(2π fT/ fSn) and
cos(2π fT/ fSn) are available, the fitted sine wave is certainly
attainable.
Due to the coherent and zero-mean properties of thdn(n), the least-squares (LS) estimation described in IEEE Standard 1241 [28] well suits for deriving the coefficients a0, AI,
and AQ in our applications [29]–[31]. Assume N samples
yADC(1), . . . , yADC(N) are taken in the estimation. The LS
estimation tends to find the values of a0, AI, and AQ that
minimize the following sum: N
n=1
yADC(n)−a0− AIsin
2π fT fSn − AQcos 2π fT fSn 2 . The LS solution is given by [28]
β = (XTX)−1XTy
ADC (8)
where β = [a0 AI AQ]
T, y
ADC = [yADC(1), . . . , yADC(N)] T, and X = ⎡ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎢ ⎣ 1 sin 2π fT fS · 1 cos 2πfT fS · 1 1 sin 2π fT fS · 2 cos 2πfT fS · 2 ... ... ... 1 sin 2πfT fS · N cos 2π fT fS · N ⎤ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦ .
Again, due to the coherent property, the computation of (8) can be simplified as XTX = diag(N, N/2, N/2) (9) and XTyADC = ⎡ ⎢ ⎢ ⎢ ⎣ N n=1yADC(n) N n=1sin 2πfT fSn · yADC(n) N n=1cos 2π fT fSn · yADC(n) ⎤ ⎥ ⎥ ⎥ ⎦. (10) From (8)–(10), we have ⎡ ⎢ ⎣ a0 AI AQ ⎤ ⎥ ⎦ = ⎡ ⎢ ⎢ ⎢ ⎣ 1 N N n=1yADC(n) 2 N N n=1sin 2πfT fSn · yADC(n) 2 N N n=1cos 2π fT fSn · yADC(n) ⎤ ⎥ ⎥ ⎥ ⎦. (11)
Given the test response yADC(n) and the two digital IQ ref-erence signals sin(2π fT/ fSn) and cos(2π fT/ fSn), the values
of a0, AI, AQ can be estimated according to (11). Once the
amplitudes AI and AQare acquired, the digital fitted sine wave
yfit(n) is generated according to (4).
Fig. 1 shows the detailed design of the fully integrated BIST ADC. The all-digital BIST circuitry comprises three main blocks: the DSGs, the ORA, and the BIST controller. The stimulus DSG (SDSG) generates the PDM bit-stream
DS(m) to stimulate the D
3
T AUT in the digital test mode where the notation m is the index of the signals operating at the oversampling frequency fOS. The in-phase DSG (IDSG)
and the quadrature DSG (QDSG) provide the aforementioned IQ reference signals in (4) with a normalized amplitude of 0.5 to simplify the hardware implementation, i.e., yIDSG(n) = 0.5 sin(2π fT/ fSn) and yQDSG(n) = 0.5 cos(2π fT/ fSn). A. Proposed IQWF Procedure
The IQWF procedure contains four steps to complete a test. Every step conducts the same coherent test and acquires N decimated output samples for analysis. In our design, N is set to be 211, a power of 2, to eliminate the need of a divider. The following detail the IQWF procedure and the BIST functions performed in the successive steps.
1) Calculating the Offset a0: At the beginning of the BIST,
the setup parameters AT and a21 are loaded into the DSGs to
specify the amplitude AT and the frequency fT of the stimulus, respectively. Then, the SDSG generates the PDM bit-stream
DS(m) to stimulate the D3T AUT. Then, the ORA accepts N decimated outputs from the AUT and calculates the offset a0in real time according to (11). The offset-free response is
defined as
yADC(n) ≡ yADC(n) − a0. (12) 2) Calculating the Amplitude of the In-Phase Component AI: In the second step, the IDSG generates the in-phase
refer-ence signal yIDSG(n) = 0.5 sin(2π fT/ fSn). According to (11),
the ORA performs the following equation to calculate AI:
AI = 4 N N n=1 yIDSG(n) · yADC(n). (13) Note that the offset-free response yADC(n) is used in (13) instead of yADC(n) to increase the computational DR of the ORA design. Equations (11) and (13) have the same results because the coherent property makesnN=1yIDSG(n) · a0= 0. 3) Calculating the Amplitude of the Quadrature Component AQ: Similar to the previous step, the ORA now accepts
the quadrature reference signal generated by the QDSG,
yQDSG(n) = 0.5 cos(2π fT/ fSn), and conducts the following: AQ = 4 N N n=1 yQDSG(n) · yADC(n). (14) 4) Calculating the THD+N Power: The last step aims
at calculating the THD+ N power. The BIST circuitry first uses the computed AI and AQ to derive the THD+ N signal according to
thdn(n) = yADC(n) − 2AIyIDSG(n)
−2AQyQDSG(n). (15) After that, the ORA accepts the resulted THD+ N signal and calculates the THD+ N power of the test by
PTHDN= 1 N N n=1 thdn(n)2. (16) Finally, the SNDR of the test can be calculated by
SNDR= A 2 I + A 2 Q 2PTHDN . (17)
TABLE I
SUMMARY OF THEIQWF BIST FUNCTIONS OF THEORA
Fig. 3. Configuration of the ORA in substep 1.
B. Implementation of the BIST Circuitry
The BIST circuitry benefits from its all-digital implementa-tion so that it is synthesizable, scalable, testable, and robust. Since the real-time IQWF procedure does not need huge memory, the BIST hardware is small enough for on-chip integration.
1) Implementation of the ORA: Table I lists the IQWF BIST
functions of the ORA in every BIST step. The function in the first step performs accumulation while the other functions per-form both multiplications and accumulation. Since the BIST functions are executed sequentially, the four BIST steps are designed to share the same multiplier and accumulator with the help of the multiplexers to save the hardware cost. By taking advantage of the ADCs oversampling feature, a radix-2 Booth multiplier instead of a parallel multiplier is used to perform the signed multiplication. In addition, the computation of every decimated output in the last BIST step is further divided into three serial substeps to avoid adopting additional multipliers. The design sets N = 211 to eliminate the need of a divider. With all the efforts, the ORA design consists of only 2.5 k digital gates. Figs. 3–5 show the configurations of the ORA in the corresponding substeps. The temporary results of the first two substeps are stored in the register x(n, p), where p∈ {1, 2}. For the nth decimated output of the AUT, 1 n N, the ORA processes it as follows.
a) Substep 1 (Removing the in-phase component of the fitted sine wave): With the configuration shown in Fig. 3,
Fig. 4. Configuration of the ORA in substep 2.
Fig. 5. Configuration of the ORA in substep 3.
the ORA first computes
x(n, 1) = yADC(n) − 2AIyIDSG(n) = yADC(n) − AIsin 2π fT fS n . (18)
The Booth multiplier in this substep takes 24 oversampling cycles to complete the 24-bit by 24-bit multiplication.
b) Substep 2 (Removing the quadrature component of the fitted sine wave): Fig. 4 shows the configuration of the ORA
in this substep. The ORA computes
x(n, 2) = x(n, 1) − 2AQyQDSG(n) = yADC(n) − AIsin 2π fT fS n − AQcos 2π fT fS n = yADC(n) − yfit(n) ∼ = thdn(n). (19) So far, the offset and the fitted sine wave are both eliminated from the AUTs nth output, resulting in the nth THD+ N signal sample. Similarly, this substep takes another 24 oversampling cycles to complete the Booth multiplication.
c) Substep 3 (Accumulating the square of the current THD+N signal): As the signal flow shown in Fig. 5, the ORA
Fig. 6. Implementation of the DSG.
first calculates the square of the nth THD+ N signal resulted from the prior substep. Then, the ORA accumulates the square and results in Pthdn(n) = Pthdn(n − 1) + x(n, 2)2= n i=1 thdn(i)2. (20) This substep also requires 24 oversampling cycles for the Booth multiplication.
The above three substeps are repeated for every decimated output until n= N. Finally, the output of the ORA is
1 NPthdn(N) = 1 N N i=1 thdn(i)2= PTHDN (21) which is the THD+ N power of the test. For each decimated period of the AUT, the three substeps totally take only 72 out of 256 oversampling cycles.
2) Implementation of the DSG: As shown in Fig. 1, the
IQWF procedure requires three DSGs to provide the PDM bit-stream and the digital IQ reference signals. As the stimulus, the in-band SNDR of DS(m) is suggested to be at least
12 dB higher than that of the AUTs response to ensure the test accuracy [32]. Regarding the linearity of the stimuli, the discrete-time analog stimuli converted from DS(m) are
inherently linear thanks to that the D3T scheme only adopts single-bit DCCs. In addition, the SNDRs of yIDSG(n) and yQDSG(n) are suggested to be at least 6 dB higher than that of the AUTs response to ensure the computational accuracy according to (15).
We modified the digital oscillator in [17] to implement the three DSGs. Fig. 6 shows the DSG design, which is a digital resonator embedded with a digital modulator with a unity-gain STF. The DSG operates at the oversampling frequency and simultaneously generates the multibit sine wave ys(m) and the PDM bit-stream DS(m). The required reference signal is
obtained by directly decimating ys(m) by a factor of OSR. To stimulate the second-order analog MUT, we embedded a third-order digital modulator in the DSG for its better
noise-shaping capability. Thus, the DSG can provide the PDM bit-streams with high in-band SNDRs. However, the embedded digital modulator introduces an extra shaped quantization noise into the oscillation loop and thus may disturb the stability of the DSGs oscillation, especially when the amplitude and/or the frequency of the output signal is high.
An effective approach to keeping the oscillation stable and enhancing the quality of the stimuli is to add another feedback path with a gain K , as shown in Fig. 6 [17]. The characteristic equation of the DSG was shown to be
z−2+ (a12a21− 2)z−1+ 1
+(a12a21− K )z−1NTFDSG(z)EDSG(z)
X2(z) = 0 (22)
where NTFDSG(z) and EDSG(z) are the NTF and the quantiza-tion noise of the embedded digital modulator, respectively.
X2(z) is the z-transform of x2(m). The DSG stably oscillates
if (22) has solutions exactly on the z-domain unit circle. Thus, the term containing the shaped noise NTFDSG(z)EDSG(z) in (22) needs to be eliminated. Setting K = a12a21makes this
term approximate to zero as desired. Note that the gain K is realized by shifting and adding so that the DSG is multiplier-free. The implementation results show the SDSG has a gate count of 4.6 k while the IDSG and the QDSG both consist of 3.8 k gates after properly truncating the signals. The three DSGs have different sizes because they are used to generate different signals. The SDSG is demanded to supply the high-quality stimuli even with an amplitude as small as−60 dBFS for the dynamic tests. On the other hand, the amplitude of the IQ reference signals provided by the other two DSGs are fixed at 0.5. Hence, the implementation of the SDSG needs to be more precise.
Once the shaped noise related term in (22) is vanished, the oscillation frequency is solely determined by the product of a12
and a21. We fixed a12 at 2−10 so that the stimulus frequency
can be set by a21 alone to simplify the test setup. In addition,
the amplitude and the phase of the output signal are well controlled by the initial values of the two integrators x1(0) and x2(0) [17]. To sum up, the design not only is cost-effective,
but also provides the flexibility of conducting accurate tests with various amplitudes and frequencies.
With slight modifications, the proposed IQWF-based ORA can be applied to arbitrary ADCs with the same computational accuracy. However, the method of using the PDM bit-streams as stimuli is only suitable for ADCs. To make the pro-posed BIST design applicable to arbitrary ADCs, an on-chip ASG, instead of the cost-effective combination of the SDSG and the simple D3T scheme, is necessary.
IV. EXPERIMENTALRESULTS
The fully integrated BIST ADC has been fabricated in a 0.18-μm CMOS process. Fig. 7 shows the micrograph of the test chip. The active area of the ADC including the analog D3T MUT and the digital decimation filter is 0.49 mm2. On the other hand, the all-digital BIST circuitry consists of 16.6 k gates and occupies 0.20 mm2. The hardware overhead of the BIST circuitry is about 29.0%. When the design is
Fig. 7. Micrograph of the test chip. TABLE II
SUMMARY OF THETESTCHIP
ported to advanced technology, the area of the analog core is scaled down less while the digital core has the same gate count and its area is scaled down more significantly. Thus, the BIST area overhead becomes smaller in advanced technology. Table II summarizes the test chip design.
A. Test Setup
For each BIST, the setup parameters are loaded to specify the amplitude and frequency of the single-tone test. As soon as the BIST procedure is completed, the BIST circuitry outputs the test results. Note that the BIST design achieves an all-digital I/O interface during the BIST. If users prefer to con-trol the BIST and observe the detailed results externally, the only test resource required is a low-cost digital tester, which can be realized by a low-end FPGA. For production tests, the BIST design outputs as simple as a go/no-go signal by storing all the BIST setup parameters including the threshold values for pass/fail decisions in on-chip memory. In both the cases, the proposed BIST ADC eliminates the need of high-end AMS ATE of conventional analog tests. Hence, the proposed design not only significantly reduces the test cost but also addresses the test issue of lacking accessible I/O pads in 3-D ICs.
In addition to the BIST, we also conducted the corre-sponding FFT-based analog tests in the conventional way as references. The analog stimuli are generated by the audio
Fig. 8. Measured spectra of the AUTs output and the corresponding THD+ N signal derived by the BIST circuitry in the 1 kHz,−6-dBFS test.
precision system II while the AUTs outputs are captured by a logic analyzer. The acquired output samples are then analyzed by FFT to compute the SNDR result of the test.
B. Validation of the IQWF Procedure
The similarity between the spectrum of the AUTs output and that of the derived THD+ N signal in the last BIST step validates the IQWF procedure. The BIST design contains an additional I2S interface to simultaneously acquire the AUTs output and the corresponding THD+ N signal. Fig. 8 plots the measured spectra of these two signals of the 1-Hz,
−6-dBFS test. The offset and the stimulus-tone response are
successfully eliminated to be beneath the noise floor in both spectra. Meanwhile, the THD+ N floors of the two spectra are almost the same. Thus, the cumulative THD+ N power plots of the two test results highly overlap with each other. The observations indicate that the amplitude, frequency, and phase shift of the fitted sine wave accurately match those of the stimulus-tone response, respectively, as our expectation. In the meantime, the BIST circuitry reports an offset of−49.5 dBFS in this test.
C. SNDR Versus Stimulus Level Test Results
Fig. 9 shows the test results of SNDR versus stimulus level. The stimulus amplitude was swept from −60 to −3 dBFS with a 2-dBFS step till −10 dBFS, and a narrower 1-dBFS step thereafter. In the meantime, the stimulus frequency was kept at 0.96 kHz. The BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB, while the conventional FFT-based analog tests result in 88.8 and 94.1 dB, respectively. The peak SNDR of the BIST results occurs at a stimulus level of−3 dBFS, very close to the full scale of the AUT.
Fig. 10 further shows the SNDR differences between the FFT-based analog test results and their BIST counterparts. For various stimulus levels, the SNDR differences are within 1.5 dB. The SNDR results of the BIST are slightly lower than their counterparts of the FFT-based analog tests because using
Fig. 9. Test results of SNDR versus stimulus level.
Fig. 10. SNDR differences of the SNDR versus stimulus level test. TABLE III
SUMMARY OF THEDR TESTS
the PDM bit-streams as stimuli induces additional correlated shaped noise, which slightly increases the THD+ N power of the test [20]. Table III summarizes the tests. Compared with the conventional FFT-based analog tests, the proposed BIST achieves a good test accuracy and a lower test cost with less setup efforts.
D. SNDR Versus Stimulus Frequency Test Results
Fig. 11 shows the SNDR test results versus stimulus fre-quency with the same stimulus amplitude of −6 dBFS. The BIST circuitry successfully achieves a test bandwidth as wide as the AUTs 20-kHz rated bandwidth. The SNDR differences between the FFT-based analog test results and their BIST counterparts are shown in Fig. 12 and within 0.6 dB.
Fig. 11. Test results of SNDR versus stimulus frequency.
Fig. 12. SNDR differences of the SNDR versus stimulus frequency test.
Fig. 13. Measured spectra of the AUTs output and the corresponding THD+ N signal derived by the BIST circuitry in the 20 kHz, −6-dBFS test.
Fig. 13 further plots the measured spectra of the AUTs output and the corresponding THD+ N signal in the 20 kHz,
−6-dBFS test. As well as the 1 kHz, −6-dBFS test, the
BIST circuitry successfully eliminates the offset and the stimulus-tone response from−44.6 and −6.1 dBFS to −110.7 and −109.7 dBFS, respectively. The results verify that the
TABLE IV
PERFORMANCESUMMARY ANDCOMPARISON
Fig. 14. Frequency response test results.
fitted sine wave generated by the IQWF procedure precisely matches the stimulus-tone response, even though the MUTs phase shift varies more significantly at the higher stimulus fre-quencies. Hence, the proposed IQWF procedure successfully addresses the limited BIST bandwidth issue in [21].
E. Frequency Response Test Results
Fig. 14 shows the frequency-response test results in which the stimulus amplitude was kept at −6 dBFS. The passband ripples are mainly due to the intrinsic frequency response of the decimation filter design, which is also plotted on the figure. The BIST result of the 20-kHz test is less than the expected gain by 0.06 dB only. Since the corresponding FFT-based analog test also shows the same gain, the difference comes from the frequency response of the MUTs STF.
Fig. 15 shows the test results of the gain error of the AUT. The gain error is defined as the differences between the measured gains and the designed values including the deterministic passband ripples of the decimation filter. The test results indicate that the proposed BIST circuitry can accurately calculate the signal power.
Note that the frequency responses tested by the BIST are more reliable than those tested by the FFT-based analog tests.
Fig. 15. Gain error test results.
The reason is that the analog signal paths on the evaluation board may introduce unpredictable gain errors, which are hard to be precisely calibrated. On the other hand, all the analog signal paths of the BIST are within the AUT. Thus, all the tested frequency responses are due to the AUT itself. No calibration for the test environment is required. This is another advantage of the proposed BIST design.
Table IV summarizes the performance of the proposed BIST ADC and compares it with the previous work.
V. CONCLUSION
This paper demonstrated the fully integrated BIST ADC based on the proposed IQWF procedure. The all-digital BIST circuitry provided the SNDR, DR, frequency response, offset, and gain error of the AUT. Compared with the FFT-based test methods, the BIST circuitry benefited from its real-time computation so it did not need huge memory and only consisted of 16.6 k gates. Experimental results showed that the BIST circuitry reported a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding conventional analog tests resulted in 88.8 and 94.1 dB, respectively. Particularly, it is the first BIST ADC that achieves a test bandwidth as wide as the ADCs rated bandwidth thanks to the IQWF
procedure. The tested frequency responses of the BIST and those of the corresponding FFT-based analog tests were almost the same. Moreover, the BIST design can be modified to test the noise, individual harmonic distortion components, SFDR, and SNR by first testing for the coefficients ai of the harmonic components of interest using the IQWF procedure. Once the coefficients are obtained, the aforementioned parameters can be calculated. The proposed BIST ADC eliminated the need of high-end AMS ATE without compromising test qual-ity. It greatly reduced the test cost and provided a test solution for the applications in which conventional test resources are not available such as 3-D ICs.
ACKNOWLEDGMENT
The authors would like to thank the Chip Implementation Center (CIC), Taiwan, for fabricating the test chips.
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Shao-Feng Hung (S’09) received the B.S. and M.S.
degrees in electrical and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2009, respectively, where he is currently pursuing the Ph.D. degree.
He was a Visiting Researcher with the University of California at Santa Barbara, Santa Barbara, CA, USA, from 2013 to 2014. His current research interests include the design-for-testability, built-in self-test, and calibration techniques for mixed-signal circuits and systems.
Mr. Hung was a recipient of the Diamond Prize in the IC design competition of the Twelfth Macronix Golden Silicon Award in 2012.
Hao-Chiao Hong (S’98–M’04–SM’12) received the
B.S., M.S., and Ph.D. degrees in electrical engineer-ing from National Tsengineer-ing Hua University, Hsinchu, Taiwan, in 1990, 1992, and 2003, respectively.
He was with Taiwan Semiconductor Manufactur-ing Company, Ltd., Hsinchu, from 1997 to 2001, where he developed mixed-signal IPs for customers and process vehicles. In 2001, he became the Senior Manager of the Department of Analog IP at Intel-lectual Property Library Company, Hsinchu. He has been with National Chiao Tung University, Hsinchu, since 2004, where he is currently a Full Professor of the Department of Electrical and Computer Engineering. He holds three U.S. patents, two Taiwan patents, and one China patent. His current research interests include the design-for-testability, built-in self-test, and calibration techniques for mixed-signal circuits and high-performance mixed-mixed-signal IC design.
Dr. Hong served as the Executive Secretary of the Mixed-Signal and RF Consortium of the Ministry of Education, Taiwan, from 2006 to 2008, and the Executive Secretary of the Heterogeneous Integration Consortium of the Ministry of Education, Taiwan, from 2008 to 2009. He was the General Chair of the Sixth VLSI Test Technology Workshop (VTTW) and the Program Chair of the Fifth VTTW. He is a Life Member of the Taiwan IC Design Association and the VLSI Test Technology Forum, Taiwan. He was a recipient of the Best Paper Award from the 2009 International Symposium on VLSI Design, Automation & Test, and the Best Advisor Award in the IC design competition of the twelfth Macronix Golden Silicon Award in 2012.
![Fig. 2. Schematic of the D 3 T second-order MUT [20].](https://thumb-ap.123doks.com/thumbv2/9libinfo/7631428.135182/3.918.137.782.83.684/fig-schematic-d-t-second-order-mut.webp)
