with shallow trench isolation (STI) longitudinal compressive me-chanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting. Index Terms—Layout, mechanical stress, MOSFET, piezoresis-tance, shallow trench isolation (STI), tunneling.
I. INTRODUCTION
H
OLE direct tunneling current across the gate oxide of p-MOSFETs has been extensively studied in the presence of an external mechanical stress applied during the measure-ment of this current [1]–[3]. The corresponding gate oxide thickness change due to the effect of Poisson’s ratio has been shown to be negligible in magnitude; for example, in [1], around 0.03% change in the gate oxide thickness has been estimated for an external stress of 300 MPa. Therefore, the physical gate oxide thickness essentially remains unchanged, regardless of the externally applied stress. Under the circum-stances, the induced gate current variation can be properly attributed, through the change in both the carrier repopulation and the effective SiO2/Si barrier height, to the strain-inducedvalence-band splitting. It has therefore been argued that the hole gate direct tunneling current decreases with the external
Manuscript received January 27, 2009; revised May 5, 2009. Current version published July 22, 2009. This work was supported by the National Science Council of Taiwan, under Contract NSC 97-2221-E-009-155-MY3. The review of this paper was arranged by Editor C. Jungemann.
C.-Y. Hsu, C.-C. Lee, Y.-T. Lin, and M.-J. Chen are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]).
C.-Y. Hsieh was with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. He is now with the Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2009.2024024
compressive stress [1], [2]. On the other hand, for the case of p-MOSFETs undergoing a process-induced (internally applied) mobility-boosting mechanical stress during the manufacturing of the device, hole gate direct tunneling current may encounter complicated situations (gate oxide thickness change due to strain dependence of the oxidation rate, for example), rather than simply the strain-altered valence-band splitting. So far, it has been unclear whether the decreasing trend of the hole direct tunneling with the compressive stress, as claimed in the literature [1], [2], could hold for the internal case. Thus, the ability to distinguish the external stress effect from the internal one and/or find the similarities between the two is crucial.
In this paper, we will elaborate on the above subject. First, we will present the experimental hole gate direct tunneling current of p-MOSFETs under shallow trench isolation (STI)-induced longitudinal compressive stress, which does not appear to fol-low the trend [1], [2] caused by the strain-altered valence-band splitting alone. A quantum strain simulator will be developed to resolve this contradictory issue. The validity of the simulator will be examined in detail. Then, the quantum simulator will be combined, in a systematic manner, with the experimental data in order to determine the underlying physical origin.
II. EXPERIMENTAL
P-channel MOSFETs, as schematically shown in Fig. 1, were fabricated using a state-of-the-art manufacturing process. In this process, the STI-induced compressive stress was applied prior to the growth of the gate oxide and the source/drain implantation. The nominal process parameters were obtained by the capacitance–voltage fitting: p+ polysilicon doping
con-centration Npoly= 1× 1020cm−3; physical gate oxide
thick-ness tox= 1.27 nm; and n-type substrate doping concentration
Nsub= 6× 1017 cm−3. The gate width-to-length ratio was
fixed at W/L = 10 μm/1 μm. The devices were formed on the (001) wafer with the channel length direction along110. The use of the wide structures ensures that the transverse channel stress can be reasonably ignored. To control the longitudinal channel stress, the gate to STI spacing, labeled as a in Fig. 1, was drawn with three values of 10.0, 0.495, and 0.21 μm. The corresponding stress magnitude can be determined via the piezoresistance coefficients. First, the peak hole mobility at
VD=−0.025 V was measured across the wafer. The relative change of the average peak hole mobility was then obtained with respect to that of a = 10 μm, as plotted in Fig. 2 versus
Fig. 1. Schematic demonstration of (a) the cross-sectional and (b) topside view of the test device. The gate edge to STI edge spacing labeled as a is highlighted. The compressive stress is due to the lower thermal expansion rate of STI oxide compared to silicon.
Fig. 2. Measured (symbols) and calculated (line) hole mobility change versus STI stress. The straight line is from the piezoresistance coefficient [2]. The inset shows the extracted stress divided by that of the minimum a as a function of a, along with a fitting curve as cited in [4].
stress. Here, the state-of-the-art inversion-layer piezoresistance coefficient for holes, as quoted elsewhere [2], was employed as demonstrated by a straight line in the figure. The corresponding longitudinal channel stress σ is therefore determined to be around −120 and −215 MPa for a = 0.495 and 0.21 μm, respectively. To testify to the validity of the extracted stresses, one empirical formula, which connects the layout parameters to the stress quantities, was also cited elsewhere [4]: σ(a) =
σ(amin) (1 + Vmσ(a− amin)/a), where aminis the minimum
gate-to-STI spacing, and Vmσ is the maximum variation for a→ ∞ with respect to σ(amin). Excellent fitting was achieved
with Vmσ=−1.02, as shown in the inset of Fig. 2.
To examine the poly stress, the threshold voltage was also measured across the wafer with the results in Fig. 3 in terms of the average and standard deviation of the distribution. The threshold voltage variation appears to be a weak function of the gate-to-STI spacing, and its trend looks irregular, prohibiting the poly stress from being determined. However, in our pre-vious work [9], the electron direct tunneling data confirm the
Fig. 3. Measured threshold voltage versus gate-to-STI spacing at VD= −0.025 V. The error bar represents the standard deviation of the distribution
and the data point (symbol) represents the average of the distribution.
Fig. 4. Comparison of simulated (line) gate current versus gate voltage with those (symbols) measured from eight samples. The different symbols stand for the different device positions on wafer and the different gate-to-STI spacing values. The line represents the no-stress simulation result with the nominal process parameters. The source, drain, and substrate are all tied to the ground. The inset shows the distribution of the measured gate current at VG=−1 V
versus gate-to-STI spacing. The error bar represents the standard deviation of the distribution and the data point represents the average of the distribution.
existence of a lateral STI-induced stress in the polysilicon, and since the gate oxide is rather thin, the lateral stress near the polysilicon surface is reasonably close to that of the underlying silicon. The same wafer was used in this study, and thereby, the poly stress was made equal to the channel stress. Extra evidence will be given later.
The hole gate direct tunneling current was measured in in-version with the source, drain, and substrate tied to the ground. Strikingly, the gate current versus gate voltage characteristics measured across the whole wafer do not appear to deviate from each other. This situation is displayed in Fig. 4 for several samples with different a values and different device positions. Obviously, it is difficult to distinguish the measured I–V char-acteristics in a wide current range. This argument remains valid, regardless of the device position on wafer or the value of a used. To produce a clear difference, the average and standard deviation of the gate current distribution at a specific gate volt-age VG=−1 V was adopted, as inserted into Fig. 4. The inset of the figure clearly reveals an increasing trend of the average hole gate direct tunneling current with the compressive stress (decreasing a), which is exactly contrary to that published in the
Fig. 5. Experimental and simulated gate current change versus gate voltage under−215 MPa longitudinal stress. The formulas used are inserted.
literature [1], [2]. The role played by the standard deviation of the gate current will be described later. Additionally, the relative change of the average gate current with respect to that of a = 10 μm was found to be a weak function of the gate voltage, as shown in Fig. 5 for σ =−215 MPa. This specific characteristic over the gate voltage can serve as the corroborating evidence while determining the underlying physical mechanisms, as will be explained later.
III. QUANTUMSTRAINSIMULATION
To resolve the contradicting issue mentioned above, a quan-tum strain simulator was developed around the hole direct tun-neling process, as schematically described in Fig. 6 in terms of the energy band diagram. First, with the combination of the six-band k• p Hamiltonian and a triangular-well approximation, as detailed elsewhere [5], the strain-induced valence-band edge shift can be calculated under a certain surface electric field as follows: E(j, i) = 2 2mzhi 1/3⎛ ⎝3πqFs j− 14 2 ⎞ ⎠ 2/3 +q(EV 1−EV i) (1) where E(j, i) represents the energy of the jth subband in the
ith valence band, i = 1, 2, and 3 correspond to the first, second,
and third valence band, respectively, mzhi is the hole out-of-plane effective mass associated with the ith valence band, Fs is the silicon surface electric field strength, EV iis the energy of the ith valence band, and q is the elemental charge. The cal-culated energy levels at VG=−1 V for the top (first), second, and split-off (third) hole subbands are shown in Fig. 7 versus stress. Here, it can be seen that the top subband is insensitive to the stress while for the remaining subbands, the energy levels rise up, thereby reducing the corresponding SiO2/Si barrier
height seen by the holes while tunneling across the oxide. The involved hole out-of-plane effective masses in the inversion layer were found to be fairly constant, i.e., mzh1= 0.27 m0,
mzh2= 0.22 m0, and mzh3= 0.23 m0, which are the same
values as those of the citation [1].
Fig. 6. Schematic energy band diagram of a p+ polysilicon/SiO 2/n-Si
system biased in the inversion condition and stressed with uniaxial compressive conditions. The solid lines indicate the conduction and valence band edge without external stress. The dotted lines indicate the stress induced band edge shift of the conduction and valence band. The figure also shows the energy quantization effect in the inversion layer and the hole direct tunneling process from the inversion layer to the polysilicon gate.
Fig. 7. Calculated energy levels versus stress for the top (first), second, and split-off (third) hole subbands.
Then, the carrier repopulation under stress can be calculated as follows: N (j, i) = mdhikBT π2 ln 1 + exp EF− E(j, i) kBT (2) where N (j, i) represents the hole density per unit area of the
jth subband in the ith valence band, mdhi is the 2-D density of states effective mass of the ith valence band, EF is the hole Fermi level, kB is Boltzmann’s constant, and T is the absolute temperature. Finally, the triangular-potential-based hole direct
Fig. 8. External-stress-dependent hole gate current data [1], [2] (symbols) used to examine the validity of the quantum strain simulator. The line represents the simulation result due to the strain altered valence-band splitting only.
tunneling model in our previous work [6] can be applied, in which the hole direct tunneling current per unit area reads as
Jh=
i
j
qf (j, i)N (j, i)Pt(E(j, i)) (3) where f (j, i) is the hole impact frequency on the Si/SiO2
interface and equals (qFs/2)(2mzhiE(j, i))−1/2, where εsi is
the silicon permittivity, and Pt(E(j, i)) is the hole transmission probability across the SiO2film. The hole effective mass in
ox-ide m∗oxcan play a critical role in determining the transmission probability Pt(E(j, i)).
Therefore, by incorporating both the conduction-band de-formation potential (see [7] for the complete formulas, which were also cited in our previous work dedicated to the electron direct tunneling [8], [9]) and the valence-band k• p calculation results into the triangular-potential-based hole direct tunneling simulator [6], the strain-altered hole gate current is able to be readily quantified. The validity of the presented quantum strain simulator can be examined using three different aspects. First, a fairly good agreement with the measured gate current versus gate voltage characteristics was created in a wide range of four decades, as demonstrated in Fig. 4 for σ = 0. This means that the simulator is reliable for the gate voltage more negative than−0.2 V. The same argument holds for the nonzero stress. Second, the hole effective mass in the oxide m∗ox is exactly equal to the literature value (0.32 mo) [10]. This also is the case for the hole out-of-plane effective masses in the inversion layer as mentioned above. Finally, with the fixed gate oxide thickness, the simulated hole gate direct tunneling current change at VG=−1 V due to the strain-altered valence-band splitting was found to be close to those measured under the
externally applied compressive stress [1], [2], as depicted in
Fig. 8. Therefore, the validity of the quantum strain simulator is confirmed.
IV. PHYSICALORIGIN ANDDISCUSSION
To find out the plausible physical mechanisms that account for the hole gate current enhancement, we employed the quan-tum strain simulator verified above through the changes in the process parameters. First, with polysilicon doping
concen-Fig. 9. Simulated gate current change versus gate voltage for (a) different gate oxide thicknesses, (b) different poly gate doping concentrations, and (c) different substrate doping concentrations. The formulas used are inserted.
tration Npoly and substrate doping concentration Nsub both
fixed at their nominal values, the simulated gate current change percentage is given in Fig. 9(a) versus gate voltage with the gate oxide thickness tox as a parameter. The corresponding
fractional gate current change remains constant in a wide range of the gate voltage, regardless of tox. This means that the same
flat characteristics as those experimentally encountered over the gate voltage can be reached as long as the appropriate gate oxide thickness has been determined. Second, to reflect the stress effect on impurity diffusion [9], [11]–[13], additional simulations were conducted for varying Npoly or Nsub. The
Fig. 10. Simulated gate current change versus stress for several oxide thick-ness with respect to the gate current of σ = 0 case (i.e., tox= 1.27 nm). Both
the polysilicon doping concentration and substrate doping concentration are kept at the nominal values. Also shown for comparison are the experimental data (symbols) corresponding to the inset of Fig. 4.
results are given in Fig. 9(b) and (c). The gate current change presented in Fig. 9(b) corresponds to two different values of
Npolyunder fixed toxand Nsub, clearly revealing a profoundly
significant deviation for more negatively biased gate voltages. Such a huge deviation also appears in Fig. 9(c) for two different values of Nsubunder fixed toxand Npoly, which occurs instead
in the direction of less negative gate voltage. Therefore, the stress-induced dopant redistribution is unlikely to serve as the responsible mechanism. Furthermore, the remaining possible factors were considerably ruled out: 1) the channel area change due to source/drain extension diffusion retardation [9], [13] is insignificant (∼10−3) and 2) the trap-assisted tunneling as the dominant mechanism is impossible because of less correlation with the mobility data in Fig. 2; specifically, the mobility change at−215 MPa stress is about three times the gate current change.
The analyses above suggest the reduction in the physical gate oxide thickness over the whole gate area as the principal factor in producing the gate current enhancement. Thus, the quantum strain simulation was further carried out for different gate oxide thicknesses with other process parameters kept unchanged. The results are plotted in Fig. 10 versus stress along with the data for comparison. The underlying gate oxide thickness can be straightforwardly obtained with an accuracy of 0.001 nm:
tox= 1.267 and 1.264 nm for −120 and −215 MPa stress,
respectively. The extracted gate oxide thickness reduction is around 0.003 and 0.006 nm for −120 and −215 MPa stress, respectively. Again, the gate current change for tox= 1.264 nm
and σ =−215 MPa was simulated with respect to the nominal case (tox= 1.27 nm and σ = 0 MPa). The results are given in
Fig. 5. Here, it can be seen that good agreements with the data are created for a wide range of gate voltage down to−0.2 V, achieved without adjusting any parameters.
At this point, it is interesting to make a comparison with the existing thermal oxidation experiment on a bending silicon wafer [14], [15]. In one of the citations [14], an externally applied mechanical stress of−100 MPa was shown to have no noticeable effect on the thickness of the formed oxide (800◦C dry O2100% oxidation), particularly in a certain range down to
2 nm thick, which is comparable with the gate oxide thickness
Fig. 11. Simulated gate current change of zero poly stress with respect to a poly stress of−215 MPa as a function of gate voltage for a channel stress of
−215 MPa. The formulas used are inserted.
used in this work. In [15], the effect of the external compres-sive mechanical stress was also shown to be insignificant as well, valid with an accuracy of 0.5 nm. However, with the combination of both the quantum strain simulator and the hole direct tunneling data as done in this work, we reached the gate oxide thickness with the greatly improved precision down to 0.001 nm. Indeed, it is difficult for current capacitance mea-surements to deliver such a precision of 0.001 nm or 0.08% in gate oxide thickness variation. As widely recognized, however, in the direct tunneling regime the gate current is highly sensitive to the change in the gate oxide thickness. This means that the gate direct tunneling current may serve as an ultra-precision detector of the oxide thickness. However, care must be taken in this direction. This explains the importance of a quantum simulator, as demonstrated in this paper.
Additionally, the inset of Fig. 4 clearly points out that the standard deviation of the gate current is comparable between different gate-to-STI spacing values. This dictates that the spa-tial fluctuation in the gate oxide thickness is caused by the random process during the thermal oxidation, regardless of the stress. Only the average of the gate current steadily increases with the stress. This means that applying a compressive stress may retard the oxidation rate and, thus, give rise to a reduction in the physical gate oxide thickness. On the other hand, the presented change of up to 0.47% in the gate oxide thickness is larger than that caused by the Poisson’s ratio (0.03%) [1]. This means that the strain-retarded gate oxidation rate may dominate over the strain-altered valence-band splitting counterpart. As a result, the currently recognized trend [1], [2] that the hole gate direct tunneling current decreases with the compressive stress is significantly reversed, as clearly demonstrated in this paper.
Finally, the simulator was, again, carried out to examine the effect of the poly stress. The resulting gate current change of zero poly stress with respect to poly stress of −215 MPa is plotted in Fig. 11 as a function of gate voltage for channel stress of−215 MPa. It can be seen in the figure that significant discrepancies occur, particularly for less negative gate voltage. Thus, this new deviation, as well as its striking trend, can provide the extra evidence to support the aforementioned hypothesis that the poly stress is close to the channel stress. On the other hand, modeling the gate current through a
the overall band diagram may be achieved through the fitting of the gate current. At this point, the tunneling model used in this work must be modified substantially. Specifically, the tunneling involved with the traps might dominate the overall gate current in metal-gate/high-k devices due to the thicker insulator and the higher trap density within the insulator of the metal-gate/high-k devices. Multilayer tunneling and/or hopping mechanisms may be significant as well.
V. CONCLUSION
The measured hole gate direct tunneling current on a nominal 1.27-nm gate oxide p-MOSFET has exhibited an increasing trend with STI compressive stress, which is exactly contrary to that of the externally applied compressive stress. To resolve this contradicting issue, a quantum strain simulator has been established. The validity of the simulator has been examined in detail. The combination of the verified simulator and the experimental data has systematically led to the finding of the origin: a reduction in the apparent physical gate oxide thickness over the whole gate area, with an accuracy of 0.001 nm, occurs under the influence of the STI compressive stress. A linkage to the mechanical-stress-dependent thermal oxidation experiment in the open literature has been constructed. The extracted gate oxide reduction in this work has been shown to be able to significantly enhance the hole direct tunneling current and, con-sequently, reverse the conventional trend with the stress. Some suggestions have also been given concerning the application of the simulator in the metal-gate/high-k devices.
REFERENCES
[1] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, no. 5, pp. 052 108-1–052 108-3, Jan. 2006.
[2] S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: Extending the CMOS roadmap,” IEEE Trans.
Elec-tron Devices, vol. 53, no. 5, pp. 1010–1020, May 2006.
[3] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 410–412, Jun. 2005.
[4] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electri-cal performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117–120. [5] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim,
“Six-band k• p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness,” J. Appl.
Phys., vol. 94, no. 2, pp. 1079–1095, Jul. 2003.
Tech. Dig., June 2000, pp. 198–199.
[11] M. J. Aziz, Y. Zhao, H. J. Gossmann, S. Mitha, S. P. Smith, and D. Schiferl, “Pressure and stress effects on the diffusion of B and Sb in Si and Si–Ge alloys,” Phys. Rev. B, Condens. Matter, vol. 73, no. 20, pp. 054 101-1–054 101-20, Feb. 2006.
[12] M. J. Chen and Y. M. Sheu, “Effect of uniaxial strain on anisotropic diffusion in silicon,” Appl. Phys. Lett., vol. 89, no. 16, pp. 161 908-1– 161 908-3, Oct. 2006.
[13] Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30–38, Jan. 2005.
[14] T. Tamura, N. Tanaka, M. Tagawa, N. Ohmae, and M. Umeno, “Effects of external stresses on the low temperature thermal oxidation of silicon,”
Jpn. J. Appl. Phys., vol. 32, no. 1A, pp. 12–16, Jan. 1993.
[15] J. Y. Yen and J. G. Hwu, “Stress effect on the kinetics of silicon thermal oxidation,” J. Appl. Phys., vol. 89, no. 5, pp. 3027–3032, Mar. 2001.
Chih-Yu Hsu (S’07) received the B.S. degree in electrophysics from the National Chiao Tung Uni-versity, Hsinchu, Taiwan, in 2005, where he is cur-rently working toward the Ph.D. degree in electronics engineering.
His research interests include the characterization and modeling of strained-Si MOSFETs and trap physics in nanoscale devices.
Chien-Chih Lee (S’07) was born in Taipei, Taiwan, in 1981. He received the B.S. degree in physics from the National Chung Hsing University, Taichung, Taiwan, in 2004. He is currently working toward the Ph.D. degree in electronics engineering at the National Chiao Tung University, Hsinchu, Taiwan.
His research interests include the characteriza-tion and modeling of silicon-based devices and trap physics in nanoscale devices.
Yi-Tang Lin was born in Taipei, Taiwan, in 1984. He received the B.S. and M.S. degrees in electronics en-gineering from the National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2008, respectively.
He is currently devoted to the military service. His research interests include strain physics and its modeling in nanoscale devices.
He is the holder of eight U.S. patents and six Taiwanese patents in the field of the high-precision analog capacitors, 1-T memory cell, dynamic threshold MOS, electrostatic discharge protection, and Flash memory. He has graduated 15 Ph.D. students and more than 100 M.S. students. His current research interests include semiconductor device physics and nanoelectronics.
