IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 9, SEPTEMBER 2004 649
Lateral Migration of Trapped Holes in
a Nitride Storage Flash Memory Cell
and Its Qualification Methodology
N. K. Zous, M. Y. Lee, W. J. Tsai, Albert Kuo, L. T. Huang, T. C. Lu, C. J. Liu, Tahui Wang, Senior Member, IEEE,
W. P. Lu, Wenchi Ting, Joseph Ku, and Chih-Yuan Lu, Fellow, IEEE
Abstract—The negative threshold voltage ( ) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative drift is proposed.
Index Terms—Lateral migration, MXVAND, NBit, nitride storage, NROM, trapped hole.
I. INTRODUCTION
B
Y UTILIZING channel hot electron injection and band-to-band hot hole injection as programming and erasing methods, respectively, injected electrons and holes will be locally trapped in a nitride layer of an “NBit” cell in a multiplex virtual ground AND(MXVAND) array [1], and two bits per cell operation is therefore achieved [2]. Since the charge storage material of Nbit cells is different from that of conventional floating gate flash devices, the understanding of data retention loss mechanisms in these nitride storage devices is critical to the improvement of the device reliability. Though the cells have been demonstrated to possess excellent intrinsic electron retention [3], the data retention loss caused by electron leakage via stress created oxide traps is still a reliability concern after program/erase (P/E) cycling. A g acceleration method [1] and a temperature acceleration test [4] are proposed for qualification of the NBit devices in its program state. In contrast to electrons, we observe a stronger temperature dependence of hole-lateral transport in the nitride layer in an over-erased cell [5]. This lateral spread of trapped holes results in channel shortening, thus causing a negative threshold voltage ( ) shift and an increase of leakage current in a memory arrayManuscript received May 20, 2004; revised June 18, 2004. The review of this letter was arranged by Editor C.-P. Chang.
N. K. Zous, M. Y. Lee, A. Kuo, L. T. Huang, T. C. Lu, C. J. Liu, W. P. Lu, W. Ting, J. Ku, and C.-Y. Lu are with Macronix International Company, Ltd., Science Park, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).
W. J. Tsai and T. Wang are with the Macronix International Company, Ltd., Science Park, Hsin-Chu, Taiwan, R.O.C. and also with the Department of Elec-tronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2004.833824
Fig. 1. Lowest bound of erase stateV distribution versus cycle number before and after bake at 150 C for 168 h. The required erase time to pass erase-verify is plotted in the inset.
[5]. Since the negative shift is related to the short-channel effect, this issue becomes more serious in a scaled device. In this paper, the hole lateral migration effect is demonstrated by using charge pumping measurement. In addition, by monitoring the band-to-band tunneling current, trapped hole emission is investigated at various temperatures. Finally, an accelerated qualification methodology is proposed for such negative drift. An NBit cell with m and g m was used in this study. The thickness of each ONO layer is 9 (top oxide), 6 (nitride), and 5 nm, respectively.
II. EXPERIMENTAL
In Fig. 1, the lowest bound of erase state distribution versus cycle number was shown before and after bake at 150 C for 168 h. The test sample size is a sector of 512 K cells, which are at “all 1 pattern,” i.e., all in erase state. It is found that the drifts toward a more negative value as cycling number increases. In the inset of Fig. 1, we plot the required erase time for the entire sector to pass erase-verify. The increase of erase time with cycle number is due to the location mismatch of injected electrons and holes [6]. In order to compensate for stored electrons far in the channel region, more hole injection is needed in erase operation. In other words, to obtain a similar erase , more holes are accumulated in the nitride layer as cycle number increases. This implies that the larger negative drift in an erased cell after P/E cycling is related 0741-3106/04$20.00 © 2004 IEEE
650 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 9, SEPTEMBER 2004
Fig. 2. Charge pumping characteristics of a fresh memory cell, after 30 erase shots, and subsequently after bake of 15 min, 3 h, and 37 h at 150 C, respectively. Schematic drawing of hole lateral spread is also drawn.
to trapped holes in the nitride layer. To further characterize the negative drift of , a charge pumping method [7], which is able to probe the lateral distribution of trapped charges, is used. A trapezoidal pulse train with a fixed low level ( ) and successively increasing high levels ( ) is applied to the gate. The pulse frequency is 2.5 MHz. The substrate, the source, and the drain are grounded. The charge pumping current versus is measured. The is sufficiently low to ensure that the entire channel is in accumulation. By varying , only the part of the channel that undergoes inversion-accumulation-inversion over a pulse cycle can contribute to . To emulate the erase time effect as shown in Fig. 1 and to avoid excess interface trap generation after P/E cycling and their annealing during bake, a fresh cell is intentionally over-erased by 30 erase-shots instead. The charge-pumping result is shown in Fig. 2. The generated interface traps during erase are negligible since the at V is almost unchanged. Because a considerable amount of holes are trapped in the nitride after erase, a leftward shift of the low portion (for V) of the characteristic [7] is observed. The local threshold voltage in the hole injection region is reduced to around V. Here, we also define a parameter , which is the corresponding to pA. reflects the maximum hole density in the nitride. The cell is then baked at 150 C. A crossover of the characteristics before and after bake is observed. The shifts rightward with bake time. In addition, between V and V increases. This increased is opposed to interface trap annealing effect. To explain the observed characteristics, the lateral movement of holes is depicted in the figure. After bake, the peak trapped hole density decreases and thus the shifts rightward. On the other hand, the trapped hole region extends due to the hole lateral spread in the nitride. Thus, the corresponding for V increases due to a larger channel region contributing to . In short, the negative shift can be explained in the following. Holes are firstly thermally emitted from the traps to the valence band (or conducting shallow states) and then laterally drifted by an internal field and re-captured by other nitride traps during
Fig. 3. V is plotted againstV . A positive correlation is found between them. In the inset, the evolution ofV is shown. TheV is defined as gate voltage to have an off-state drain current of 100 pA atV = 2:5 V.
bake. The spreading of holes enlarges the low region and causes channel length shortening. The cells’ is therefore reduced.
III. QUALIFICATIONMETHODOLOGY
A. Measurement
Since the loss depends on both hole lateral spreading and the change of the local trapped hole density, which is a compli-cated two-dimensional (2-D) effect, it is not a suitable indicator to investigate the acceleration method. For example, with the same extent of hole lateral migration, the cell is not affected in a long-channel device while it is significantly reduced in a short-channel device. Therefore, the [8], [9] and the are adopted to monitor the temporal evolution of trapped hole density instead. The is defined as the gate voltage when the band-to-band tunneling current is 100 pA at V, as illustrated in the inset of Fig. 3. Regardless of number of over-erase shots, a positive correlation is found between and in Fig. 3. In other words, a consistent result is obtained from these two methods.
B. Model
According to the thermionic emission model, the emission time constant of a hole in a trap with trap energy above the nitride valence band can be described as [10], [11]
h h
h (1)
where h is the capture cross-section of the hole trap and mh is the effective hole mass in the nitride. Other variables have their usual definitions. It follows from (1) that
ZOUS et al.: LATERAL MIGRATION OF TRAPPED HOLES IN A NITRIDE STORAGE FLASH MEMORY CELL 651
Fig. 4. 1V versus bake time at various temperatures. All curves follow a straight line on a semi-log scale. The solid lines represent calculation result.
Assuming the trapped holes have a continuous distribution in energy and the trapped hole density is a constant, the emitted positive charge h is then derived as
h
h
h
(3) where h is the volumetric trapped hole density in the nitride layer, J is the current density resulting from the emitted holes, and E is the band gap value of the nitride film. Equation (3) indicates that the time-dependence of the trapped holes density due to the thermionic emission should follow a straight line on a semi-log scale and the slope is proportional to the temperature. In measurement, the variation of h is monitored by the due to a positive correlation between them [8], [9].
C. Model Result
In Fig. 4, the versus bake time at various tempera-tures is plotted. All curves follow a straight line on a semi-log scale. The solid lines represent calculation result with h in (1) and the proportionality constant in (3) as fitting parame-ters. The extracted capture cross-section h of holes is about 1 . In calculation, mh m is used. Based on this result, the temperature dependence and the time dependence can be predicted. In practice, the acceleration test for the
nega-tive drift at T C is required to pass 114 h to meet the ten years of data retention at T C.
IV. CONCLUSION
In this paper, the hole lateral migration effect of an NBit cell in erase state is investigated. A negative shift is found to increase with cycling number and will be a potential issue for future device scaling. According to the thermionic emission model, the hole emission effect should exhibit a logarithm dependence on bake time and a linear dependence on bake temperature. The extracted hole capture cross section is about 1 . Therefore, to achieve ten years of data retention at T C, acceleration test at T C for 114 h is required.
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