SD Specifications Part 1 Physical Layer Simplified Specification

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SD Specifications Part 1

Physical Layer

Simplified Specification

Version 2.00

September 25, 2006

SD Group

Matsushita Electric Industrial Co., Ltd. (Panasonic) SanDisk Corporation

Toshiba Corporation

Technical Committee

SD Card Association

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Revision History

Date Version Changes compared to previous issue

April 3, 2006 1.10 Physical Layer Simplified Specification Version 1.10 initial release.

(Supplementary Notes Ver1.00 is applied.)

September 25, 2006 2.00 Physical Layer Simplified Specification Version 2.00

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Conditions for publication

Publisher:

SD Card Association

2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615, Fax: +1 (925) 886-4870

E-mail: office@sdcard.org

Copyright Holders:

The SD Group

Matsushita Electric Industrial Co., Ltd. (Panasonic) SanDisk Corporation (SanDisk)

Toshiba Corporation (Toshiba) The SD Card Association

Notes:

The copyright of the previous versions (Version 1.00 and 1.01) and all corrections or non-material changes thereto are owned by SD Group.

The copyright of material changes to the previous versions (Version 1.01) are owned by SD Card Association.

Disclaimers:

The information contained herein is presented only as a standard specification for SD Card and SD Host/Ancillary products. No responsibility is assumed by SD Card Association for any damages, any infringements of patents or other right of the third parties, which may result from its use. No license is granted by implication or otherwise under any patent or rights of SD Group and SD Card Association or others.

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Conventions Used in This Document

Naming Conventions

• Some terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.

Numbers and Number Bases

• Hexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h.

• Binary numbers are written with a lower case “b” suffix (e.g., 10b).

• Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.

• All other numbers are decimal.

Key Words

• May: Indicates flexibility of choice with no implied recommendation or requirement.

• Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.

• Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.

Application Notes

Some sections of this document provide guidance to the host implementers as follows:

Application Note:

This is an example of an application note.

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Table of Contents

1. General Description...1

2. System Features ...3

3. SD Memory Card System Concept ...5

3.1 Read-Write Property ... 5

3.2 Supply Voltage... 5

3.3 Card Capacity... 5

3.4 Speed Class ... 6

3.5 Bus Topology ... 7

3.6 Bus Protocol ... 7

3.6.1 SD Bus ... 7

3.6.2 SPI Bus ... 10

3.7 SD Memory Card–Pins and Registers... 11

4. SD Memory Card Functional Description ...12

4.1 General... 12

4.2 Card Identification Mode... 13

4.2.1 Card Reset ... 13

4.2.2 Operating Condition Validation... 13

4.2.3 Card Initialization and Identification Process ... 15

4.3 Data Transfer Mode ... 17

4.3.1 Wide Bus Selection/Deselection ...19

4.3.2 2 GByte Card ... 19

4.3.3 Data Read ... 19

4.3.4 Data Write ... 20

4.3.5 Erase... 22

4.3.6 Write Protect Management ... 22

4.3.7 Card Lock/Unlock Operation ... 23

4.3.7.1 General ... 23

4.3.7.2 Parameter and the Result of CMD42 ... 25

4.3.7.3 Forcing Erase ... 27

4.3.7.3.1 Force Erase Function to the Locked Card... 27

4.3.7.4 Relation Between ACMD6 and Lock/Unlock State... 28

4.3.7.5 Commands Accepted for Locked Card ... 28

4.3.7.6 Two Types of Lock/Unlock Card... 29

4.3.8 Content Protection ... 29

4.3.9 Application-Specific Commands...29

4.3.9.1 Application-Specific Command – APP_CMD (CMD55)... 29

4.3.9.2 General Command - GEN_CMD (CMD56) ... 30

4.3.10 Switch Function Command ...31

4.3.10.1 General ... 31

4.3.10.2 Mode 0 Operation - Check Function ... 32

4.3.10.3 Mode 1 Operation - Set Function... 33

4.3.10.4 Switch Function Status... 35

4.3.10.4.1 Busy Status Indication for Functions ... 36

4.3.10.4.2 Data Structure Version ... 37

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4.3.10.4.3 Function Table of Switch Command ... 37

4.3.10.5 Relationship between CMD6 data & other commands ... 38

4.3.10.6 Switch Function Flow Example ... 38

4.3.10.7 Example of Checking ... 38

4.3.11 High-Speed Mode (25 MB/sec interface speed)... 39

4.3.12 Command System... 39

4.3.13 Send Interface Condition Command (CMD8) ... 40

4.3.14 Command Functional Difference in High Capacity SD Memory Card... 41

4.4 Clock Control ... 42

4.5 Cyclic Redundancy Code (CRC) ... 43

4.6 Error Conditions... 45

4.6.1 CRC and Illegal Command ... 45

4.6.2 Read, Write and Erase Timeout Conditions ... 45

4.6.2.1 Read ... 45

4.6.2.2 Write ... 45

4.6.2.3 Erase ... 45

4.7 Commands ... 46

4.7.1 Command Types ... 46

4.7.2 Command Format ... 46

4.7.3 Command Classes... 46

4.7.4 Detailed Command Description ... 49

4.8 Card State Transition Table ... 56

4.9 Responses... 58

4.9.1 R1 (normal response command):... 58

4.9.2 R1b... 58

4.9.3 R2 (CID, CSD register) ... 58

4.9.4 R3 (OCR register) ... 59

4.9.5 R6 (Published RCA response) ...59

4.9.6 R7 (Card interface condition) ... 59

4.10 Two Status Information of SD Memory Card ... 61

4.10.1 Card Status ... 61

4.10.2 SD Status ... 65

4.11 Memory Array Partitioning ... 68

4.12 Timings ... 68

4.13 Speed Class Specification ... 69

4.13.1 Allocation Unit (AU) ... 69

4.13.2 Recording Unit (RU)... 69

4.13.3 Write Performance ... 69

4.13.4 Read Performance ... 69

4.13.5 Performance Curve Definition ... 69

4.13.6 Speed Class Definition ... 69

4.13.7 Consideration for Inserting FAT Update during Recording... 70

4.13.8 Measurement Conditions and Requirements of the Speed Class... 70

4.14 Erase Timeout Calculation... 71

4.14.1 Erase Unit ... 71

4.14.2 Case Analysis of Erase Time Characteristics... 71

4.14.3 Method for Erase Large Areas ...72

4.14.4 Calculation of Erase Timeout Value Using the Parameter Registers ... 72

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5.2 CID register ... 75

5.3 CSD Register... 77

5.3.1 CSD_STRUCTURE ... 77

5.3.2 CSD Register (CSD Version 1.0) ... 78

5.3.3 CSD Register (CSD Version 2.0) ... 86

5.4 RCA register ... 89

5.5 DSR register (Optional) ... 89

5.6 SCR register ... 89

6. SD Memory Card Hardware Interface...91

6.1 Hot Insertion and Removal ... 91

6.2 Card Detection (Insertion/Removal) ... 91

6.3 Power Protection (Insertion/Removal)... 91

6.4 Power Scheme ... 91

6.4.1 Power Up ... 91

6.4.2 Power Down and Power Cycle... 92

6.5 Programmable Card Output Driver (Optional) ... 92

6.6 Bus Operating Conditions... 92

6.7 Bus Timing (Default) ... 92

6.8 Bus Timing (High-Speed Mode)... 92

7. SPI Mode...93

7.1 Introduction... 93

7.2 SPI Bus Protocol ... 93

7.2.1 Mode Selection and Initialization... 94

7.2.2 Bus Transfer Protection... 96

7.2.3 Data Read ... 96

7.2.4 Data Write ... 97

7.2.5 Erase & Write Protect Management... 98

7.2.6 Read CID/CSD Registers... 99

7.2.7 Reset Sequence... 99

7.2.8 Error Conditions ... 99

7.2.9 Memory Array Partitioning... 99

7.2.10 Card Lock/Unlock... 99

7.2.11 Application Specific Commands ... 99

7.2.12 Content Protection Command... 99

7.2.13 Switch Function Command ... 100

7.2.14 High-Speed Mode ... 100

7.2.15 Speed Class Specification... 100

7.3 SPI Mode Transaction Packets ... 101

7.3.1 Command Tokens ... 101

7.3.1.1 Command Format... 101

7.3.1.2 Command Classes ... 101

7.3.1.3 Detailed Command Description ... 102

7.3.1.4 Card Operation for CMD8 in SPI mode ... 108

7.3.2 Responses ... 109

7.3.2.1 Format R1... 109

7.3.2.2 Format R1b... 109

7.3.2.3 Format R2...110

7.3.2.4 Format R3...110

7.3.2.5 Formats R4 & R5 ...111

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7.3.2.6 Format R7...111

7.3.3 Control Tokens ... 111

7.3.3.1 Data Response Token...111

7.3.3.2 Start Block Tokens and Stop Tran Token...111

7.3.3.3 Data Error Token...112

7.3.4 Clearing Status Bits ... 113

7.4 Card Registers... 114

7.5 SPI Bus Timing Diagrams... 114

7.6 SPI Electrical Interface ... 114

7.7 SPI Bus Operating Conditions... 114

7.8 Bus Timing... 114

8. SD Memory Card Mechanical Specification ... 115

Appendix A ... 116

A.1 Connector... 116

A.2 Related Documentation... 116

Appendix B... 117

B.1 Abbreviations and terms... 117

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Table of Figures

Figure 1-1: SD Specifications Documentation Structure ... 1

Figure 3-1: Hosts-Cards Usability... 6

Figure 3-2: “no response” and “no data” Operations ... 7

Figure 3-3: (Multiple) Block Read Operation ... 7

Figure 3-4: (Multiple) Block Write Operation... 8

Figure 3-5: Command Token Format... 8

Figure 3-6: Response Token Format ... 8

Figure 3-7: Data Packet Format - Usual Data ... 9

Figure 3-8: Data Packet Format - Wide Width Data ... 10

Figure 4-1: SD Memory Card State Diagram (card identification mode)... 14

Figure 4-2: Card Initialization and Identification Flow (SD mode)... 16

Figure 4-3: SD Memory Card State Diagram (data transfer mode)... 17

Figure 4-4: Use of Switch Command... 32

Figure 4-5: Busy Status of ‘Command System’ ... 36

Figure 4-6: CRC7 Generator/Checker ... 43

Figure 4-7: CRC16 Generator/Checker ... 44

Figure 4-8: Definition of Allocation Unit (AU) ... 69

Figure 4-9: Three Performance Curves ... 70

Figure 4-10: Example Erase Characteristics (Case 1 TOFFSET=0) ... 71

Figure 4-11: Example Erase Characteristics (Case 2 TOFFSET=2) ... 72

Figure 5-1: ERASE_BLK_EN = 0 Example ... 83

Figure 5-2: ERASE_BLK_EN = 1 Example ... 83

Figure 6-1: Power-up Diagram ... 91

Figure 7-1: SD Memory Card State Diagram (SPI mode)... 94

Figure 7-2: SPI Mode Initialization Flow ... 95

Figure 7-3: Single Block Read Operation ... 96

Figure 7-4: Read Operation - Data Error ... 97

Figure 7-5: Multiple Block Read Operation... 97

Figure 7-6: Single Block Write Operation ... 97

Figure 7-7: Multiple Block Write Operation ... 98

Figure 7-8: ‘No data’ Operations... 98

Figure 7-9: R1 Response Format ... 109

Figure 7-10: R2 Response Format ...110

Figure 7-11: R3 Response Format ...110

Figure 7-12: R7 Response Format ...111

Figure 7-13: Data Error Token ...112

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Table of Tables

Table 3-1: SD Memory Card Registers ...11

Table 4-1: Overview of Card States vs. Operation Modes ... 12

Table 4-2: Read Command Blocklen ... 20

Table 4-3: Write Command Blocklen ... 20

Table 4-4: Lock Card Data Structure ... 23

Table 4-5: Lock Unlock Function (Basic Sequence for CMD42) ... 26

Table 4-6: Force Erase Function to the Locked Card (Relation to the Write Protects)... 27

Table 4-7: Relation between ACMD6 and the Lock/Unlock State ... 28

Table 4-8: Version Difference of Lock/Unlock Functions... 29

Table 4-9: Available Functions ... 34

Table 4-10: Status Data Structure ... 36

Table 4-11: Data Structure Version ... 37

Table 4-12: Status Code of Mode 0 to Supported Function Group ... 37

Table 4-13: Status Code of Mode 1 to Supported Function Group ... 38

Table 4-14: Status Code of Mode 0 and 1 to Unsupported Function Group ... 38

Table 4-15: Format of CMD8 ... 40

Table 4-16: Command Format... 46

Table 4-17: Card Command Classes (CCCs)... 48

Table 4-18: Basic Commands (class 0) ... 50

Table 4-19: Block-Oriented Read Commands (class 2)... 50

Table 4-20: Block-Oriented Write Commands (class 4) ... 51

Table 4-21: Block Oriented Write Protection Commands (class 6) ... 52

Table 4-22: Erase Commands (class 5) ... 52

Table 4-23: Lock Card (class 7)... 53

Table 4-24: Application-specific Commands (class 8) ... 53

Table 4-25: I/O Mode Commands (class 9) ... 54

Table 4-26: Application Specific Commands used/reserved by SD Memory Card... 55

Table 4-27: Switch Function Commands (class 10)... 55

Table 4-28: Card State Transition Table... 57

Table 4-29: Response R1 ... 58

Table 4-30: Response R2 ... 58

Table 4-31: Response R3 ... 59

Table 4-32: Response R6 ... 59

Table 4-33: Response R7 ... 59

Table 4-34: Voltage Accepted in R7... 60

Table 4-35: Card Status ... 63

Table 4-36: Card Status Field/Command - Cross Reference... 64

Table 4-37: SD Status... 66

Table 4-38: Speed Class Code Field ... 66

Table 4-39: Performance Move Field... 66

Table 4-40: AU_SIZE Field ... 67

Table 4-41: Maximum AU size ... 67

Table 4-42: Erase Size Field... 67

Table 4-43: Erase Timeout Field... 68

Table 4-44: Erase Offset Field ... 68

Table 5-1: OCR Register Definition ... 74

Table 5-2: The CID Fields... 75

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Table 5-5: TAAC Access Time Definition ... 79

Table 5-6: Maximum Data Transfer Rate Definition ... 79

Table 5-7: Supported Card Command Classes ... 80

Table 5-8: Data Block Length ... 80

Table 5-9: DSR Implementation Code Table... 81

Table 5-10: VDD, min Current Consumption ... 81

Table 5-11: VDD, max Current Consumption... 81

Table 5-12: Multiply Factor for the Device Size ... 82

Table 5-13: R2W_FACTOR ... 84

Table 5-14: Data Block Length ... 84

Table 5-15: File Formats... 85

Table 5-16: The CSD Register Fields (CSD Version 2.0) ... 86

Table 5-17: The SCR Fields ... 89

Table 5-18: SCR Register Structure Version... 89

Table 5-19: Physical Layer Specification Version ... 90

Table 5-20: SD Supported Security Algorithm ... 90

Table 5-21: SD Memory Card Supported Bus Widths... 90

Table 7-1: Command Format... 101

Table 7-2: Command Classes in SPI Mode ... 102

Table 7-3: Commands and Arguments ... 106

Table 7-4: Application Specific Commands used/reserved by SD Memory Card - SPI Mode ... 107

Table 7-5: Card Operation for CMD8 in SPI Mode ... 108

Table 7-6: SPI Mode Status Bits ...114

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1. General Description

SD Memory Card is a memory card that is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. The SD Memory Card will include a content protection mechanism that complies with the security of the SDMI standard and will be faster and capable of higher Memory capacity. The SD Memory Card security system uses mutual authentication and a "new cipher algorithm" to protect against illegal usage of the card content. A Non-secure access to the user‘s own content is also available.

SD memory cards may also support a second security system based on commonly used standards, such as ISO-7816, which can be used to interface the SD memory card into public networks and other systems supporting mobile e-commerce and digital signature applications.

In addition to the SD Memory Card, there is the SD I/O (SDIO) Card. The SDIO Card specification is defined in a separate specification named: "SDIO Card Specification" that can be obtained from the SD Association. The SDIO Specification defines an SD card that may contain interfaces between various I/O units and an SD Host. The SDIO card may contain memory storage capability as well as its I/O functionality. The Memory portion of SDIO card shall be fully compatible to the given SD Memory Card specification. The SDIO card is based on and compatible with the SD Memory card. This compatibility includes mechanical, electrical, power, signalling, and software. The intent of the SD I/O card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an I/O card inserted into a non-SDIO aware host will cause no physical damage or disruption of that device or its software. In this case, the I/O card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card will be via the normal means described in the given SD Physical Specification with some extensions that are described in the SDIO Specification.

The SD Memory Card communication is based on an advanced 9-pin interface (Clock, Command, 4xData and 3xPower lines) designed to operate in at maximum operating frequency of 50 MHz and low voltage range. The communication protocol is defined as a part of this specification.

The SD Specifications are divided into several documents. The SD Specifications documentation structure is given in Figure 1-1.

SD

Specifications Security Spec

SD Specifications Physical Layer Spec.

(This Document)

Mc-EX interface Specification

SDIO Card Specification Audio Specification Other Application Documents

File System Specification

Figure 1-1: SD Specifications Documentation Structure

Audio Specification:

This specification, along with other application specifications, describes the specification of a specific application (in this case - Audio Application) and the requirements to implement it.

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Memory Card (in protected and un-protected areas).

Security Specification:

The specification describes the content protection mechanism and the application-specific commands that support it.

Physical Layer Specification (this document):

The specification describes the physical interface and the command protocol used by the SD Memory Card.

The purpose of the Physical Layer specification is to define the SD Memory Card, its environment, and handling.

The document is divided into several portions. Chapter 3 gives a general overview of the system concepts. The common SD Memory Card characteristics are described in Chapter 4. As this description defines an overall set of card properties, we recommend using the product documentation in parallel.

The card registers are described in Chapter 5.

Chapter 6 defines the electrical parameters of the SD Memory Card’s hardware interface.

Chapter 8 describes the physical and mechanical properties of the SD Memory Cards and the minimal recommendations to the card slots or cartridges.

As used in this document, “shall” or “will” denote a mandatory provision of the standard. “Should”

denotes a provision that is recommended but is not mandatory. “May” denotes a feature, which may or may not be present–at the option of the implementer–and whose presence does not preclude compliance.

• Mc-EX Interface Specification: (This section was added in version 1.10)

Part A1 of the SD memory card specification (refer to Figure 1-1) serves as an extension to the SD card Physical Layer Specification and provides all of the definitions required to transfer the Mobile Commerce Extension (Mc-EX) command packets from the Mc-EX host to the Mc-EX enabled SD memory card, and vice versa.

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2. System Features

Targeted for portable and stationary applications

Memory capacity:

Standard Capacity SD Memory Card: Up to and including 2 GB

High Capacity SD Memory Card: More than 2GB (This version of specification limits capacity up to and including 32GB)

Voltage range:

High Voltage SD Memory Card – Operating voltage range: 2.7-3.6 V

Dual Voltage SD Memory Card – Operating voltage range: Low Voltage Range (T.B.D) and 2.7-3.6 V

Designed for read-only and read/write cards.

Default mode: Variable clock rate 0 - 25 MHz, up to 12.5 MB/sec interface speed (using 4 parallel data lines)

High-Speed mode: Variable clock rate 0 - 50 MHz, up to 25 MB/sec interface speed (using 4 parallel data lines)

Switch function command supports High-Speed, eCommerce, and future functions

Correction of memory field errors

Card removal during read operation will never harm the content

Content Protection Mechanism - Complies with highest security of SDMI standard.

Password Protection of cards (CMD42 - LOCK_UNLOCK)

Write Protect feature using mechanical switch

Built-in write protection features (permanent and temporary)

Card Detection (Insertion/Removal)

Application specific commands

Comfortable erase mechanism

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Protocol attributes of the communication channel:

SD Memory Card Communication Channel Six-wire communication channel

(clock, command, 4 data lines) Error-protected data transfer

Single or Multiple block oriented data transfer

SD Memory Card Form-factor

Standard Size SD Memory Card: Specified in this specification (See Chapter 6 and 8) miniSD Memory Card: Specified in “miniSD Memory Card Specification”

microSD Memory Card: Specified in “microSD Memory Card Specification”

Standard Size SD Memory Card thickness is defined as both 2.1 mm (normal) and 1.4 mm (Thin SD Memory Card).

All features in this specification are applied to Standard Size SD Memory Card.

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3. SD Memory Card System Concept

Description here is a blank for the Simplified Specification.

3.1 Read-Write Property

In terms of read-write property, two types of SD Memory Cards are defined:

• Read/Write (RW) cards (Flash, One Time Programmable - OTP, Multiple Time Programmable - MTP). These cards are typically sold as blank (empty) media and are used for mass data storage, end user video, audio or digital image recording

• Read Only Memory (ROM) cards. These cards are manufactured with fixed data content. They are typically used as a distribution media for software, audio, video etc.

3.2 Supply Voltage

In terms of operating supply voltage, two types of SD Memory Cards are defined:

• High Voltage SD Memory Cards that can operate within the voltage range of 2.7-3.6 V.

• Dual Voltage SD Memory Cards –Dual Voltage SD Memory Cards that can operate within the voltage range of Low Voltage Range (T.B.D) and 2.7-3.6 V.

Note that details of Dual Voltage SD Memory Card will be defined in future specification.

3.3 Card Capacity

In terms of capacity, two types of SD Memory Cards are defined:

• Standard Capacity SD Memory Cards supports capacity up to and including 2 G bytes (231 bytes).

All versions of the Physical Specifications define the Standard Capacity SD Memory Card.

• High Capacity SD Memory Cards supports capacity more than 2 G bytes (231 bytes) and this version of specification limits capacity up to and including 32 GB. High Capacity SD Memory Card is newly defined from the Physical Layer Specification Version 2.00.

Only hosts that are compliant to the Physical Layer Specification version 2.00 or higher and the SD File System Specification Ver2.00 can access High Capacity SD Memory Cards. Other hosts fail to initialize High Capacity SD Memory Cards (See Figure 3-1).

Note:

1. The Part 1 Physical Layer Specification Version 2.00 and Part 2 File System Specification Version 2.00 allow Standard Capacity SD Memory Cards to have capacity up to and including 2 GB and High Capacity SD Memory Cards to have capacity up to and including 32 GB. SD Memory Cards with a capacity greater than 32 GB will be available with updated versions of Part 1 and Part 2 Specifications.

2. Hosts that can access (read and/or write) SD Memory Cards with a capacity greater than 2 GB and up to and including 32 GB, shall also be able to access SD Memory Cards with a capacity of 2 GB or less.

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Figure 3-1: Hosts-Cards Usability

• 2 types of High Capacity SD Memory Card are specified. Type A (Single State Card) has single High Capacity memory area. Details of Type A are specified in the Physical Layer Specification version 2.00. Type B (Dual State Card) has both High Capacity memory area and Standard Capacity memory area. In Type B card, only one memory area can be used at any given time. A mechanical switch is used to select the desired memory area. Details of Type B will be defined in future specifications. It is not necessary for the host to distinguish card types.

3.4 Speed Class

Four Speed Classes are defined and indicate minimum performance of the cards

• Class 0 - These class cards do not specify performance. It includes all the legacy cards prior to this specification, regardless of its performance

• Class 2 - Are more than or equal to 2 MB/sec performance.

• Class 4 - Are more than or equal to 4 MB/sec performance.

• Class 6 - Are more than or equal to 6 MB/sec performance.

High Capacity SD Memory Cards shall support Speed Class Specification and have performance more than or equal to Class 2.

Note that the unit of performance [MB/sec] indicates 1000x1000 [Byte/sec] while the unit of data size [MB] indicates 1024x1024 [Byte]. This is because the maximum SD Bus speed is specified by the maximum SD clock frequency (25 [MB/sec] = 25000000 [Byte/sec] at 50 MHz) and data size is based on memory boundary (power of 2).

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3.5 Bus Topology

This section is a blank for the Simplified Specification.

3.6 Bus Protocol 3.6.1 SD Bus

Communication over the SD bus is based on command and data bit streams that are initiated by a start bit and terminated by a stop bit.

• Command: a command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.

• Response: a response is a token that is sent from an addressed card, or (synchronously) from all connected cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line.

• Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.

Figure 3-2: “no response” and “no data” Operations

Card addressing is implemented using a session address, assigned to the card during the initialization phase. The structure of commands, responses and data blocks is described in Chapter 4. The basic transaction on the SD bus is the command/response transaction (refer to Figure 3-2). This type of bus transaction transfers their information directly within the command or response structure. In addition, some operations have a data token.

Data transfers to/from the SD Memory Card are done in blocks. Data blocks are always succeeded by CRC bits. Single and multiple block operations are defined. Note that the Multiple Block operation mode is better for faster write operation. A multiple block transmission is terminated when a stop command follows on the CMD line. Data transfer can be configured by the host to use single or multiple data lines.

command response command response

block read operation data stop operation

CMD DAT

from host to card

stop command stops data transfer data from card

to host from

card to host

data block crc data block crc data block crc

multiple block read operation

Figure 3-3: (Multiple) Block Read Operation

The block write operation uses a simple busy signaling of the write operation duration on the DAT0 data

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Figure 3-4: (Multiple) Block Write Operation Command tokens have the following coding scheme:

Figure 3-5: Command Token Format

Each command token is preceded by a start bit (0) and succeeded by an end bit (1). The total length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated.

Response tokens have one of four coding schemes, depending on their content. The token length is either 48 or 136 bits. The detailed commands and response definition is given in Chapter 4.7. The CRC protection algorithm for block data is a 16-bit CCITT polynomial. All allowed CRC types are described in Chapter 4.5.

0 0 CONTENT 1

total length=48 bits start bit:

always'0' transmitter bit:

'0'=card response

end bit:

always '1' Response content: mirrored command and status infor-

mation (R1 response), OCR register (R3 response) or RCA (R6), protected by a 7bit CRC checksum

R1, R3,R6

0 0 CONTENT=CID or CSD

total length=136 bits

R2 1

end bit:

always '1'

CRC

Figure 3-6: Response Token Format

In the CMD line the Most Significant Bit (MSB) is transmitted first, the Least Significant Bit (LSB) is the last.

When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 3-8). Start and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are calculated and checked for every DAT line individually. The CRC status response and Busy indication will be sent by the card to the host on DAT0 only (DAT1-DAT3 during that period are don’t care).

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There are two types of Data packet format for the SD card.

(1) Usual data (8-bit width): The usual data (8-bit width) are sent in LSB (Least Significant Byte) first, MSB (Most Significant Byte) last sequence. But in the individual byte, it is MSB (Most Significant Bit) first, LSB (Least Significant Bit) last.

(2) Wide width data (SD Memory Register): The wide width data is shifted from the MSB bit.

Figure 3-7: Data Packet Format - Usual Data

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Ex. SD Status

b511 b0

b7 b499

b503 b507

b511 b3 CRC 1

0

Start bit End bit

DAT3

DAT2 DAT1 DAT0

Data Packet Format for Wide Bus (all four lines used) Data Packet Format for Standard Bus (only DAT0 used)

b6 b498

b502 b506

b510 b2 CRC 1

0

b5 b497

b501 b505

b509 b1 CRC 1

0

b4 b496

b500 b504

b508 b0 CRC 1

0

b508 b509 b510

b511 b0 CRC 1

0

Start bit End bit

DAT0 Wide Width

Data

2. Data Packet Format for Wide Width Data (Ex. ACMD13)

[SD memory]

ACMD13(SD Status), ACMD51(SCR), etc

Ex. b1

Figure 3-8: Data Packet Format - Wide Width Data

3.6.2 SPI Bus

Details of the SPI Bus protocol are described in Chapter 7.

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3.7 SD Memory Card–Pins and Registers

A part of this section is not described.

Each card has a set of information registers (see Chapter 5):

Name Width Description

CID 128 Card identification number; card individual number for identification (See 5.2).

Mandatory.

RCA1 16 Relative card address; local system address of a card, dynamically suggested by the card and approved by the host during initialization (See 5.4). Mandatory.

DSR 16 Driver Stage Register; to configure the card’s output drivers (See 5.5). Optional.

CSD 128 Card Specific Data; information about the card operation conditions (See 5.3).

Mandatory

SCR 64 SD Configuration Register; information about the SD Memory Card’s Special Fea- tures capabilities (See 5.6). Mandatory

OCR 32 Operation conditions register (See 5.1). Mandatory.

SSR 512 SD Status; information about the card proprietary features (See 4.10.2).

Mandatory

CSR 32 Card Status; information about the card status (See 4.10.1). Mandatory (1) RCA register is not used (available) in SPI mode

Table 3-1: SD Memory Card Registers

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4. SD Memory Card Functional Description

4.1 General

All communication between host and cards is controlled by the host (master). The host sends com- mands of two types: broadcast and addressed (point-to-point) commands.

• Broadcast commands

Broadcast commands are intended for all cards. Some of these commands require a response.

• Addressed (point-to-point) commands

The addressed commands are sent to the addressed card and cause a response from this card.

A general overview of the command flow is shown in Figure 4-1 for card identification mode and in Figure 4-3 for data transfer mode. The commands are listed in the command tables (Table 4-18- Table 4-27). The dependencies between current state, received command, and following state are listed in Table 4-28. In the following sections, the various card operation modes will be described first. Afterwards, the restrictions for controlling the clock signal are defined. All SD Memory Card commands, along with the corresponding responses, state transitions, error conditions and timings are presented in the succeeding sections.

Two operation modes are defined for the SD Memory Card system (host and cards):

• Card identification mode

The host will be in card identification mode after reset and while it is looking for new cards on the bus. Cards will be in this mode after reset until the SEND_RCA command (CMD3) is received.

• Data transfer mode

Cards will enter data transfer mode after their RCA is first published. The host will enter data transfer mode after identifying all the cards on the bus.

The following table shows the dependencies between operation modes and card states. Each state in the SD Memory Card state diagram (see Figure 4-1) is associated with one operation mode:

Card state Operation mode Inactive State inactive

Idle State Ready State Identification State

card identification mode

Stand-by State Transfer State Sending-data State Receive-data State Programming State Disconnect State

data transfer mode

Table 4-1: Overview of Card States vs. Operation Modes

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4.2 Card Identification Mode

While in card identification mode the host resets all the cards that are in card identification mode, validates operation voltage range, identifies cards and asks them to publish Relative Card Address (RCA). This operation is done to each card separately on its own CMD line. All data communication in the Card Identification Mode uses the command line (CMD) only.

During the card identification process, the card shall operate in the SD clock frequency of the identification clock rate fOD (see Chapter 6.7).

4.2.1 Card Reset

The command GO_IDLE_STATE (CMD0) is the software reset command and sets each card into Idle State regardless of the current card state. Cards in Inactive State are not affected by this command.

After power-on by the host, all cards are in Idle State, including the cards that have been in Inactive State before.

After power-on or CMD0, all cards’ CMD lines are in input mode, waiting for start bit of the next com- mand. The cards are initialized with a default relative card address (RCA=0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability).

4.2.2 Operating Condition Validation

At the start of communication between the host and the card, the host may not know the card supported voltage and the card may not know whether it supports the current supplied voltage. The host issues a reset command (CMD0) with a specified voltage while assuming it may be supported by the card. To verify the voltage, a following new command (CMD8) is defined in the Physical Layer Specification Version 2.00.

SEND_IF_COND (CMD8) is used to verify SD Memory Card interface operating condition. The card checks the validity of operating condition by analyzing the argument of CMD8 and the host checks the validity by analyzing the response of CMD8 (See Chapter 4.3.13). The supplied voltage is indicated by VHS filed in the argument. The card assumes the voltage specified in VHS as the current supplied voltage. Only 1-bit of VHS shall be set to 1 at any given time. Both CRC and check pattern are used for the host to check validity of communication between the host and the card.

If the card can operate on the supplied voltage, the response echoes back the supply voltage and the check pattern that were set in the command argument.

If the card cannot operate on the supplied voltage, it returns no response and stays in idle state. It is mandatory to issue CMD8 prior to first ACMD41 for initialization of High Capacity SD Memory Card (See Figure 4-1). Receipt of CMD8 makes the cards realize that the host supports the Physical Layer Version 2.00 and the card can enable new functions.

It is also mandatory for low-voltage host to send CMD8 before ACMD41. In case that a Dual Voltage Card is not receiving CMD8 the card will work as a high-voltage only card, and in this case that a low- voltage host didn't send CMD8 the card will go to inactive at ACMD41.

SD_SEND_OP_COND (ACMD41) is designed to provide SD Memory Card hosts with a mechanism to identify and reject cards which do not match the VDD range desired by the host. This is accomplished by the host sending the required VDD voltage window as the operand of this command (See Chapter 5.1).

Cards which cannot perform data transfer in the specified range shall discard themselves from further bus operations and go into Inactive State. The levels in the OCR register shall be defined accordingly (See Chapter 5.1). Note that ACMD41 is application specific command, therefore APP_CMD (CMD55) shall always precede ACMD41. The RCA to be used for CMD55 in idle_state shall be the card’s default RCA = 0x0000.

After the host issues a reset command (CMD0) to reset the card, the host shall issue CMD8 prior to ACMD41 to re-initialize the SD Memory card.

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Identification State(ident)

ACMD41

CMD3

from all states except (ina)

from all states in data- transfer- mode cards with non compatible

voltage range card returns busy(*1)or

host omitted voltage range

Power on

Card responds with new RCA

Card responds with new RCA

data- transfer mode card- identification mode

No Response (Non valid command) Must be a

MultiMediaCard CMD0 + CS Asserted

("0")

CMD2 Ready State

(ready) Idle State

(idle) CMD0

CMD3

CMD15 Inactive

State(ina)

Stand- by State (stby) SPI Operation

Mode

initialization process starting at CMD1

CMD8

If card cannot operate under supplied voltage, card doesn't respond and return to 'Idle State'

(*1) Note : Card returns busy when

- Card executes internal initialization process -

This means that CMD8 is mandatory to initialize High capacity SD Memory Card.

It is mandatory for the host compliant to Physical Spec Version 2.00 to send CMD8 before ACMD41

Identification State(ident)

ACMD41

CMD3

- -

or

Power on

- -

CMD2 Ready State

(ready) Idle State

(idle) CMD0

CMD3

CMD15 Inactive

State(ina)

Stand- by State (stby) SPI Operation

Mode

Start MultiMediaCard initialization process starting at CMD1

CMD8

-

- Card is High capacity SD Memory Card and host doesn't support High capacity

Figure 4-1: SD Memory Card State Diagram (card identification mode)

By setting the OCR to zero in the argument of ACMD41, the host can query each card and determine the common voltage range before sending out-of-range cards into the Inactive State (query mode). This query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. The card does not start initialization if ACMD41 is issued as a query. Afterwards, the host may choose a voltage for operation and reissue ACMD41 with this condition, sending incompatible cards into the Inactive State.

During the initialization procedure, the host is not allowed to change the operating voltage range. Refer to the power up sequence as described in Chapter 6.4.

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4.2.3 Card Initialization and Identification Process

After the bus is activated the host starts card initialization and identification process (See Figure 4-2).

The initialization process starts with SD_SEND_OP_COND (ACMD41) by setting its operational conditions and the HCS bit in the OCR. The HCS (Host Capacity Support) bit set to 1 indicates that the host supports High Capacity SD Memory card. The HCS (Host Capacity Support) bit set to 0 indicates that the host does not support High Capacity SD Memory card.

Receiving of CMD8 expands the ACMD41 function; HCS in the argument and CCS (Card Capacity Status) in the response. HCS is ignored by cards, which didn’t respond to CMD8. However the host should set HCS to 0 if the card returns no response to CMD8. Standard Capacity SD Memory Card ignores HCS. If HCS is set to 0, High Capacity SD Memory Card never return ready statue (keep busy bit to 0). The busy bit in the OCR is used by the card to inform the host that initialization of ACMD41 is completed. Setting the busy bit to 0 indicates that the card is still initializing. Setting the busy bit to 1 indicates completion of initialization. The host repeatedly issues ACMD41 until the busy bit is set to 1.

The card checks the operational conditions and the HCS bit in the OCR only at the first ACMD41. While repeating ACMD41, the host shall not issue another command except CMD0.

If the card responds to CMD8, the response of ACMD41 includes the CCS field information. CCS is valid when the card returns ready (the busy bit is set to 1). CCS=1 means that the card is a High Capacity SD Memory Card.

CCS=0 means that the card is a Standard Capacity SD Memory Card.

The host performs the same initialization sequence to all of the new cards in the system. Incompatible cards are sent into Inactive State. The host then issues the command ALL_SEND_CID (CMD2), to each card to get its unique card identification (CID) number. Card that is unidentified (i.e. which is in Ready State) sends its CID number as the response (on the CMD line). After the CID was sent by the card it goes into Identification State. Thereafter, the host issues CMD3 (SEND_RELATIVE_ADDR) asks the card to publish a new relative card address (RCA), which is shorter than CID and which is used to address the card in the future data transfer mode. Once the RCA is received the card state changes to the Stand-by State. At this point, if the host wants to assign another RCA number, it can ask the card to publish a new number by sending another CMD3 command to the card. The last published RCA is the actual RCA number of the card.

The host repeats the identification process, i.e. the cycles with CMD2 and CMD3 for each card in the system.

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Figure 4-2: Card Initialization and Identification Flow (SD mode)

ACMD41 with HCS=0

No response

Power-on

CMD0

Ver2.00 or later SD Memory Card

CMD8

Non- compatible voltage range or check pattern is not correct Ver2.00 or later SD Memory Card(voltage mismatch)

or Ver1.X SD Memory Card or not SD Memory Card

Compatible voltage range and check pattern is correct

ACMD41 with HCS=0or1

Card returns response

Valid Response?

Card with compatible Voltage range

Card is ready?

Card returns busy

cards with non compatible voltage range or time- out(no response or busy) occurs Card is

ready?

cards with non compatible voltage range(card goes to 'ina' state) or time-out

(no response or busy) occurs Unusable

Card

Unusable Card

Unusable Card Card returns

busy Card returns

ready

Ver1.X Standard Capacity

SD Memory Card

CCS in Response?

Card returns ready

Ver2.00 or later Standard Capacity

SD Memory Card

Ver2.00 or later High Capacity SD Memory Card CCS=0

CCS=1 Not SD Memory Card

No response

CMD2

CMD3

If host supports high capacity, HCS is set to 1

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4.3 Data Transfer Mode

Until the end of Card Identification Mode the host shall remain at fOD frequency because some cards may have operating frequency restrictions during the card identification mode. In Data Transfer Mode the host may operate the card in fPP frequency range (see Chapter 6.7). The host issues SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), e.g. block length, card storage capacity, etc.

The broadcast command SET_DSR (CMD4) configures the driver stages of all identified cards. It programs their DSR registers corresponding to the application bus layout (length) and the number of cards on the bus and the data transfer frequency. The clock rate is also switched from fOD to fPP at that point. SET_DSR command is an option for the card and the host.

CMD7 is used to select one card and put it into the Transfer State. Only one card can be in the Transfer State at a given time. If a previously selected card is in the Transfer State its connection with the host is released and it will move back to the Stand-by State. When CMD7 is issued with the reserved relative card address “0x0000”, all cards are put back to Stand-by State (Note that it is the responsibility of the Host to reserve the RCA=0 for card de-selection - refer to Table 4-18, CMD7.

Figure 4-3: SD Memory Card State Diagram (data transfer mode)

This may be used before identifying new cards without resetting other already registered cards. Cards which already have an RCA do not respond to identification commands (ACMD41, CMD2, see Chapter 4.2.3) in this state.

Important Note: The card de-selection is done if certain card gets CMD7 with un-matched RCA. That happens automatically if selection is done to another card and the CMD lines are common. So, in SD Memory Card system it will be the responsibility of the host either to work with common CMD line (after initialization is done) - in that case the card de-selection will be done automatically or if the CMD lines are separate then the host shall be aware to the necessity to de-select cards.

All data communication in the Data Transfer Mode is point-to point between the host and the selected

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The relationship between the various data transfer modes is summarized below.

• All data read commands can be aborted any time by the stop command (CMD12). The data transfer will terminate and the card will return to the Transfer State. The read commands are: block read (CMD17), multiple block read (CMD18), send write protect (CMD30), send scr (ACMD51) and general command in read mode (CMD56).

• All data write commands can be aborted any time by the stop command (CMD12). The write commands shall be stopped prior to deselecting the card by CMD7. The write commands are: block write (CMD24 and CMD25), program CSD (CMD27), lock/unlock command (CMD42) and general command in write mode (CMD56).

• As soon as the data transfer is completed, the card will exit the data write state and move either to the Programming State (transfer is successful) or Transfer State (transfer failed).

• If a block write operation is stopped and the block length and CRC of the last block are valid, the data will be programmed.

• The card may provide buffering for block write. This means that the next block can be sent to the card while the previous is being programmed.

If all write buffers are full, and as long as the card is in Programming State (see SD Memory Card state diagram Figure 4-3 ), the DAT0 line will be kept low (BUSY).

• There is no buffering option for write CSD, write protection and erase. This means that while the card is busy servicing any one of these commands, no other data transfer commands will be accepted. DAT0 line will be kept low as long as the card is busy and in the Programming State.

Actually if the CMD and DAT0 lines of the cards are kept separated and the host keep the busy DAT0 line disconnected from the other DAT0 lines (of the other cards) the host may access the other cards while the card is in busy.

• Parameter set commands are not allowed while card is programming.

Parameter set commands are: set block length (CMD16), erase block start (CMD32) and erase block end (CMD33).

• Read commands are not allowed while card is programming.

• Moving another card from Stand-by to Transfer State (using CMD7) will not terminate erase and programming operations. The card will switch to the Disconnect State and will release the DAT line.

• A card can be reselected while in the Disconnect State, using CMD7. In this case the card will move to the Programming State and reactivate the busy indication.

• Resetting a card (using CMD0 or CMD15) will terminate any pending or active programming operation. This may destroy the data contents on the card. It is the host’s responsibility to prevent this.

• CMD34-37, CMD50 and CMD57 are reserved for SD command system expansion. State transitions for these commands are defined in each command system specification.

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4.3.1 Wide Bus Selection/Deselection

Wide Bus (4 bit bus width) operation mode may be selected/deselected using ACMD6. The default bus width after power up or GO_IDLE (CMD0) is 1 bit bus width.

In order to change the bus width two conditions shall be met:

a) The card is in ‘tran state‘.

b) The card is not locked

A locked card will responds to ACMD6 as illegal command.

4.3.2 2 GByte Card

To make 2GByte card, the Maximum Block Length (READ_BL_LEN=WRITE_BL_LEN) shall be set to 1024 bytes. However, the Block Length, set by CMD16, shall be up to 512 bytes to keep consistency with 512 bytes Maximum Block Length cards (Less than and equal 2GByte cards).

4.3.3 Data Read

The DAT bus line level is high by the pull-up when no data is transmitted. A transmitted data block consists of start bits (1 or 4 bits LOW), followed by a continuous data stream. The data stream contains the payload data (and error correction bits if an off-card ECC is used). The data stream ends with end bits (1 or 4 bits HIGH). The data transmission is synchronous to the clock signal. The payload for block oriented data transfer is protected by 1 or 4 bits CRC check sum (See Chapter 3.6).

The Read operation from SD Memory Card may be interrupted by turning the power off. The SD Memory Card ensures that data is not destroyed during all the conditions except write or erase operations issued by the host even in the event of sudden shut down or removal.

Read command is rejected if BLOCK_LEN_ERROR or ADDRESS_ERROR occurred and no data transfer is performed.

Block Read

Block read is block oriented data transfer. The basic unit of data transfer is a block whose maximum size is always 512 bytes. Smaller blocks whose starting and ending address are entirely contained within 512 bytes boundary may be transmitted.

Block Length set by CMD16 can be set up to 512 bytes regardless of READ_BL_LEN.

A CRC is appended to the end of each block ensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and after completing the transfer, the card returns to the Transfer State. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.

Blocks will be continuously transferred until a STOP_TRANSMISSION command (CMD12) is issued.

The stop command has an execution delay due to the serial command transmission. The data transfer stops after the end bit of the stop command.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed, the card shall detect a block misalignment at the beginning of the first misaligned block, set the ADDRESS_ERROR error bit in the status register, abort transmission and wait in the Data State for a stop command.

Table 4-2 defines the card behavior when a partial block accesses is enabled.

If the misaligned block is the first data block of the command (i.e. ADDRESS_ERROR was reported in the actual response to the command), then no data is transferred and the card remains in the TRAN state.

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CSD value Max block size

READ_BL_LEN Misalign Partial

Current Blocklen*1

Read CMD Start Address

512Bytes 0 (Disable) 1 (Enable) 1- 512 bytes Any address is accepted. *2 1kBytes 0 (Disable) 1 (Enable) 1- 512 bytes Any address is accepted. *2 2kBytes 0 (Disable) 1 (Enable) 1- 512 bytes Any address is accepted. *2

*1: “Current Blocklen" size is set or changed by CMD16. If value is less than or equal 512 bytes (There are no relations with Misalign and Partial option), it is set with no error.

*2: When the Blocklen size data range crosses 512 bytes block boundary, card outputs the data until the 512 bytes block boundary” and then the data becomes invalid and CRC error also may occur. The card will send “ADDRESS_ERROR" on the next command response. Host should issue CMD12 to recover.

Table 4-2: Read Command Blocklen

4.3.4 Data Write

The data transfer format is similar to the data read format. For block oriented write data transfer, the CRC check bits are added to each data block. The card performs 1 or 4 bits CRC parity check (See Chapter 4.5) for each received data block prior to the write operation. By this mechanism, writing of erroneously transferred data can be prevented.

Write command is rejected if BLOCK_LEN_ERROR or ADDRESS_ERROR occurred and no data transfer is performed.

Block Write

During block write (CMD24 - 27, 42, 56(w)) one or more blocks of data are transferred from the host to the card with 1 or 4 bits CRC appended to the end of each block by the host. A card supporting block write shall be required that Block Length set by CMD16 shall be 512 bytes regardless of WRITE_BL_LEN is set to 1k or 2k bytes.

Table 4-3 defines the card behavior when partial block accesses is disabled (WRITE_BL_PARTIAL = 0).

CSD value Max block size

WRITE_BL_LEN Misalign Partial

Current Blocklen *1

Write CMD Start Address

512Bytes 0 (Disable) 0 (Disable) 512 bytes *2 n * 512 bytes *3 (n: Integer) 1kBytes 0 (Disable) 0 (Disable) 512 bytes *2 n * 512 bytes *3 (n: Integer) 2kBytes 0 (Disable) 0 (Disable) 512 bytes *2 n * 512 bytes *3 (n: Integer)

*1: “Current Blocklen” size is set or changed by CMD16. If value is less than 512 bytes (there are no relations with Misalign and Partial option), it is set with no error. And then “Current Blocklen” size is tested when write command execution.

*2: If the current Blocklen is other than this value, the card indicates “BLOCK_LEN_ERROR” on the Write command response.

*3: If start address is other than this value, the card will send “ADDRESS_ERROR” on the Write command response.

Table 4-3: Write Command Blocklen

If WRITE_BL_PARTIAL is allowed (=1) then smaller blocks, up to resolution of one byte, can be used as well. If the CRC fails, the card shall indicate the failure on the DAT line (see below); the transferred data will be discarded and not be written, and all further transmitted blocks (in multiple block write mode) will be ignored.

Multiple block write command shall be used rather than continuous single write command to make faster write operation.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is

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not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card shall detect the block misalignment error and abort programming before the beginning of the first misaligned block. The card shall set the ADDRESS_ERROR error bit in the status register, and while ignoring all further data transfer, wait in the Receive-data-State for a stop command.

Note that the first data block is misaligned for write command (i.e. ADDRESS_ERROR is reported in the actual response of the write command), the card remains in tran state and no data is programmed.

The write operation shall also be aborted if the host tries to write over a write protected area. In this case, however, the card shall set the WP_VIOLATION bit.

Programming of the CSD register does not require a previous block length setting. The transferred data is also CRC protected. If a part of the CSD register is stored in ROM, then this unchangeable part shall match the corresponding part of the receive buffer. If this match fails, then the card will report an error and not change any register contents.

Some cards may require long and unpredictable times to write a block of data. After receiving a block of data and completing the CRC check, the card will begin writing and hold the DAT0 line low if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The status bit READY_FOR_DATA indicates whether the card can accept new data or whether the write process is still in progress). The host may deselect the card by issuing CMD7 (to select a different card) which will displace the card into the Disconnect State and release the DAT line without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling DAT to low if programming is still in progress and the write buffer is unavailable. Actually, the host may perform simultaneous write operation to several cards with inter-leaving process. The interleaving process can be done by accessing each card separately while other cards are in busy. This process can be done by proper CMD and DAT0-3 line manipulations (disconnection of busy cards).

Pre-erased Setting prior to a Multiple Block Write Operation

Setting a number of write blocks to be pre-erased (ACMD23) will make a following Multiple Block Write operation faster compared to the same operation without preceding ACMD23. The host will use this command to define how many number of write blocks are going to be send in the next write operation. If the host will terminate the write operation (Using stop transmission) before all the data blocks sent to the card the content of the remaining write blocks is undefined(can be either erased or still have the old data). If the host will send more number of write blocks than defined in ACMD23 the card will erase block one by one(as new data is received). This number will be reset to the default (=1) value after Multiple Blocks Write operation.

It is recommended using this command preceding CMD25, some of the cards will be faster for Multiple Write Blocks operation. Note that the host should send ACMD23 just before WRITE command if the host wants to use the pre-erased feature. If not, pre-erase-count might be cleared automatically when another commands (ex: Security Application Commands) are executed.

Send Number of Written Blocks

Systems that use Pipeline mechanism for data buffers management are, in some cases, unable to determine which block was the last to be well written to the flash if an error occurs in the middle of a Multiple Blocks Write operation. The card will respond to ACMD22 with the number of well written blocks.

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4.3.5 Erase

It is desirable to erase many write blocks simultaneously in order to enhance the data throughput.

Identification of these write blocks is accomplished with the ERASE_WR_BLK_START (CMD32), ERASE_WR_BLK_END (CMD33) commands.

The host should adhere to the following command sequence: ERASE_WR_BLK_START, ERASE_WR_BLK_END and ERASE (CMD38).

If an erase (CMD38) or address setting (CMD32, 33) command is received out of sequence, the card shall set the ERASE_SEQ_ERROR bit in the status register and reset the whole sequence.

If an out of sequence command (except SEND_STATUS) is received, the card shall set the ERASE_RESET status bit in the status register, reset the erase sequence and execute the last command.

If the erase range includes write protected sectors, they shall be left intact and only the non protected sectors shall be erased. The WP_ERASE_SKIP status bit in the status register shall be set.

The address field in the address setting commands is a write block address in byte units. The card will ignore all LSB’s below the WRITE_BL_LEN (see CSD) size.

As described above for block write, the card will indicate that an erase is in progress by holding DAT0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card or perform card disconnection, as described in the Block Write section, above.

The data at the card after an erase operation is either ‘0’ or ‘1’, depends on the card vendor.

The SCR register bit DATA_STAT_AFTER_ERASE (bit 55) defines whether it is ‘0’ or ‘1’.

4.3.6 Write Protect Management

Three write protect methods are supported in the SD Memory Card as follows:

- Mechanical write protect switch (Host responsibility only) - Card internal write protect (Card’s responsibility)

- Password protection card lock operation.

Mechanical Write Protect Switch

A mechanical sliding tablet on the side of the card (refer to the mechanical description Chapter 8) will be used by the user to indicate that a given card is write protected or not. If the sliding tablet is positioned in such a way that the window is open it means that the card is write protected. If the window is close the card is not write-protected.

A proper, matched, switch on the socket side will indicate to the host that the card is write-protected or not. It is the responsibility of the host to protect the card. The position of the write protect switch is un- known to the internal circuitry of the card.

Card’s Internal Write Protection (Optional)

This section is a blank for the Simplified Specification.

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4.3.7 Card Lock/Unlock Operation

4.3.7.1 General

The password protection feature enables the host to lock a card while providing a password, which later will be used for unlocking the card. The password and its size are kept in a 128-bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase them.

Locked cards respond to (and execute) all commands in the "basic" command class (class 0), ACMD41, CMD16 and “lock card” command class. Thus, the host is allowed to reset, initialize, select, query for status, etc., but not to access data on the card. If the password was previously set (the value of PWD_LEN is not 0), the card will be locked automatically after power on.

Similar to the existing CSD register write commands, the lock/unlock command is available in "transfer state" only. This means that it does not include an address argument and the card shall be selected before using it.

The card lock/unlock command has the structure and bus transaction type of a regular single block write command. The transferred data block includes all the required information of the command (password setting mode, PWD itself, card lock/unlock etc.). Table 4-4 describes the structure of the command data block. Note that the host compliant to the SD Physical Specification Version 2.00 shall set reserved bits (Bit7-4) to 0 when issuing CMD42.

Byte # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 Reserved

(shall be set to 0)

ERASE LOCK_

UNLOCK

CLR_

PWD

SET_

PWD

1 PWDS_LEN 2

...

PWDS_LEN + 1

Password data

Table 4-4: Lock Card Data Structure

• ERASE: 1 Defines Forced Erase Operation. In byte 0, bit 3 will be set to 1 (all other bits shall be 0). All other bytes of this command will be ignored by the card.

• LOCK/UNLOCK: 1 = Locks the card. 0 = Unlock the card (note that it is valid to set this bit together with SET_PWD but it is not allowed to set it together with CLR_PWD).

• CLR_PWD: 1 = Clears PWD.

• SET_PWD: 1 = Set new password to PWD

• PWDS_LEN: Defines the following password(s) length (in bytes). In case of a password change, this field includes the total password lengths of old and new passwords.

The password length is up to 16 bytes. In case of a password change, the total length of the old password and the new password can be up to 32 bytes.

• Password data: In case of setting a new password, it contains the new password. In case of a password change, it contains the old password followed by the new password.

The data block size shall be defined by the host before it sends the card lock/unlock command. The block length shall be set to greater than or equal to the required data structure of the lock/unlock command. In the following explanation, changing block size by CMD16 is not a mandatory requirement for the lock/unlock command.

Figure

Updating...

References

Related subjects :