A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle
研究生 張湘輝 指導教授 劉深淵博士
台大電子所電子電路實驗室 http://analog12.ee.ntu.edu.tw/
With the evolution and continuing scaling of CMOS technologies, the demand of high speed and high integration density VLSI systems have exponential growth recently. However, the synchronization problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high performance systems.
Phase-locked loops (PLLs) and Delay-locked loops（DLLs）have been typically employed for the purpose of synchronization. Due to the difference of their configuration, the DLLs are preferred for their unconditional stability and faster locking time than the PLLs. Additionally, a DLL offers better jitter performance than a PLL because noise in the voltage-controlled delay line (VCDL) does not accumulate over many clock cycles.
Conventional DLLs may suffer from harmonic locking over wide operating range as shown in Fig.1. If the DLLs would operate at lower frequency without harmonic locking, the number of delay stages must be increased to let the maximum delay of the delay line equal to the period of the lowest frequency. However, the maximum operating frequency of a DLL will be limited by the minimum delay of the delay line.
A DLL with wide-range operation and fixed latency of one clock cycle is proposed by using the phase selection circuit and the start-controlled circuit. The proposed DLL not only locks the delay equal to one clock cycle but also operates without the restrictions stated above. By the way, the operating frequency range of the proposed DLL can be increased. The architecture of the proposed DLL is shown in Fig. 2. It is composed of a conventional analog DLL, a phase selection circuit and a start-controlled circuit. Before the DLL begins to lock, the phase selection circuit will choose an appropriate delay cell to
be a feedback signal (vcdl_clk) according to different frequencies of input signal. In other words, the
number of the delay cells may change at different input frequencies. The minimum delay, TDmin, of the
delay line is determined by one unit-delay cell. The maximum delay can be decided as N×TDmax where N
is the number of unit-delay cells. Thus, the operating frequency range of the DLL can be from 1/(3TDmin)
to 1/(N×TDmax).
ref_clk
Tclk
The first rising edge of ouput clock should be located in this range
vcdl_clk1 ( normal lock ) vcdl_clk2 ( normal lock ) vcdl_clk3 ( false lock ) vcdl_clk4 ( false lock )
Fig.1 The DLL in normal lock and false lock conditions
VCDL
Phase Detector Charge Pump
Vctrl ref_clk vcdl_clk Start-Controlled setupb startb 1 2 3 4 9 10
Phase Selection Circuit
3
φ φ9 φ10
3
Fig.2 System architecture of the proposed DLL
