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Effect of nickel concentration on source/drain series resistance and channel resistance of Ni-metal-induced crystallization thin-film transistors

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Effect of nickel concentration on source/drain series resistance and channel

resistance of Ni-metal-induced crystallization thin-

film transistors

Ming-Hui Lai

a

, YewChung Sermon Wu

a

, Jung-Jie Huang

b,

a

Department of Materials Science and Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC bDepartment of Materials Science and Engineering, Ming Dao University, 369 Wen-Hua Road, Peetow, Changhua 52345, Taiwan, ROC

a b s t r a c t

a r t i c l e i n f o

Available online 25 January 2013 Keywords:

Metal-induced crystallization (MIC) Thinfilm transistors (TFTs) Poly-Si

Ni concentration Source/drain resistance

The Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Most studies have focused only on reducing Ni contamination because Ni residues cause high leakage current in MIC–TFTs. Also of concern is the source/drain (S/D) series resistance, which degrades the device performance (driving ability) that might vary with the Ni concentration in MIC–TFTs. Improving the driving ability of MIC–TFTs requires a detailed understanding of how Ni residues affect S/D series resistance. This study investigates how Ni concen-tration affects S/D series resistance by using the transmission line method. The results of this study provide further insight into how Ni concentration and resistance are related. The results show that the S/D series resistance and channel resistance decreased with a reduction in Ni concentration in MIC poly-Si because of better crystalline quality and lower degradation of the donor concentration. This phenomenon was caused by the Ni concentration forming less NiSi2nucleation sites to generate a large grain size; Ni atoms serve as

acceptor-like dopants in silicon, which counteract with the effects of n-type doping, subsequently reducing the donor concentration in the S/D region.

© 2013 Elsevier B.V. All rights reserved.

1. Introduction

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely applied to high-resolution integrated active-matrix organic light-emitting diodes, which exhibit good electrical prop-erties and can be used to realize of glass substrates[1]. In various fabri-cations for LTPS, metal-induced crystallization (MIC) is promising for use because of its low cost, good uniformity, low crystallization temper-ature (approximately 500 °C) and short crystallization time (0.5 to 5 h) [2,3]. However, Ni and NiSi2residues in poly-Sifilm increase the leakage

current and shift the threshold voltage[4,5]. As is well known, the leak-age current can be reduced by lowering the Ni concentration by em-ploying certain technologies such as the gettering method[6], metal-induced crystallization through a cap layer (MICC)[7], and ultra-thin Nifilms by atomic layer deposition[8].

Whereas most studies have focused only on reducing Ni contami-nation to improve the leakage current, lowering the Ni concentration may change the source/drain (S/D) series resistance of MIC–TFTs. In-evitably, the S/D series resistance negatively influences the device performance, especially the on-state current and mobility [9–14]. This phenomenon is a serious issue because of the increased ratio of

the S/D series resistance of short-channel devices. Therefore, improv-ing the performance of MIC–TFTs requires a detailed understanding of how the Ni concentration affects S/D series resistance. However, ex-actly how Ni concentration and series resistance are related at the S/D region has not been examined.

In this study, the S/D series resistance of MIC–TFTs was extracted using the transmission line method[9]. The S/D resistance included contact resistance, sheet resistance, and S/D parasitic resistance. Ex-actly how Ni concentration affects the S/D series resistance of MIC– TFTs is also examined using the conventional MIC and MICC to repre-sent high and low Ni concentration devices, respectively. The cap layer was formed using chemical oxide (CF–MIC), which is simpler and more economical than plasma-enhanced chemical vapor deposition (PECVD) SiNx. The study results demonstrate that the S/D series resistance and

channel resistance decreased with the reduction of Ni concentration in MIC poly-Si.

2. Experimental details

This study investigated N-channel poly-Si TFTs. A 100-nm-thick undopedα-Si layer was deposited onto a 500-nm-thick oxide-coated Si wafer by employing a low-pressure chemical vapor deposition (LPCVD) system using SiH4as the precursor gas at 550 °C. To form chemical

oxidefilter MIC poly-Si films (CF–MIC), the samples were dipped into a mixed solution of H2SO4and H2O2for 20 min to form a chemical oxide

filter layer on top of α-Si. A 5-nm-thick Ni film was then deposited Thin Solid Films 544 (2013) 500–503

⁎ Corresponding author. Tel.: +886 4 887 6660x8014; fax: +886 4 887 9050. E-mail address:[email protected](J.-J. Huang).

0040-6090/$– see front matter © 2013 Elsevier B.V. All rights reserved.

http://dx.doi.org/10.1016/j.tsf.2013.01.042

Contents lists available atScienceDirect

Thin Solid Films

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onto the chemical oxide/α-Si by using an e-gun evaporator, as shown in Fig. 1(a). For nickel-induced crystallization ofα-Si, the heat treatment of the sample was performed at 500 °C for 1 h in a N2atmosphere, which is

referred from the MILC growth rate (1μm/h at 500 °C)[15]. Moreover, annealing at 500 °C for 1 h can ensure full crystallization of a-Si. The unreacted Nifilm and chemical oxide layer were then removed by wet etching, as shown inFig. 1(b). The cross-sectional image of the chemical oxide layer, shown inFig. 1(c), was obtained byfield-emission trans-mission electron microscopy (FE-TEM, Jem-2100F, Jeol) operated at 200 keV. Preparation of the TEM sample was polished using a grinder and then damaged using ion-beam milling in the precision ion polishing system.

TFT devices were fabricated using standard IC processes. The islands of poly-Si regions on the wafers were defined by reactive ion etching using CF4- and SF6-reactive gases (manufactured by SAMCO, Japan;

type: RIE-10N). After the cleaning process, a 100-nm-thick tetraethyl orthosilicate/O2 oxide layer was deposited as the gate insulator at

350 °C by PECVD. Thereafter, a 100-nm-thick poly-Sifilm was deposit-ed as the gate electrode by LPCVD. After defining the gate, self-aligned 35 keV phosphorous ions were implanted at a dose of 5 × 1015cm−2

to form the S/D and gate. Dopant activation was performed at 600 °C for 24 h, followed by deposition of the passivation layer and a definition of contact holes. A 500-nm-thick Al layer was then deposited by ther-mal evaporation, and patterned as the electrode. Finally, the sintering process was performed at 400 °C for 30 min in a N2ambient. Thefinal

TFT device is shown inFig. 1(d).

After fabrication of the device, the transfer characteristics of the TFTs were measured at room temperature by using a KEITHLEY 4200 semiconductor parameter analyzer. The S/D series resistance of the TFTs was extracted using the transmission line method[9]. For comparison, a conventional MIC TFT without a chemical oxide layer was also fabricated and measured. The TLM method is generally used to determine the series resistance to conducting materials. How-ever, in this work, the TLM test structure was employed to measure the series resistance of a top-gate TFT device used to induce electrons into the channel. The extraction of S/D series resistance in these gated structures differs slightly from that of the conventional TLM method because the measurement is performed at various gate voltages.

3. Results and discussion

Fig. 2shows the drain-current versus gate-voltage (ID–VG) transfer

characteristics andfield-effect mobility (μFE) of MIC and CF–MIC TFT

de-vices. Thefield-effect mobility (μFE) is extracted from the maximum

value of transconductance at VDS= 0.1 V. The TFT channel length and

width were 20μm and 20 μm respectively. According to this figure, CF–MIC TFTs have excellent electrical characteristics, especially low off-state leakage current and highfield-effect mobility. The leakage cur-rent improvement was attributed to the reduction of Ni concentration in the CF–MIC films. This improvement is due to Ni residues (Ni-related defects) in the poly-Si film serving as deep-level traps to promote the thermionic emission-dominated leakage current in the off-state re-gion[16–18]. In addition, the Ni concentrations in poly-Sifilms were

Fig. 1. Schematic illustration of CF–MIC TFT process: (a) the chemical oxide layer between α-Si layer and Ni layer, (b) removing of remained Ni film and chemical oxide, (c) typical structure of top-gate TFT device, and (d) TEM image of chemical oxide layer.

Fig. 2. Typical ID–VGtransfer characteristics andfiled-effect mobility of conventional MIC and CF–MIC (W/L=20/20 μm).

501 M.-H. Lai et al. / Thin Solid Films 544 (2013) 500–503

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analyzed using the secondary-ion mass spectroscopy (SIMS) depth pro-file (SIMS, IMS-7F, CAMECA) operated at 5 keV of accumulated energy with oxygen primary ions and detected Ni ions per depth of 0.15 nm. As shown inFig. 3, the Ni concentration was reduced by two orders of magnitude in the CF–MIC over that of conventional MIC poly-Si because the chemical oxide layer reduced the content of Ni atoms into the chan-nel layer during the MIC annealing process. With the reduction of the Ni concentration, the minimum leakage current decreased, and therefore, the on/off current ratio increased[6]. Moreover, thefield-effect mobility also increased from 23.5 to 32.3 cm2V−1s−1because of lower

impuri-ty scattering of Ni-related defects and better crystalliniimpuri-ty of CF-MIC poly-Sifilm.

In addition to basic transfer characteristics, the other important issue of MIC–TFTs is the S/D series resistance, which might be changed with Ni concentration. The transmission line method was employed to investigate the S/D series resistance (RS/D), which is a standard

approach for the extraction of RS/Dbyfitting the ON-resistance (RON)

as a function of the channel length. In the linear region of the TFT output characteristics (low drain voltage and high gate voltage), RONis assumed

to consist of channel resistance (RCH) and RS/D. The ON-resistance can be

estimated using the following equations:

RON¼ ∂Vð D=∂IDÞ ¼ RCHþ RS=D ð1Þ

RCH¼ L= Wμ½ oCiðVG−VtÞ ð2Þ

where Ciis the gate oxide capacitance per unit area;μois the intrinsic

car-rier mobility without an S/D resistance effect; and W, L, and Vtare the

device channel width, length, and the intrinsic threshold voltage, respectively.

Fig. 4shows the ON-resistance data of MIC TFTs and CF–MIC TFTs as a function of the channel length. The ON-resistance of TFTs was evaluated at VD= 0.1 V of the TFT output characteristics. The

transis-tors have afixed channel width of 20 μm. The results showed that the ON-resistance increased with the device channel length; a large ON-resistance in the high Ni concentration device (MIC TFT) was also observed. By linearfitting for different gate voltages, the inter-ception with the y-axis indicated the S/D series resistance of TFTs. Fig. 5shows the extracted S/D series resistance and channel resis-tance as a function of the gate voltage. Consequently, the S/D series resistance and channel resistance of the CF–MIC TFT were lower than those of the conventional MIC TFT. In the S/D region, the device with a high Ni concentration (MIC TFT) exhibited a larger S/D series resistance than that of CF–MIC TFT. The S/D series resistance can be affected by the crystalline quality and dopant concentration in the S/D region. First, regarding crystalline quality, samples were annealed at 600 °C for dopant activation and recrystallization after ion implan-tation because the poly-Si in the S/D region was amorphized by a heavily doped implantation at a dosage of 5 × 1015cm−2[19].Fig. 6

shows the Raman spectra of undoped and heavily doped poly-Si films after dopant activation at 600 °C for 24 h. This figure shows a poly-Si peak at 520 cm−1. In contrast, no a-Si peak appears at 480 cm−1, indicating that all samples are transferred to the polycrys-talline structure. The heavily doped poly-Sifilms show a lower Raman spectral intensity because recrystallization of a-Si with Ni at 600 °C is not oriented, and growth is limited by the formation of solid-state crystallization (SPC), subsequently lowering crystallinity in the S/D region. Furthermore, the crystallinity of“CF–MIC+SPC” is superior to that of“MIC+SPC” because the lower number of nucleation sites of NiSi2causes a larger grain size in CF–MIC poly-Si films with a low

Ni concentration[20]. However, the crystallinity of the S/D region is Fig. 3. SIMS depth profiles of nickel and in the structure of poly-Si film after MIC process.

Fig. 4. Measured on-resistance of conventional MIC TFT and CF–MIC TFT as a function of channel length. The transistors have a channel width of 20 μm.

Fig. 5. The extracted S/D series resistance and channel resistance as a function of the gate voltage (W/L = 20/20μm).

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not different in a general recrystallization without Ni because of the only SPC mechanism. Second, the variation in S/D series resistance can also be attributed to the dopant concentration. As is well known, heavily doped implantation can significantly reduce the resis-tance of Sifilms. However, Ni atoms serve as acceptor-like dopants in silicon[21], which counteract the effects of phosphorous doping and ultimately reduce the donor concentration in the S/D region. Hall measurements showed that the carrier concentration decreased from 2.518 × 1015to 8.594 × 1014cm−2, and that the sheet resistance

increased from 205.7 to 261.9Ω/cm2 with increased Ni contents.

Therefore, a high Ni concentration reduces the conductivity of the S/D region, leading to a large S/D series resistance in MIC–TFTs. As mentioned, CF–MIC has a lower S/D series resistance than that of MIC because of a lower Ni concentration.

Moreover, in the channel region, the MIC TFT also shows a larger channel resistance (RCH) because of the high trap-state density and

impurity scattering (Ni-related defects). According toFig. 6, CF–MIC presents a crystalline quality superior to that of MIC at the channel re-gion. The effective trap-state density (Nt) uses the Levinson and Proano

method, which can estimate Ntfrom the slope of the linear segment

of ln [ID/(VG−VFB)] vs. 1 / (VG−VFB)2at a low VDand high VG, where

VFBis defined as the gate voltage that yields the minimum drain current

at VD= 0.1 V[22,23]. The Ntof the CF–MIC TFT is 4.65×1012cm−2,

which is smaller than that of the MIC TFT (6.08× 1012cm−2). These

results imply that the defects are minimized in the CF–MIC TFT because of the reduced Ni concentration. As mentioned, the Ni atoms are obstructers of performance and S/D conductivity of the MIC–TFTs. These results confirmed that it is an efficient means to improve the elec-trical characteristics of a channel and S/D region by reducing the Ni con-centration in MIC–TFTs.

4. Conclusion

This study investigated how Ni concentration affects S/D series re-sistance by using the transmission line method. For comparison, high

and low Ni concentration devices were formed using MIC–TFTs with and without a chemical oxide layer, respectively. Thisfinding pro-vides further insight into how the Ni concentration and resistance of MIC–TFTs are related. Consequently, the channel resistance and S/D series resistance decreased with the reduction of the Ni concen-tration in MIC poly-Si because of improved crystalline quality and a lower degradation of the donor concentration. This phenomenon was caused by the low Ni concentration forming less NiSi2nucleation

sites, resulting in a large grain size; Ni atoms serve as acceptor-like dopants in silicon, which counteract the effects of n-type doping, sub-sequently reducing the donor concentration in the S/D region. In brief, the results of this study demonstrate that the Ni residues ob-struct the performance and S/D conductivity of MIC–TFTs.

Acknowledgments

This project was funded by the Sino American Silicon Products Incorporation and the NSC of the ROC under Grant Nos. 98-2221-E-009-041-MY3 and 100-2221-E-451-005. Technical supports from the National Nano Device Laboratory, Center for Nano Science and Tech-nology and the Nano Facility Center of the National Chiao Tung Univer-sity are also acknowledged.

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ac-tivation at 600 °C for 24 h.

503 M.-H. Lai et al. / Thin Solid Films 544 (2013) 500–503

數據

Fig. 1. Schematic illustration of CF–MIC TFT process: (a) the chemical oxide layer between α-Si layer and Ni layer, (b) removing of remained Ni film and chemical oxide, (c) typical structure of top-gate TFT device, and (d) TEM image of chemical oxide layer.
Fig. 5. The extracted S/D series resistance and channel resistance as a function of the gate voltage (W/L = 20/20 μm).

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