OBDD-based network reliability calculation

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4 JACOBS, G.M., and BRODERSEN, R.W.: ‘A fully asynchronous digital signal processor using self-timed circuits’, ZEEE J. Solid-state Circuits, 1990, 25, (6), pp. 1526-1537

5 BACKHAUS, c.: ‘Performance evaluation of primitives in event- driven-logic’. Tech. Report, Centre for Applied Microelectronics, University of Gran Canaria, Spain, 1994

6 LOPEZ, J.F., ESHRAGHIAN, K., SARMIENTO, R., and NOREZ, A.: ‘Gallium arsenide pseudodynamic latched logic’, Electron. Lett., 1996, 32, (15), pp. 1353-1355

I ESHRAGHIAN, K., SARMIENTO, R., CARBALLO, P.P., and NUREZ, A.: ‘Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation’, Microprocess. Microprogr., 1991, 32, pp. 75-82

OBDD-based network reliability calculation

Fu-Min Yeh and Sy-Yen Kuo

Indexing term: Reliability theory

An efficient method for evaluating the terminal-pair reliability based on an edge expansion tree and using an OBDD (ordered binary decision diagram) is presented. The effectiveness of the algorithm is demonstrated on the larger benchmarks collected in previous work. One notable case of the experimental results for a 2 X 20 lattice network is that the number of nodes in the OBDD is linearly proportional to the number of stages. This is significantly superior to previous algorithms which are based on the sum of disjoint products and has exponential complexity.

Introduction: The terminal-pair reliability is the probability that in a network system at least one path exists between the source and the sink. Theoretically, this reliability is the summation of the probabilities of disjoint paths, but the complexity of identifying all paths or cut sets is exponential. The terminal-pair calculation is a well known NP-hard problem [l], so the determination of reliability is very time-consuming. Therefore, research in terminal-pair reliability [2, 31 has been focused on speeding up the calculation by reducing the computation efforts as much as possible. Previous references have emphasised the improvement of two classical tech- niques: (i) efficient decomposition or factoring of a network with minimal sum of disjoint products (SDP) 11, 21, or (ii) given path/ cut sets to reduce computing redundancy in the sum of disjoint products [3]. Although these algorithms were demonstrated with a reasonable efficiency on medium-scale networks, there still exists one inherent drawback: the sum of disjoint production forms is inefficient in dealing with larger Boolean functions.

In this Letter, an efficient method for evaluating the terminal- pair reliability based on the edge expansion tree using an ordered binary decision diagram (OBDD) is presented. First, the success- path function of a given network is constructed based on the OBDD by traversing a network with edge expansion. The reliability of the network is then obtained by directly evaluating this OBDD recursively.

Four assumptions for terminal-pair reliability are described as follows: (i) the network is modelled as a directed graph (ii) The pi

(success) and q i (failure) probabilities, i = 1, ..., n are known for links; (iii) nodes are fault free; (iv) all failure events are mutually independent statistically.

Symbolic method with an edge expansion tree: A symbolic method for evaluating network reliability based on an edge expansion tree using an OBDD is presented. This tree diagram is able to repre- sent all of the paths between terminal vertices. During the construction of the diagram, a multiple-level Boolean function of the paths, noted as the path function, is efficiently manipulated by the OBDD. Once the OBDD-based path function is obtained, determination of the reliability becomes straightforward. Our method consists of three main steps:

(i) We propose a heuristic approach for a good variable ordering of the OBDD-based path function. Variable ordering is advantageous in the sense that it yields a compact OBDD. Variable ordering of an OBDD-based path function is a consequence of edge variables in the network.

(ii) The path function is built using the OBDD according to the edge expansion tree.

(iii) The network reliability is obtained by recursively evaluating the probability of every node in the OBDD-based path function.

Variable ordering: For a given network G and initial index, first insert the edges connected with the source into a queue and mark these edges; then remove an edge e from the head of the queue. If the queue becomes empty, then the process is completed, other- wise, for each edge connected to e and not marked, insert it into the tail of the queue; then mark these new inserted edges. Declare a new variable of the OBDD for the edge variable e with the cur- rent value of the index. Increase the value of the index by one for the next new variable. Repeat the above steps until the queue becomes empty. This heuristic approach keeps the local property of edge variables as intact as possible and can be referred to as a breadth-first search ordering.

Path function construction with OBDD: In the following, we are to expand a given network into a tree so that the path function can be efficiently constructed by an OBDD. The basic idea of the edge expansion tree is to recursively expand edges of the source for each sub-graph instead of partitioning an s-t path, a cut-set, or an arbitrary edge factoring theorem. Our method is shown as follows: (i) Expand the graph with edges connected to the source. Let (e,, e,,

...,

ek) be edges linked to the source. Expand the given network

G into a number of new subnetworks according to (e,, e,,

...,

ek).

The first term corresponds to e,, the second term e,,

...,

etc.; there are k terms. For each ith term (1

<

i 5 k), perform contracting operations to obtain a new network, Ge,. In Ge,, the vertices originally linked to e, are merged into a single vertex as a new source and all edges originally connected to it are deleted. The path function of G is determined by

P ( G ) = EiP(G*el

+

E2P(G*e2)

+

...

+

E,P(G*e,)

+

...

+

EkP(G*ek)

where P(G) is a path function of G, and E, is a Boolean variable of edge e,.

(ii) Remove redundant vertices to avoid the inefficient manipulation of the numerous redundant expansions. A vertex other than

the source and the sink is called a redundant vertex if only one vertex is connected to it.

(iii) For each network Gq, repeat the above steps until reaching the sink and then return a logical value of True. The final path function of the network is obtained by recursively composing the results of intermediate path functions.

Calculating probability f r o m OBDD: The OBDD is based on Shan- non expansion which is well known as a disjoint decomposing function. Thus, the OBDD can be recognised as being a graph- based set of disjoint products. Given the probability of each variable, the reliability of an OBDD-based function f can be recursively evaluated by

Prob(f) = P(z,)Prob(f,,=l)

+

(I - P(z,))Prob(f,,=o) where x, is the top variable, and f is partitioned into two disjoint setsf(x,,,) andf(xtzo), respectively. Instead of changing the original OBDD node structure, a hash table is used to avoid the redundant computation of the shared nodes in the ProbO procedure. During calculation of the probability, the number of multiplication operations and additions is of the same order as the number of OBDD nodes. ( 2 ) 3x1 0

..::

...

Ei

t 13) 2 x 2 0

;:r

:::

at

Fig. 1 Terminal-pair networks

Experimental results: Our method for determining the terminal- pair reliability has been evaluated on a Sun SPARC 20 worksta- tion with a 128 Mbyte memory. All of the programs are written in

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C language. In the evaluation, we have used larger networks (the number of paths > 500) which is the collection of networks [2, 31 as shown in Fig. 1. All success probabilities of links are 0.9. In Table 1, we first compare our results with those in [2, 31. In [2], they employed the cofactor theorem to partition the network on an arbitrary edge with network reduction rules. An SDP generating method with a random and preprocessed list of path-sets was proposed in [3]. Dpath is the number of disjoint paths. To the best of our knowledge, the best result so far for the minimal number of disjoint products was reported in [3]. Node is the number of OBDD nodes in our method. A comparison of the effectiveness of the SDP form and the OBDD representation would not be straightforward because the OBDD represents a Boolean function by a graph-based set of disjoint products, which differs from the SDP with two level forms. However, we stdl compare the number of disjoint paths to the number of OBDD nodes of our results as a reference. For smaller networks, the performance of the SDP and the OBDD is of the same order as our experiment, but it is not shown in this Letter. When the number of network paths > 500, the number of nodes in the OBDD is significantly lower than the number of paths. However, the number of disjoint products must be greater than the number of paths. Obviously the compact OBDD size is superior to the number of SDPs in the representation of all paths for the analysis of the network reliability problems.

Table 1: Comparisons of representations of SDP and OBDD

N PI

I

L&C [3]

I

EETBDD

Time I DPath I Time I Node I Time Paths Reliability I I . .. I I I 1

I

780

I

0.99712

I

-

I

53298

I

2.6

I

3591

I

0.4 2 I 49322 I 0.96447 I 240.4 I - I - I 257 I 6.7 I I 3

1

524288

1

0.78448

1

-

I

-

1

-

1

115

1

58.8 N: networks, -: no data

L&C: cardinality and lexicographic ordering [2]: on VAX 8530

[3]: on FPS 500 system

The OBDD is not only an effective representation of a Boolean function but is also a graph-based set of disjoint products [4, 51. Once the OBDD-based path function is obtained, the network reliability is efficiently achieved by recursively evaluating the probability of every node in this OBDD. In Table 1, the computation time of [3] is the CPU time in seconds, not including the path-set generating time. All of their preprocessing times are nearest to 0.1 s. The EETBFS is a tree-based partition using OBDD with a breadth-first search ordering. Time is the CPU time in seconds, and includes the time of searching variable ordering, constructing path function with OBDD, and evaluating the probability of the OBDD. One noteworthy result obtained from our experiments is that for a 2 x 20 lattice network, the number of OBDD nodes is linearly proportional to the number of stages. The number of OBDD nodes is incremented by six when one stage is added. This is significantly superior to previous algorithms which are based on the sum of disjoint products and have exponential complexity. The CPU time of reliability calculation for a 20-stage lattice network is only -58.8s with 115 nodes in the generated OBDD.

Conclusions: Our method has avoided many of the limitations of existing algorithms in manipulating larger networks, and the results obtained are superior to those of previous approaches as demonstrated by the networks of Fig. 1. With the proposed approach, we have evaluated the terminal-pair reliability of larger networks, hitherto thought impossible.

0 IEE 1997

Electronics Letters Online No: 19970549

Fu-Min Yeh and Sy-Yen Kuo (Department of Electrical Engineering, Room 415, National Taiwan University, Taipei, Taiwan, Republic of

China)

Sy-Yen Kuo: Corresponding author E-mail: [email protected]

10 February 1997

References

1 BALL, M o : ‘Computational complexity of network reliability analysis: an overview’, IEEE Trans., 1986, R-35, pp. 230-239

2 THEOLOGOU, o.R., and CARLIER, J.G.: ’Factoring and reduction for networks with imperfect vertices’, IEEE Trans. Reliability, 199 1, 40, pp. 210-217

SOH, S., and RAI, s.: ‘Experimental results on preprocessing of path/

cut term in the sum of disjoint products technique’, IEEE Trans. Reliability, 1993, 42, pp. 24-33

4 BRYANT, R.E.: ‘Graph-based algorithms for Boolean function manipulation’, ZEEE Trans., 1986, C-35, (S), pp. 677-691

5 YEH, F.-M., and LIN, c.-s.: ‘OBDD variable ordering by interleaving compacted clusters’, Electron. Lett., 1995, 31, pp. 1724-1725 3

Wired-OR property

a

d ~ t r u ~ t u r e

of

recovered energy

Chulwoo Kim and Soowon Kim

Indexing terms: Logic circuits, Logic design

A modified MOS REL structure is proposed, which exhibits the wired-OR property and enhances speed and power characteristics. Proposed MOS REL gates have been fabricated and tested. It is shown that the power X delay product of an MOS REL inverter is enhanced by 26% with a smaller silicon area.

Introduction: The adiabatic logic family 2N-2N2D [ 11, adiabatic dynamic logic [2], and REL [3], are advantageous in terms of the minimisation of heat dissipation and the recovery of stored energy. Among these logic devices, only logic circuits REL use a TSPC (true single phase clock) which resolves the clock skew problem with ease. In addition, although REL circuits use more transistors and are slower than CMOS logic circuits, they are suit- able for low voltage systems. This Letter presents an improved MOS REL structure, which exhibits the wired-OR property that is useful in logic synthesis. Using a 0 . 8 ~ n-well CMOS process, the proposed circuits have been verified through their use in several test blocks.

Fig. I Basic concept of wired-OR

Wired-OR property: The wiring of the outputs exhibits a wired- OR property as the wired-AND property in an open collector. As an example, a PMOS gate is shown in Fig. 1. When any PMOS gate output is high, the wired output goes high (logical ‘T’), whereas the output remains low (logical ‘F’) as long as both PMOS gate outputs are low. It is apparent that V,,, in Fig. 1 fmc- tions as an output of an OR gate, hence the terminology is justi- fied. Use of the wired-OR property in. logic synthesis could simplify the sophisticated digital building blocks. For example, Fig. 2a shows the third and fourth stages of 4 bit CLA realised by REL. It is easily noted that logical operations are identical to

x

= ( A + B )

@ c =

( A + B ) CBC = Y ₍₁₎ However, using the wired-OR reduces the number of stages as in Fig. 2b. In particular, it requires only a half clock cycle for its operation.

MOS implementation of REL: An REL gate is comprised of input, precharging and output blocks. Hinman, et al., has proposed a method for realising adiabatic logic circuits with BJTs and MOS-