6
JING-WEI LIN and TSUNG-YI HO,National Cheng Kung University
IRIS HUI-RU JIANG,National Chiao Tung University
Electromigration and voltage drop (IR-drop) are two major reliability issues in modern IC design. Electro-migration gradually creates permanently open or short circuits due to excessive current densities; IR-drop causes insufficient power supply, thus degrading performance or even inducing functional errors because of nonzero wire resistance. Both types of failure can be triggered by insufficient wire widths. Although expanding the wire width alleviates electromigration and IR-drop, unlimited expansion not only increases the routing cost, but may also be infeasible due to the limited routing resource. In addition, electromigra-tion and IR-drop manifest mainly in the power/ground (P/G) network. Therefore, taking wire widths into consideration is desirable to prevent electromigration and IR-drop at P/G routing. Unlike mature digital IC designs, P/G routing in analog ICs has not yet been well studied. In a conventional design, analog designers manually route P/G networks by implementing greedy strategies. However, the growing scale of analog ICs renders manual routing inefficient, and the greedy strategies may be ineffective when electromigration and IR-drop are considered. This study distances itself from conventional manual design and proposes an automatic analog P/G router that considers electromigration and IR-drops. First, employing transportation formulation, this article constructs an electromigration-aware rectilinear Steiner tree with the minimum routing cost. Second, without changing the solution quality, wires are bundled to release routing space for enhancing routability and relaxing congestion. A wire width extension method is subsequently adopted to reduce wire resistance for IR-drop safety. Compared with high-tech designs, the proposed approach achieves equally optimal solutions for electromigration avoidance, with superior efficiencies. Furthermore, via indus-trial design, experimental results also show the effectiveness and efficiency of the proposed algorithm for electromigration prevention and IR-drop reduction.
Categories and Subject Descriptors: J.6 [Computer-Aided Engineering]: Computer-aided design General Terms: Algorithms, Design, Performance
Additional Key Words and Phrases: Analog, electromigration, IR-drop, power/ground network, routing, Steiner tree
ACM Reference Format:
Lin, J.-W., Ho, T.-Y., and Jiang, I. H.-R. 2012. Reliability-driven power/ground routing for analog ICs. ACM Trans. Des. Autom. Electron. Syst. 17, 1, Article 6 (January 2012), 26 pages.
DOI = 10.1145/2071356.2071362 http://doi.acm.org/10.1145/2071356.2071362
Authors’ addresses: J.-W. Lin, Department of Computer Science and Information Engineering, National Cheng Kung University, No.1, University Road, Tainan City 701, Taiwan; email: dattle@eda.csie.ncku.edu.tw; T.-Y. Ho (contact author), Department of Computer Science and Informa-tion Engineering, NaInforma-tional Cheng Kung University, No.1, University Road, Tainan City 701, Taiwan; email: tyho@csie.ncku.edu.tw; I. H.-R. Jiang, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, No.1001, Ta-Hsueh Road, Hsinchu City 300, Taiwan; email: huiru.jiang@gmail.com.
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permit-ted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from the Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701, USA, fax +1 (212) 869-0481, or permissions@acm.org.
c
2012 ACM 1084-4309/2012/01-ART6 $10.00
issue in recent years. In digital IC designs, P/G routing can typically be generated and analyzed using power grids [Dutta and Marek-Sadowska 1989; Silva et al. 2008], a subject that has been studied extensively. Nevertheless, because of the specific design rules, analog layout automation is relatively arduous. For analog ICs, studies on the P/G routing problem are scant; routing is usually accomplished manually. Analog de-signers apply their skills and adopt greedy strategies to route P/G networks. However, the growing scale of analog ICs renders manual design inefficient, and greedy strate-gies ineffective. For P/G routing in analog ICs, two major design reliability concerns arise from electromigration and voltage drop (IR-drop) [Todri et al. 2007]. Electromi-gration can open or shorten a wire, thus leading to a permanent circuit failure; IR-drop may also result in insufficient power, hence degrading the performance or even induc-ing functional errors. Both types of failure are triggered by insufficient wire widths. Although expanding the wire width alleviates electromigration and IR-drop, unlimited expansion not only increases the routing cost, but may also be unfeasible due to the limited routing resource. In addition, electromigration and IR-drop manifest mainly in the power/ground (P/G) network. Therefore, routing the P/G network with elaborate considerations of wire widths is desirable to prevent electromigration and IR-drop.
1.1 Background
According to a previous study [Lienig 2006], electromigration may trigger the migra-tion of metal atoms due to excessive current densities in interconnects. When the current density exceeds the tolerance of a metal, the atoms inside the metal suf-fer from two unbalanced forces: the electrostatic field, Ff ield, and the electron wind, Fwind[Lienig 2006]. Ff ieldis caused by the electric field strength in an interconnect, while Fwindis generated by the momentum transfer between electrons and metal ions (atoms). Generally, with an over-stressed current density, Fwindis more powerful than
Ff ield, as shown in Figure 1(a). The unbalanced forces cause the atoms in the metal
to migrate in the direction of the flow of electrons. Over a time period, hillocks (short circuit) and voids (open circuit) are formed, as shown in Figure 1(b) and Figure 1(c), eventually resulting in a permanent circuit failure. The rapid downscaling of circuits has recently led to ever-shrinking interconnects, signifying that the wires suffer from even higher current densities. The shrinking metal also increases the seriousness of the electromigration issue. Electromigration often occurs in interconnects that bear large current flows, such as the P/G network in analog ICs. Black proposed an em-pirical model of electromigration to estimate the mean time to failure (MTT F) of a metal [Black 1969]: MTT F = A Jn · exp Ea k· T , (1)
where A is the material constant, J is the current density, Eais the activation energy (material-dependent), k is the Boltzmann constant, T is the working temperature, and n is a scaling factor (usually set to 2 [Black 1969]). Equation (1) indicates that the current density ( J) and the working temperature (T) greatly influence MTT F. The working temperature might sustain stability and lead MTT F to depend only on
Fig. 1. Electromigration: (a) effect of Ff ieldand Fwindfor a Cu atom; (b) voids (open circuit) caused by
electromigration; (c) hillocks (short circuit) caused by electromigration.
the current density. Hence, during the physical design stage, electromigration-aware routing should be applied; given the maximum tolerable current density of a metal, the router should ensure that the current flow within the metal does not exceed the limit. This study focuses on the current density as the major consideration to prevent electromigration. The current density J is defined as.
J = I Across ≤ J
max, (2)
where I is the current flow, Acrossis the cross-sectional area, and Jmaxis the maximum current density. In modern IC designs, the wire thickness is almost a constant; hence
Across is directly proportional to the wire width Wwire. Recent studies used the total
wire area to estimate the routing cost [Jiang et al. 2010; Lienig and Jerke 2003; Yan and Chen 2008]. The wire area of each wire segment is defined as the multiplication of its wire length Lwireand its wire width Wwire:
Awire= Lwire× Wwire. (3)
Although expanding the wire width helps alleviate electromigration, unlimited ex-panding wire widths increase the routing cost and might be infeasible for a congested design. According to Eq. (1), to meet the target MTT F, the maximum J can be ob-tained. Therefore, to prevent electromigration with the least routing cost, the wire width Wwireshould be proportional to its current flow. This study defines the electromi-gration constraint as the wire width constraint and current density constraint—that is, if a wire is wider to load the current and verify that the current density is under the maximum current density, Jmaxand the width are under the maximum wire width wmax, and the electromigration safety is addressed.
In addition, IR-drop (voltage drop) is caused by excessive wire resistance. Copper has the second lowest electrical resistance of metal: 1.68 × 10−8 · m. Although it is extremely small, when the current is flowing in the copper foils, the small resistance is still harmful to the supply voltage. This phenomenon, referred to as IR-drop, results in a voltage drop available at load devices, which is especially severe for low supply voltages for advanced processes. The IR-drop Vdropis defined as
Vdrop= I× R = I × (ρ × Lwire Across
whereρ is the electrical resistivity of the material (measured in ohm-metres). Since the current flow at any terminal is a constant, the wider and shorter the wires, the lower the IR-drop. If a long wire forms an unfeasible resistance, the wire width can be adequately expanded to reduce the wire resistance and improve IR-drop. As shown in Figure 2, the voltage available at the load device Vloadis Vsupplyminus Vdrop.
1.2 Previous Work
Existing studies chiefly focus on electromigration avoidance [Jiang et al. 2010; Lienig and Jerke 2003; Yan and Chen 2008]. Lienig et al. developed a current-driven wire planning method based on the Delaunay triangulation mesh [Lienig and Jerke 2003]. Given the current source and sink terminals, the method begins with a mesh graph construction. The edges connecting the nearest pairs of terminals are subsequently greedily selected before the wire widths are determined accordingly. However, this method is unsuitable for all circuits. Because edges are only provided from the trian-gulation mesh, if certain nontriantrian-gulation edges are required, this method may not generate feasible solutions. Yan et al. proposed another greedy method that sorts the pairwise area gains of terminals and selects them in a nondecreasing order. This heuristic method may lead to suboptimal solutions [Yan and Chen 2008]. Jiang et al. first proved that this problem belongs to Class P instead of Class NP-hard [Jiang et al. 2010]. This means that electromigration-aware routing can be solved in polynomial time. Based on the greedy-choice property, they modeled the problem on a multisource multisink flow network and solved it optimally. Since their algorithm is strongly poly-nomial, they adopted a fast greedy method to obtain the initial flow. However, the results of this study show that the inferior initial solution costs more iterations of refinement to converge the flow into an optimal solution.
Figure 3 shows the routing results of the aforementioned works on an example with three current sources (terminals with positive current values) and four current sinks (terminals with negative current values) [Jiang et al. 2010]. In Figure 3(a), for exam-ple, a route is present from a source at (4, 6) to a sink at (5, 1). The wire area of this route is 24 (6 (wirelength)×4 (wire width) = 24). The minimum wirelength Steiner tree, shown in Figure 3(a), has the minimum wirelength (33), although without the minimum wire area (182). The wire area can be reduced to 154 and 144 by using the current-density-aware methods proposed by Lienig and Jerke [2003] and Yan and Chen [2008], respectively, as shown in Figure 3(b) and Figure 3(c). Figure 3(d) shows the optimal results from Jiang et al. [2010] of a minimum wire area 142. Compared with Jiang et al. [2010], this study proposes a more empirically efficient optimal algo-rithm for electromigration avoidance.
1.3 Our Contribution
As mentioned above, prior studies have chiefly focused on electromigration-aware wiring topology only. Since both electromigration and IR-drop are essential for P/G routing in analog ICs, this study constructed a P/G routing framework to overcome
Fig. 3. Wire area comparison between previous algorithms and the proposed algorithm: (a) minimum wire-length = 33 and wire area = 182; (b) Lienig et al.: Wire area = 154; (c) Yan et al.: Wire area = 144; (d) the proposed algorithm and that of Jiang et al.: Wire area = 142 (optimal).
Fig. 4. Analog Power/Ground routing example.
electromigration and IR-drop: taking into consideration the maximum tolerable cur-rent density and IR-drop, sources and sinks with curcur-rent values, and the feasible wire width range, the P/G network is routed to meet the current-density and IR-drop bounds. Figure 4 illustrates the analog P/G routing model. Each module contains two pins, one of which is the power pin, and the other is the ground pin. Around the chip, at least one pair of power and ground pads is present. This study provides each module with sufficient supplies while satisfying the electromigration and IR-drop constraints. First, using the transportation formulation [Russell 1969; Winston 2004]for global P/G routing, this study constructed an electromigration-aware rectilinear Steiner tree
Fig. 5. (a) Current vector example. Terminal has value IAssign; (b) simulated current variation in the time
period (t∈ [0, tlast]). Wire is assigned to the terminal with wire widthwRMS. The feasible current region can
be calculated using Jmax· wRMS.
with the minimum routing cost. Second, for detailed P/G routing, without changing the solution quality, wires were bundled to release increased routing space to enhance routability and alleviating congestions. A wire width extension method was subse-quently adopted to reduce wire resistance for IR-drop safety. Compared with high-tech methods, the proposed approach achieves equally optimal solutions for electromigra-tion avoidance, with superior efficiencies. Furthermore, the experimental results show the effectiveness and efficiency of the proposed algorithm not only on electromigration, but also on IR-drop.
The major contributions of this study are as follows:
— This study proposes an automatic analog P/G router considering electromigration and IR-drop.
— This study adopted the transportation formulation to obtain an optimal solution with a superior efficiency to tackle electromigration.
— This study presents effective and efficient wire bundling and wire sizing methods to manage IR-drop.
The remainder of this article is organized as follows: Section 2 provides the problem formulation; Section 3 presents an overview of the proposed framework; Section 4 details the proposed algorithm for electromigration avoidance; Section 5 introduces the algorithm for IR-drop safety; Section 6 shows the experimental results; and last, Section 7 offers conclusions.
2. PROBLEM FORMULATION
This study proposes an automatic analog P/G router considering electromigration and drop. The current is the chief concern for managing the electromigration and IR-drop. In practice, the current varies from each of the different terminals. Thus, the current model of Lienig and Jerke [2003] is adopted for analog ICs. The current value at each time interval is obtained via simulation and saves as a vector. Every terminal is considered with its root mean square (RMS) current value (IRMS), which is calcu-lated by using the vector. The total current in the vector is also calcucalcu-lated. The sum indicates whether the terminal tends to be a source (IAssign≥ 0)) or a sink (IAssign< 0). An example is shown in Figure 5.
Based on the current flow IAssign, the related wire width wRMSis assigned to the terminal. According to Eq. (2), I = J· Across ∝ J · w. The feasible current region (or interval) can be estimated as [−Jmax· wRMS, Jmax· wRMS]. If all current values in the vector are bounded by this interval, the electromigration effect can be avoided, and the IR-drop can also be reduced.
The analog P/G routing, considering the electromigration and IR-drop problem, can be formulated as follows:
Input
— A set of n modules is randomly distributed on the routing layer.
— Each module contains a power pin and a ground pin with their equivalent RMS current values.
— Each module contains the tolerant voltage drop Vdrop.
— A set of m pairs of power pads and ground pads are present with their current values.
— The maximum current density Jmax and the corresponding maximum wire width
wmaxare present.
Objective
— Automatically construct an analog P/G routing solution. — Minimize the total wiring area.
— Reduce IR-drop.
— The power net and ground net should not overlap. Output
— P/G routing topology for analog ICs
In each time period, the total current flow between terminals follows Kirchhoff ’s cur-rent law. If the RMS model is used, the law may not be satisfied. The following section first assumes that the total sum of the current follows the law. The final section shows the inequality between total supply current and total demand current.
Without a loss of generality, in the following section, this study regards the power pads as sources{S1, S2, ..., Sm}, and the power pins as targets {T1, T2, ..., Tn} to develop the proposed algorithm.
3. OVERVIEW OF THE PROPOSED FRAMEWORK
Figure 6 shows an overview of the proposed algorithm. The routing procedure contains two stages: the global routing stage and the detailed routing stage. The global routing stage handles electromigration, while the detailed routing stage manages IR-drop.
The global routing stage involves consideration of the current flow and con-structing an electromigration-aware rectilinear Steiner tree. This study defines the current-driven electromigration-avoidance rectilinear Steiner tree (CDEARST) prob-lem. CDEARST is solved optimally via the transportation formulation. First, the wire-length between terminals is calculated while considering the presence of modules. Because wires cannot cross over modules, modules are regarded as obstacles before performing obstacle-avoiding routing. Second, according to the wirelength computa-tion, the transportation problem is formulated. The basic feasible (BF) solution is obtained by using Russell’s method [Russell 1969], and is verified with an optimality
Fig. 6. Overview of our algorithm.
test. If the BF solution is not optimal, it is refined by the pivot procedure. Third, this study constructs power nets and ground nets by using the transportation formulation individually. In the global routing stage, this study did not handle the overlap between the power nets and ground nets; they will be removed in the detailed routing.
In the detailed routing stage, without altering the optimality, this study performs the wire-bundling procedure, which entails bundling the power (ground) net to release routing space for enhancing the routability and relaxing congestions. Upon perform-ing the wire-bundlperform-ing procedure, the congestion is analyzed. The negotiation-based routing technique is applied, which was introduced in PathFinder [McMurchie and Ebeling 1995] for rip-up and reroute. Finally, after obtaining a routing solution, this study analyzes the IR-drop for each route from the power pad to any power sink by using Eq. (4). The IR-drop value is compared with the tolerant voltage drop Vdrop. If the IR-drop value exceeds Vdrop, the wire width is expanded to increase Awire, and the total IR-drop is reduced to prevent IC failures.
Figure 7 shows the P/G routing results of the benchmark RPG2. RPG2 has ten modules that are randomly distributed in the chip; each module contains two pins: one is the power pin (red), and the other is the ground pin (blue). Around the chip, four power pads and five ground pads are present. Figure 7(a) shows the optimal results of CDEARST after using the transportation approach. Figure 7(b) shows the results of wire bundling from the CDEARST. Figure 7(c) shows the example of our final routing result. Before we perform the realistic detailed routing and deal with the line overlapping, we must estimate the route and congestion. Figure 7(a) shows the global routing result, we allocate the current flow and obtain the initial routing congestion. Then, we further relax the congestion by wire bundling. The example is shown in Figure 7(b). In the two phases, we just estimate the routing resource, so we do not deal with the lines overlapping. That is the reason why vertical lines overlapping
Fig. 7. P/G routing of RPG2.
each other in Figure 7(a) and Figure 7(b). We deal with overlapping problem by both negotiation-based routing method and rip-up and reroute in detailed routing.
4. ELECTROMIGRATION AVOIDANCE
With a set of modules that are randomly distributed on the routing layer, each module contains one power pin and one ground pin with their equivalent RMS current values, a set of power pads around the chip with their supply currents, and a set of ground pads around the chip with their tolerant currents. A CDEARST is constructed to connect
Fig. 8. (a) Si→ Sk→ Tjor Si→ Tj; (b) Si→ Tk→ Tjor Si→ Tj.
all power (ground) pads and power (ground) pins, enabling current sufficiency for each wire segment and minimizing the total wire area.
To tackle the CDEARST problem, obstacle-avoiding routing is first performed to compute the exact wirelength. Thereafter, this study formulates the CDEARST prob-lem as the transportation probprob-lem, and adopts Russell’s method and pivot procedure to obtain the solution. By using Russell’s method, the basic feasible (BF) solution can be achieved before the solution is verified by using the optimality test. If the BF so-lution is not optimal, the pivot procedure is adopted to fix it. Prior to discussing the detailed algorithms, this study provides certain properties of CDEARST and provides alternate proof to show that the CDEARST problem belongs to Class P.
4.1 Property
The solution space of the CDEARST problem can be reduced by using the following properties:
Property 1. Only the current transportation that directly connects a source to a sink requires consideration.
PROOF. A current flow fijis assumed to exist from a source Sito a sink Tj. Figure 8 shows that only two situations must be considered. Only vertical and horizontal lines are allowed for rectilinear routing. Each possible practical route between arbitrary two sources/sinks can be abstracted by the slant wire segment of the length equal to their Manhattan distance. The wire area is obtained by multiplying fijby the Manhattan distance Dij. Since fijis fixed, only the Manhattan distance of the wire requires con-sideration. From the triangle inequality, Dik+ Dkj≥ Dij. Hence, the optimal solution is the direct connection between a source and a sink.
Before this problem is proven to belong to Class P, the transportation problem is introduced as follows:
A set of m supply points from which goods are shipped- the supply point i can supply most Si units. A set of n demand points to which the goods are shipped—the demand point j must receive a minimum of Dj units. Each unit produced at the supply point i and shipped to the demand point j in-curs a cost of Cij. Manage the determination of a minimum-cost plan for transporting goods from a number of sources to a number of destinations. Definition 1. A balanced transportation means that the total supply equals the total demand.
Table I. Isomorphism of Two Problems
CDEARST Transportation Problem Source terminals Supply points
Sink terminals Demand points Source RMS current Supply Siunits good
Sink RMS current Demand Djunits good
Distance between terminals cij Transportation cost Cij
Wire widthwij Shipped xijgood
Minimum wire areacij· wij Minimum cost Z =Cij· xij
A balanced transportation problem can be solved optimally by using linear program-ming in polynomial time. xijis the number of units of goods being transported from the ith source to the jth demand. The formulation follows:
min Z = m i=0 n j=0 Cij· xij (5) s.t. n j=1 xij= Si (i = 1, 2, ..., m) (6) m i=1 xij= Di ( j = 1, 2, ..., n) (7) xij≥ 0 (i = 1, 2..., m; j = 1, 2, ..., n) (8)
Property 2. The Current-Driven Electromigration-Avoidance Rectilinear Steiner Tree (CDEARST) construction belongs to P-class instead of NP-class.
PROOF. Because the transportation problem belongs to P-class, a transformation method in polynomial time for both inputs are constructed before the two problems are isomorphic (or equivalent). The transformation is shown in Table I.
The CDEARST problem thus belongs to P-class, signifying that it can be solved optimally in polynomial time.
Even when only a single wire width is available, this problem is still different from the original Steiner tree routing problem. Figure 9 shows the difference. The problem seems identical when the wire width equals 1. However, differences are present. In Figure 9(a), the route is superposed to reduce the wirelength, which helps decrease the total wirelength without affecting the total wire area. Figure 9(a) and Figure 9(b) are both optimal wire area solutions. If the wire width is constrained to 1, Figure 9(b) is the appropriate solution. Hence, the CDEARST can be solved in polynomial time, although this does not mean that the original Steiner tree routing problem can be solved in polynomial time.
Instead of using the traditional method, (e.g., simplex method) to solve the trans-portation linear programming, an alternative approach is proposed to obtain an opti-mal solution efficiently.
4.2 Obstacle-Avoiding Wirelength Calculation
Before solving the current distribution problem, the distance from each source (supply) to each sink (destination) must be known. Lin et al. [2008] presented an efficient method to construct the obstacle-avoiding spanning graph, which can be used
Fig. 9. Difference between the proposed routing and the original Steiner tree routing: (a) wirelength = 9 and wire area = 12; (b) wirelength = 12 and wire area = 12.
Fig. 10. Obstacle-avoiding wirelength calculation: (a) obstacle-avoiding spanning graph (OASG); (b) adding a source to the OASG; (c) obstacle-avoiding shortest path (OASP).
to calculate the wirelength. However, this study proved that only edges with direct connections between a source and a sink require consideration. Therefore, this study adopted the method in the study by Lin et al., with certain modifications. The mod-ified obstacle-avoidance method comprises (1) an obstacle-avoiding spanning graph (OASG); and (2) an obstacle-avoiding shortest path (OASP). When the route must per-form obstacle-avoiding routing, the OASG step is used. Thereafter, the OASP step is applied to obtain the distance between the single source to all sinks.
4.2.1 Obstacle-Avoiding Spanning Graph (OASG). An OASG is a connected graph that connects all vertices without any edges intersecting obstacles. For speeding up the shortest-path algorithm, this study prevents the algorithm from calculating the dis-tance between any two sources or any two sinks. This step involves constructing the OASG with all sinks and obstacle corners. Thereafter, the source is added to the OASG to obtain the distance between the source to all sinks. Upon reading the input data, the distribution of all obstacles and sinks are analyzed, and the corresponding OASG is constructed, as shown in Figure 10(a). V is a set of vertices of all obstacle corners and U is a set of all sinks. The plane of each vertexv in V ∪ U is divided into four
Fig. 11. (a) Example of the upper-right corner of V; (b) using the horizontal sweeping line approach, with points 1, 5, and 7 connected to the reference point V.
regions, as shown in Figure 11(a). As defined in the study by Lin et al. [2008], a vertex f is a neighbor ofv if no other vertex in V cupU or obstacle is inside or on the bounding box ofv and f . The OASG is constructed by using a sweep line algorithm. Their X and Y coordinates are sorted, as shown in Figure 11(a). A horizontal sweep line technique is subsequently implemented to find all possible connections of neighbor corners, as illustrated in Figure 11(b). The details of the sweep line algorithm can be found in the study by Lin et al. [2008], which proved that the OASG implies the shortest path of any two vertices in V∪ U. This property can help find the shortest obstacle-avoiding path quickly.
4.2.2 Obstacle-Avoiding Shortest Path (OASP). Based on the graph topology, the Manhat-tan disManhat-tance between the source and sinks is obtained. After constructing the OASG, a source is added to the graph and the sweep line algorithm is applied to connect the source and the original OASG. An example of the result of this step is shown in Figure 10(b). Finally, the shortest path from the source to the sink is obtained, which can be implemented using Dijkstras single source shortest path algorithm [Cormen et al. 2009]. The same procedure is performed for all the sources until all the distances between the sources and sinks are obtained. The results are shown in Figure 10(c).
4.3 Transportation Problem
Upon calculating the distance between each source and sink, the current can be dis-tributed. The linear programming solver (e.g., simplex method) is used to obtain the optimal solution. However, this problem tends to have a large number of constraints and variables. Using the traditional simplex method may require extensive computa-tion. Fortunately, certain efficient methods have been proposed [Winston 2004]. This study presents the transportation simplex method in the following sections, that is, a special streamlined algorithm for solving the problem. First, a discussion of how to find a basic feasible (BF) solution is provided. Second, the method for pivoting the BF solution into an optimal solution is shown. Finally, this study describes how to manage the wire width constraint using a separation method.
4.3.1 Basic Feasible Solutions
Definition 2. Basic variables are obtained by the simultaneous solution of the sys-tem of functional constraints. The other variables are nonbasic variables equal to zero. For a linear programming system, the number of basic variables generally equals the number of functional constraints. For a transportation formulation with m sources and n destinations (sinks), the number of functional constraints is m + n. However , if a set
Fig. 12. Russell’s approximation method.
of values satisfies all but one of the constraints of a balanced transportation problem, the values automatically satisfy the other constraint [Winston 2004]. In other words, only m + n− 1 basic variables that yield a basic solution for transportation problems are required. This study illustrates Russell’s approximation method [Russell 1969] to find the m + n− 1 basic variables for a BF solution.
Figure 12 details Russell’s method. In each iteration, the unit cost Cij must be considered to obtain the optimal solution. In the proposed approach, the unit cost Cij is identified as the Manhattan distance between sources and sinks. Figure 13 shows an example of constructing the table. In Figure 13(a), the source with coordinate (12, 2) is used as the example, with the Manhattan distance (unit cost) calculated from (12, 2) to every sink. The result in the table are subsequently shown in Figure 13(b). For each source row i (destination column j), the largest unit cost Cijthat still remains in the row (column) is obtained and set as Ui (Vj). Using Figure 14(a) as the example, the column (13, 11)displays three unit costs (13, 7, and 10). Because the supply is exhausted (i.e., equal to 0), the unit cost (13) is not considered. Hence, the largest unit cost still remaining in the column (13, 11) is 10. V4 = 10 is set, as shown in Figure 14(a). Thereafter, ij = Cij - Ui - Vj is calculated. This value indicates the critical entry, which is chosen as a basic variable. When ijis small, the cost Cijis also small, and the largest unit costs for the row (Ui) and column (Vj) are large. If the minimumijis chosen as a basic variable entry, distributing the current with the small cost is identical. Furthermore, this also prevents distributing the current with the high cost in the row (Ui) and column (Vj). Upon selecting the minimum ij, the allocation is sufficiently enlarged to use up exactly the remaining supply in its row or the remaining demand in its column. Rows or columns that have smaller remaining supplies or demands are removed from consideration. If rows and columns have the same remaining supplies and demands, one is arbitrarily selected. Figure 14(a) hows the third iteration. The values ofij= Cij- Ui- Vjare listed below the unit cost. In this
Fig. 13. An example of how to construct the table.
Fig. 14. Example of Russell’s approximation method.
iteration, the minimum21 = 16 is chosen and x21= 1 is allocated before proceeding to the next iteration. Figure 14(b) shows the entire iteration procedure.
The complexity of Russell’s method is O(m∗ n) for each iteration. Although an-other recognized method can be used, Vogel’s method [Winston 2004], has a complexity
s.t. B · xBV+ N· xNBV= b (10)
xBV, xNBV≥ 0, (11)
where CBV(CNBV) is the row vector of the objective function coefficients for basic (non-basic) variables. xBV(xNBV) represents the basic (nonbasic) variables, and B (N) is the matrix, with its jth column being the constraint column for basic (nonbasic) variables. b is the right-hand side of the constraint. The constraint is multiplied (10) by CBVB−1 and added to (9). The optimal row is obtained as follows:
Z + (CBVB−1N− CNBV)· xNBV= CBVB−1b. (12) Hence, the coefficient of xij, called ¯cij, is obtained in the optimal row with the optimal value CBVB−1b .
¯cij= CBVB−1aij− cij (13)
where aijis the column of constraints, and cijis the objective function coefficient for xij. If xij is increased by 1, the cost directly increases by cij. In addition, increasing xijby 1 is equivalent to reducing the right-hand sides of the ith supply constraint and the jth demand constraint by 1. This increases the Z value−ui− vj. Therefore, if xij is increased by 1, Z increases by a total of cij− ui− vj. If a nonbasic variable xijhas ¯cij= ui+vj−cij> 0, Z can be decreased by ¯cijper unit. Because a minimization problem is solved, the BF solution is optimal if all of the ¯cij values are negative. Otherwise, the biggest positive entry must be pivoted into a basic variable. The ¯cijvalue can be determined after CBVB−1. Since the m+n equations have one redundant equation that can be deleted without altering the feasible region, a constraint was dropped to render CBVB−1with only m + n− 1 elements. The first supply constraint is dropped, and the following assumption is made:
CBVB−1=
u2 u3 · · · um v1 v2 · · · vn
(14) where u2, ..., umcorrespond to m− 1 supply constraints and v1, v2, ..., vncorrespond to n demand constraints. In the optimal row, the coefficient ¯cijof the basic variable xijmust equal zero (¯cij= 0). Thus,
CBVB−1aij− cij= 0 (15)
can be assigned to determine m + n− 1 variables in CBVB−1. Due to the special con-straint of the transportation problem, the number of calculations can be reduced. For each basic variable xijexcept i = 1, the equation ui+vi= cijcan be obtained. If setting u1 = 0, the total equations are followed for any i and j. Therefore, to solve CBVB−1, only the following simultaneous equations require solving:
⎧ ⎨ ⎩ u1 = 0 ui+vj = cij 1≤ i ≤ m, 1 ≤ j ≤ n, xij∈ xBV (16)
Fig. 15. (a) ¯cij= ui+vj− cijwith a signed operation on the table. The most positive entry is ¯c24= +1, which
is chosen as an enter variable to form a loop.θ = min(7, 13) = 7; (b) when all the ¯cij≤ 0, the optimal solution
is obtained.
After obtaining each ui and vj, ¯cij= ui+vj− cijcan be determined for each nonbasic variable. If ¯cij≤ 0 for all nonbasic variables, the BF solution is optimal. Otherwise, the most positive ¯cijis chosen as an enter variable and the pivoting procedure is performed. Figure 15 shows an example of the procedure and the unsigned value in the entry is the original flow value. Figure 15(a) lists the values ui and vj after solving the simultaneous equations in Eq. (16). ¯cij= ui+vj− cijis subsequently determined. The entry at the cross of column 1 and row 2 is used as an example. cij = c12 is the unit cost, and equal to 8. Hence, ¯cij= ¯c12= u1+v2− c12= (−3) + (6) − (8) = −5 is obtained. ¯cijis listed with a signed value under the unit cost in Figure 15(a).
Definition 3. A loop is an ordered sequence that contains at least four different en-tries, and satisfies the following:
(1) Any two continuous entries lie in either the same row or column. (2) Fewer than three entries lie in the same row or column.
(3) The last entry lies in the same row or column as the first entry.
This study starts at the enter variable xijbefore moving along the row or column. When a basic variable is reached, another direction is taken. This procedure is repeated until xijis reached to form a loop. Thereafter, the smallest valueθ is found among all odd entries in the loop. The entries with θ are removed from the basic variables. To perform the pivot,θ is decreased for all odd entries, and increased for all even entries. The superior BF solution is obtained; Figure 15 shows the procedure.
Before adding the wire-size constraint, an approach to solve the unbalance trans-portation is proposed. In this problem, the sum of supplies is not equal to the sum of demands. If the total supply exceeds total demand, a dummy demand terminal can be added to balance the transportation problem. Let the demand of the dummy terminal be equal to the excessive supply, which can also be accomplished when the total de-mand exceeds the total supply. Because the shipment from or to the dummy terminal is not a real shipment, a cost of zero is assigned. With the addition of the dummy termi-nal, this problem can be solved using the aforementioned method. Finally, the dummy terminal can be removed. Although some sources may remain and a certain current or sinks may receive insufficient current, a high-quality electromigration-avoiding rout-ing tree can be obtained.
4.3.3 Wire-Size Constraint Model. In modern IC design, only certain wire sizes can be used. If the wire size is not constrained, an unfeasible solution may be obtained. This study presents a method for preventing the current flow from exceeding the maximum
Fig. 16. (a)wmax= 5 and the source S1is separated into S11and S 2
1. The cost from S 2
1to T1is set to M; (b) optimal solution with wire constraint. Wire area = 154.
wire sizewmax. Upon obtaining the optimal solution, the feasibility of the current flow is checked. If a source contains a current of more than wmax, the excess current is diverted to sinks.
To prevent the source Sifrom supplying current that exceeds Pi, Siis separated into {S1
i, S2i, ..., Sni}, with supply Pik=wmax, 1 ≤ k ≤ n−1, where n = Pi/wmax and n−1
k=0 Pki+ Pn
i = Pi. Thereafter, a new table is constructed for the transportation problem. Based on the optimal solution, if Sisupplies the sink Tjwith current f low, Fij> wmax. In the new extended table, Smi is randomly chosen to supply the flow wmax with the original cost. The other Ski, k = m, are set to Tjwith a large cost M→ ∞, and the remaining flow is distributed to those entries evenly. A large cost prevents Si from supplying currents to the sink Tjwith a large cost. Upon construction of the new table, the pivot procedure is used to obtain the optimal solution under the wire constraint. Figure 16 shows the results withwmax= 5.
Upon obtaining the optimal solution, separate sources that flow to the same sink are combined into one flow value, since they actually start at Si and reach the same target. Separating sources into several parts is the same as adding new constraints to the problem. The number of basic variables exceeds m + n− 1. Although a nontree topology may be obtained, electromigration is avoided if the solution is feasible. In certain cases, even with sufficient M, a flow under the huge cost still exists. This sit-uation implies that the solution is unfeasible, and is caused by an improper wire-size constraint. In other words, with the given wire-size constraint, avoiding electromigra-tion is impossible, and thus must be resolved. Figure 7(a) shows the result after using the transportation approach.
5. IR-DROP REDUCTION
Although the optimal CDEARST of the power net and ground net are constructed sep-arately, the wires may overlap. To handle this problem, this study performed detailed routing and IR-drop reduction, as shown in the following sections.
Without changing the solution quality, wires are bundled to free routing space to enhance the routability and relax congestion. After performing the wire-bundling pro-cedure, this article adopts the negotiation-based routing technique for detailed routing. Finally, the wire-width extension method is adopted to decrease the wire resistance for IR-drop reduction. The detailed algorithm is discussed in the following section.
Fig. 17. An example of L-shape bundling.
Fig. 18. MinCost-L-RST (x(v)).
5.1 Wire Bundling
After constructing the power nets and ground nets, the nets of the same type are bun-dled when possible. Figure 17 shows an example of the wire-bundling procedure. This study maximizes the overlaps via a dynamic programming approach, which is pro-posed in the study by Ho et al. [1990]. Bundling segments do not affect the total wire area, though they can alleviate the congestion. Furthermore, the bundling approach is beneficial for reducing IR-drop, since it can free additional space to extend the wire width. Figure 7(b) shows the results after using the wire-bundling approach.
The dynamic programming method used by Ho et al. [1990] is shown below. The input tree is rooted at any point r, resulting in the rooted tree Tr. For a point set S, and a point v ∈ S, the subtree is denoted (i.e., star), which is induced by v and its neighbors as TS
v. The edge incident is also denoted from its parent on v as ev and T+
v = TvS∪ ev. The procedure of MinCost-L-RST computes the minimum cost L-RST x(v), where x is either the upper L-shape u or the lower L-shape l. If there is no enough routing space for wire width, the wire bundle failed, and set the high cost for u(wi) andl(wi). d is the number of children of the pointv in the rooted tree Tr. The procedure is shown in Figure 18.
5.2 Detailed Routing
If no overlapping is present between any power net and ground net, the feasible so-lution is obtained; otherwise, the congestion is analyzed. This study adopted the negotiation-based routing technique, which was introduced in PathFinder [McMurchie and Ebeling 1995]. The history-based cost function for estimating the cost of an edge r is defined as follows:
where bris the base cost of using the edge r and is set to its current flow (i.i., one unit of wire area), and hr× pris the congestion cost of an edge r. The historical term hris updated in the following manner during iterations:
hi+1r =
hi
r+ 1 if r has overflow
hir otherwise (18)
where i is the iteration count and h1
g= 1. The penalty term pris defined as follows: pr= (
d(r) + 1 s(r) )
k, (19)
where s(r) is the supply of an edge r and represents the number of available routing tracks; d(r) is the demand on the edge and the number of wires that utilize an edge r; and k is a constant that controls the rising rate of pr.
In the highly congested region, since the detoured net with small current flow may slightly increase the wire area, rip-up and reroute segments with low current flow are conducted. The ripped-up net is first rerouted by adopting the monotonic routing ap-proach [Pan and Chu 2006]. This study performs the reroute procedure within the bounding box without any detour. This method would not increase the total wire area. If the monotonic routing method fails to find an overflow-free path, the detour con-straint is released to compose the reroute procedure for detouring the segment within the bonding box. However, if the procedure still fails, the segment reroute is composed without a bounding box constraint. This study continues using the same congested region procedure to each of the remaining nets, and rips-up and reroutes the marked nets.
5.3 Wire Sizing
This step involves analyzing the IR-drop for each route from the power pad to any power sink by using Eq. (4). The current I is distributed by performing the trans-portation approach, and the cross-sectional area Awireis proportional to the current. The electrical resistivity of the materialρ is provided in the input. Upon obtaining the routing solution, the total wire length Lwirecan be estimated with ease. By using Eq. (4), the IR-drop for each net is obtained. This study compares the IR-drop value with the tolerant voltage drop Vdropof each module. If the IR-drop value exceeds Vdrop,
Table III. Comparison of the Proposed Algorithm and Three High-Tech Algorithms
the wire width can be expanded to increase Awire, to reduce the total IR-drop value. The wire width is extended until the IR-drop value is smaller than the Vdrop. When we use the wire-sizing method for reducing the IR-drop, we check whether there is enough routing resource for the wire-width expansion or not. If there are some ob-stacles blocking the wire sizing, we first try to separate the wire from the source into two or more nets as we mentioned in Section 4.3.3 and Figure 16. Then, we route all the separated nets on the region and avoid the blocked obstacles. However, if there is not enough routing space for the separated nets, for the IR-drop safety, we rip-up and reroute the original net (i.e., the net without separation). Then, the negotiation-based routing would obtain another routing solution. In certain cases, even when we adopt rip-up and reroute the method, we still cannot obtain an IR-drop safety routing solution. That means, with the given infeasible IR-drop threshold, avoiding IR-drop is impossible, and the chip must be redesigned. Figure 7(c) shows the routing results.
5.4 Complexity
Table II shows the comparison between the proposed algorithm and three high-tech algorithms. The algorithm proposed by Lienig and Jerke [2003] is with the lowest complexity. However, the algorithm may fail to route or obtain a huge wire-area so-lution. The algorithm by Yan and Chen [2008] can route all benchmarks, although the complexity is the greatest, and the runtime is extremely large. The algorithm by Jiang et al. [2010] can solve the wiring topology optimally. Thus, this study compares the proposed algorithm with that of Jiang et al. [2010]. Although the proposed algo-rithm derives the superior initial solution with a slightly higher complexity than that
of Jiang et al. [2010], the algorithm can reduce the iterations significantly in the fol-lowing step for finding the optimal solution. The experimental results show that the proposed algorithm is more efficient than that of Jiang et al. [2010], and obtains the same optimal solution.
6. EXPERIMENTAL RESULTS
The proposed algorithm was implemented in the C++ programming language. For a fair comparison, this study compares the results in two different platforms. Tables III, IV, and V are compared on a PC with an IntelCoreT Mi7 CPU 920 of 2.67GHz fre-quency and 4GB memory under Windows 7 Enterprise 32 bit. Table VI runs on a 2.0 GHz Intel Xeon workstation with 16GB memory. The operating system used was Linux, and the compiler was gcc (Version 4.3.3). The algorithms by Lienig and Jerke [2003], Yan and Chen [2008], and Jiang et al. [2010] were implemented on the same platform for a fair comparison.
Table III compares the proposed algorithm of CDEARST with three high-tech algo-rithms. Fourteen benchmarks are present from the study by Jiang et al. [2010]. The first benchmark (INP1) is shown in Figure 3. Russell’s approximation method and the pivot procedure were implemented. Lienig and Jerke [2003] may generate unfeasi-ble solutions, especially for large benchmarks. Because the optimal edges are chosen greedily in the triangular mesh graph and the terminals that have been considered are deleted, isolated terminals may be produced. The method used by Yan and Chen [2008] does not consider the competition of all sources, and hence the solution quality is limited. Jiang et al. [2010] proposed a method to obtain optimal solutions. How-ever, they adopted a greedy heuristic to obtain the initial solution. Therefore, it may consume a large number of iterations in the step for finding the optimal solution.
Table V. Results of the proposed Obstacle-Avoiding Routing Algorithm
Table IV compares the proposed algorithm of CDEARST with that of Jiang et al. [2010]. The number of iterations (pivots) is usually proportional to the number of ter-minals (sources and sinks). Russell’s algorithm is the method for finding the initial so-lution that approximates to the optimal soso-lution. The algorithm should obtain a more accurate initial solution that is close to the optimal solution, while fewer terminals are processed. In other words, in certain circuits with fewer terminals, the optimal solution can be obtained when only adapting Russell’s method. Furthermore, refining the initial solution that is iteratively obtained via Russell’s method is unnecessary to obtain an optimal solution, which is the reason why 0 pivots exist in certain circuits, as shown in Table IV and Table V. Hence, in small benchmarks, Russell’s method can obtain the optimal solution without any pivots. For the large benchmarks, the method provides good-quality BF solutions before the solution is pivoted into an optimal so-lution. The results show that Russell’s method obtains superior initial solutions to reduce the iteration (pivot) times. Furthermore, all the procedures were calculated in a two-dimensional array, which is efficient and effective. The results show that the
Fig. 19. RC11 output. Obstacles are shown in blue. Wire area = 1568429; runtime = 80.104 sec; number of pivot = 1374; total transportation runtime = 1.338 sec.
proposed algorithm can also obtain optimal solution, although with fewer than 11 CPU times.
Table V shows the obstacle-avoiding routing results. The 23 benchmarks with m + n terminals that range from 7 to 1000 were used. Five industrial benchmark (IND1 to IND5) from Synopsys; 12 benchmarks (RC1 to RC12); and 5 random test cases (RT01 to RT05) were present [Lin et al. 2008]. Since these benchmarks do not have current information, this study randomly assigned either a positive or negative current value to each terminal. The total sum of the current values must follow Kirchhoff ’s current conservation law. Even under the RMS model, when the total current sum is not equal to zero, the proposed algorithm is still effective. In both situations, the proposed algorithm guarantees an optimal solution.
Figure 19 shows the large benchmark result (RC11), which contains 1000 terminals and 100 obstacles. The total wire area is 1568429.
Table VI shows the P/G routing results in analog ICs. Five benchmarks with ran-domly distributed modules are present. The power pads and ground pads are situated on the boundary of the chip. The tolerant voltage drop and the required current of each module are fixed, and two layers are used for routing. In practical analog IC de-signs, area routing is often adopted, which signifies that each routing layer can assign horizontal routing and vertical routing wires. The proposed router adopts area routing and renders the routing result in a single layer as much as possible. Maximum current density quantifies the result after addressing EM. The lower current density identifies the better prevention of EM. Without addressing the EM, due to the high current den-sity, it leads to the influence of MTT F, and creates the permanent failure of the chip by EM. The initial wire area after using the transportation approach is shown in the row labelled, CDEARST. The final total wire area using the proposed router is shown in the row labeled, Routing. The increased wire area is caused by net rerouting and IR-drop reduction. Net rerouting prevents power nets and ground nets from overlap-ping; IR-drop reduction maintains sufficient voltage for each module. The ratio of free routing space is used to estimate the routing congestion. The wire-bundling procedure obtains additional free routing space, and is conducive to detail routing and IR-drop reduction. Finally, Eq. (4) is used to calculate the total voltage drop. Assigning the Awirein direct proportion to I equalizes the initial voltage drop to the total wire length (Lwire). After detailed routing, the voltage drop of each module is estimated before
ex-Table VI. Results of the Proposed Analog P/G Routing Algorithm
panding the wire width for unfeasible module routes. Figure 7(c) shows the routing results of the benchmark RPG2.
7. CONCLUSION
This study proposed an automatic analog P/G router that manages the electromigra-tion and IR-drop. By using the transportaelectromigra-tion approach, this article solved the current-driven electromigration-aware rectilinear Steiner tree (CDEARST) problem efficiently and optimally. To handle IR-drop, this study first bundled the wire to free more routable areas and alleviate congestion. Thereafter, a wire width extension method was adopted to further reduce IR-drop. The experimental results show the effective-ness and efficiency of the proposed algorithm.
REFERENCES
BLACK, J. 1969. Electromigration - A brief survey and some recent results. IEEE Trans. Electron Devices
16, 4, 338–347.
CORMEN, T. H., LEISERSON, C. E., RIVEST, R. L.,ANDSTEIN, C. 2009. Introduction to Algorithms 3rd Ed., MIT Press.
DUTTA, R.ANDMAREK-SADOWSKA, M. 1989. Automatic sizing of power/ground (p/g) networks in VLSI. In
Proceedings of the IEEE/ACM Design Automation Conference (DAC’89). ACM, New York, 783–786.
HO, J.-M., VIJAYAN, G.,ANDWONG, C. K. 1990. New algorithms for the rectilinear steiner tree problem.
IEEE Trans. Comput.-Aid. Des. Integrat. Circuits Syst. 9, 2, 185–193.
JIANG, I. H.-R., CHANG, H.-Y.,AND CHANG, C.-L. 2010. Optimal wiring topology for electromigration-avoidance considering multiple layers and obstacles. In Proceedings of the International Symposium on
Physical Design (ISPD’10). ACM, New York, 177–184.
LIENIG, J. 2006. Introduction to electromigration-aware physical design. In Proceedings of the International
Symposium on Physical Design (ISPD’06). ACM, New York, 39–46.
LIENIG, J.AND JERKE, G. 2003. Current-driven wire planning for electromigration avoidance in analog circuits. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’03). ACM, New York, 783–788.
portation problem. Oper. Res. 17, 1, 187–191.
SILVA, J. M. S., PHILLIPS, J. R.,ANDSILVEIRA, L. M. 2008. Efficient representation and analysis of power grids. In Proceedings of the Conference on Design, Automation, and Test in Europe (DATE’08). ACM, New York, 420–425
TODRI, A., MAREK-SADOWSKA, M.,ANDCHANG, S.-C. 2007. Analysis and optimization of power-gated ICS with multiple power gating configurations. In Proceedings of the IEEE International Conference on
Computer-Aided Design (ICCAD’07). IEEE, Los Alamitos, CA, 783–790.
WINSTON, W. L. 2004. Operations Research Applications and Algorithms 4th Ed., Thomsom Brooks/Cole. YAN, J.-T.ANDCHEN, Z.-W. 2008. Electromigration-aware rectilinear Steiner tree construction for analog
circuits. In Proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS’08). IEEE, Los Alamitos, CA, 1692–1695.
