The proposed algorithm was implemented in the C++ programming language. For a fair comparison, this study compares the results in two different platforms. Tables III, IV, and V are compared on a PC with an IntelCoreT Mi7 CPU 920 of 2.67GHz fre-quency and 4GB memory under Windows 7 Enterprise 32 bit. Table VI runs on a 2.0 GHz Intel Xeon workstation with 16GB memory. The operating system used was Linux, and the compiler was gcc (Version 4.3.3). The algorithms by Lienig and Jerke [2003], Yan and Chen [2008], and Jiang et al. [2010] were implemented on the same platform for a fair comparison.
Table III compares the proposed algorithm of CDEARST with three high-tech algo-rithms. Fourteen benchmarks are present from the study by Jiang et al. [2010]. The first benchmark (INP1) is shown in Figure 3. Russell’s approximation method and the pivot procedure were implemented. Lienig and Jerke [2003] may generate unfeasi-ble solutions, especially for large benchmarks. Because the optimal edges are chosen greedily in the triangular mesh graph and the terminals that have been considered are deleted, isolated terminals may be produced. The method used by Yan and Chen [2008] does not consider the competition of all sources, and hence the solution quality is limited. Jiang et al. [2010] proposed a method to obtain optimal solutions. How-ever, they adopted a greedy heuristic to obtain the initial solution. Therefore, it may consume a large number of iterations in the step for finding the optimal solution.
Table V. Results of the proposed Obstacle-Avoiding Routing Algorithm
Table IV compares the proposed algorithm of CDEARST with that of Jiang et al.
[2010]. The number of iterations (pivots) is usually proportional to the number of ter-minals (sources and sinks). Russell’s algorithm is the method for finding the initial so-lution that approximates to the optimal soso-lution. The algorithm should obtain a more accurate initial solution that is close to the optimal solution, while fewer terminals are processed. In other words, in certain circuits with fewer terminals, the optimal solution can be obtained when only adapting Russell’s method. Furthermore, refining the initial solution that is iteratively obtained via Russell’s method is unnecessary to obtain an optimal solution, which is the reason why 0 pivots exist in certain circuits, as shown in Table IV and Table V. Hence, in small benchmarks, Russell’s method can obtain the optimal solution without any pivots. For the large benchmarks, the method provides good-quality BF solutions before the solution is pivoted into an optimal so-lution. The results show that Russell’s method obtains superior initial solutions to reduce the iteration (pivot) times. Furthermore, all the procedures were calculated in a two-dimensional array, which is efficient and effective. The results show that the
Fig. 19. RC11 output. Obstacles are shown in blue. Wire area = 1568429; runtime = 80.104 sec; number of pivot = 1374; total transportation runtime = 1.338 sec.
proposed algorithm can also obtain optimal solution, although with fewer than 11 CPU times.
Table V shows the obstacle-avoiding routing results. The 23 benchmarks with m + n terminals that range from 7 to 1000 were used. Five industrial benchmark (IND1 to IND5) from Synopsys; 12 benchmarks (RC1 to RC12); and 5 random test cases (RT01 to RT05) were present [Lin et al. 2008]. Since these benchmarks do not have current information, this study randomly assigned either a positive or negative current value to each terminal. The total sum of the current values must follow Kirchhoff ’s current conservation law. Even under the RMS model, when the total current sum is not equal to zero, the proposed algorithm is still effective. In both situations, the proposed algorithm guarantees an optimal solution.
Figure 19 shows the large benchmark result (RC11), which contains 1000 terminals and 100 obstacles. The total wire area is 1568429.
Table VI shows the P/G routing results in analog ICs. Five benchmarks with ran-domly distributed modules are present. The power pads and ground pads are situated on the boundary of the chip. The tolerant voltage drop and the required current of each module are fixed, and two layers are used for routing. In practical analog IC de-signs, area routing is often adopted, which signifies that each routing layer can assign horizontal routing and vertical routing wires. The proposed router adopts area routing and renders the routing result in a single layer as much as possible. Maximum current density quantifies the result after addressing EM. The lower current density identifies the better prevention of EM. Without addressing the EM, due to the high current den-sity, it leads to the influence of MTT F, and creates the permanent failure of the chip by EM. The initial wire area after using the transportation approach is shown in the row labelled, CDEARST. The final total wire area using the proposed router is shown in the row labeled, Routing. The increased wire area is caused by net rerouting and IR-drop reduction. Net rerouting prevents power nets and ground nets from overlap-ping; IR-drop reduction maintains sufficient voltage for each module. The ratio of free routing space is used to estimate the routing congestion. The wire-bundling procedure obtains additional free routing space, and is conducive to detail routing and IR-drop reduction. Finally, Eq. (4) is used to calculate the total voltage drop. Assigning the Awirein direct proportion to I equalizes the initial voltage drop to the total wire length (Lwire). After detailed routing, the voltage drop of each module is estimated before
ex-Table VI. Results of the Proposed Analog P/G Routing Algorithm
panding the wire width for unfeasible module routes. Figure 7(c) shows the routing results of the benchmark RPG2.
7. CONCLUSION
This study proposed an automatic analog P/G router that manages the electromigra-tion and IR-drop. By using the transportaelectromigra-tion approach, this article solved the current-driven electromigration-aware rectilinear Steiner tree (CDEARST) problem efficiently and optimally. To handle IR-drop, this study first bundled the wire to free more routable areas and alleviate congestion. Thereafter, a wire width extension method was adopted to further reduce IR-drop. The experimental results show the effective-ness and efficiency of the proposed algorithm.
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Received January 2011; revised July 2011; accepted August 2011