Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory

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Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in

Nonvolatile Memory

View the table of contents for this issue, or go to the journal homepage for more 2010 Jpn. J. Appl. Phys. 49 086202

(http://iopscience.iop.org/1347-4065/49/8R/086202)

Effect of Nitrogen Plasma Treatment on Electrical Characteristics

for Pd Nanocrystals in Nonvolatile Memory

Tsung-Kuei Kang, Ta-Chuan Liao1_{, Cheng-Li Lin, and Wen-Fa Wu}2

Department of Electronic Engineering, Feng-Chia University, Taichung, Taiwan 40724, R.O.C.

1_{Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 30010, R.O.C.} 2_{National Nano Device Laboratories, Hsinchu, Taiwan 30078, R.O.C.}

Received January 19, 2010; accepted May 24, 2010; published online August 20, 2010

Pd nanocrystals (NCs) are successfully embedded in a TaN/SiO2/HfAlO/Si structure. The initial memory window increases at a higher rate with increasing fabrication temperature of Pd NCs compared with the linear variation of Pd NC density, which is related to the thermally induced neutral traps in the HfAlO film around Pd NCs. After manufacturing a TaN/SiO2/Pd NCs/HfAlO/Si/Al structure, the subsequent N2plasma treatment is conducted at 300_{C for 3 min. The number of leakage current paths in the SiO}

2 blocking layer adjacent to TaN is clearly reduced, but that of leakage current paths in SiO2/HfAlO around Pd NCs is slightly increased owing to the thermal stress. The thermally induced neutral traps in the HfAlO film around the Pd NCs can be passivated by nitrogen atoms, which leads to the improvement of the final memory window for the Pd NC samples fabricated at 600 – 700_{C. However, the intrinsic traps in the HfAlO film play an important role in memory characteristic and the final} memory window is reduced by thermal densification for the Pd NC samples fabricated at 500_C. #_{2010 The Japan Society of Applied Physics} DOI: 10.1143/JJAP.49.086202

1. Introduction

To improve the performance of nanocrystals embedded in a nonvolatile memory (NVM), the use of metal nanocrystal (NC) structures was suggested to prolong the data retention time.1–5) _{Apparent improvement in the programming speed}

and data retention in a nanocrystal nonvolatile memory was also observed when a high-k material was used instead of the conventional SiO2.6–9) Therefore, a combined struc-ture of a metal nanocrystal and a high-k tunneling layer is expected to show better data retention characteristics. For metal-nanocrystal-embedded SiO2, some annealing processes can induce defects or traps in the SiO2 film around metal nanocrystals. The induced deficiency in the surrounding SiO2 results in stored charges leaking out of the nanocrystals through trap-assisted tunneling.10–12)

There-fore, the quality of the surrounding dielectric including the blocking oxide and tunneling oxide is an important issue in metal nanocrystal memories. As is well known, a high-k material easily crystallizes at a high annealing temperature for the integration of metal NCs with a high-k material, thereby inducing leakage current paths.13) _{HfAlO is a}

promising candidate material for use in metal nanocrystal memories owing to its higher crystallization temperature than the HfO2 film.14)In addition, although they are widely used in Pd metal electrodes and are a promising metal NC candidate owing to their high work function of 5.1 eV, only a few Pd nanocrystals have been used for NVM.15)

As mentioned above, for the defects induced by the fabrication process, previous research studies have mainly focused on NVMs with a SiO2tunneling layer. In a previous study, the induction of defects during Mo nanocrystal formation in a tunneling oxide and the reduction in the density of defects were achieved by NH3 plasma treat-ment.12) _{In this study, the effect of N}

2 plasma treatment on electrical characteristics will be investigated for Pd nanocrystal nonvolatile memories with fabricated by differ-ent processes. Moreover, process-induced defects including the leakage current paths in dielectrics and intrinsic traps/thermally induced neutral traps in a HfAlO tunneling layer will be considered in explaining all electrical charac-teristics.

2. Experimental Procedure

A 5-nm-thick HfAlO film was grown on a p-type (100) substrate by the MOCVD method. The HfAlO film was deposited at 500
_{C by using a combination of} Hf-[OC(CH3)3]2[C5H11O2]2 and Al[PCH(CH3)2]3 precursors. The chemical compositional analysis of the as-prepared sample ðHf : Al : O ¼ 0:34 : 0:07 : 0:59 { 0:42 : 0:06 : 0:52Þ was conducted by auger electron spectrometer (AES) analy-sis, as shown in Fig. 1. Then, a thin Pd wetting layer (2 nm) was deposited by using an E-gun system (3  106Torr, 40 mA and 0.02 – 0.03 nm/s). After Pd deposition, some samples were annealed by rapid thermal annealing at tem-peratures ranging from 500 to 700
C for 30 s. Then, all annealed samples were followed by the deposition of a 25-nm-thick SiO2blocking oxide layer in a high density plasma CVD (HDPCVD) system. Photolithography processes were conducted, and TaN layers (50 nm) were deposited as the top electrodes by lift-off technology. Finally, Al bottom elec-trodes were deposited. After manufacturing a TaN/SiO2/Pd NCs/SiO2/Si/Al structure, partial Pd NC samples with different fabrication temperatures of Pd NCs were subjected to N2 plasma treatment (200 mTorr, 200 W, and 200 sccm)

Etch Time (s) 0 20 40 60 80 100 Atomic concentration (%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Si Hf O Al O Hf Al Si

Fig. 1. Chemical compositional analysis of the as-prepared HfAlO film by AES analysis.

with a wafer substrate at 300
_{C for 3 min. To investigate the} mechanism underlying the improvement in electrical char-acteristics, some samples were subjected to 300
_{C annealing} in N2 ambient for 3 min. The capacitance–voltage (C–V) measurements were performed using a precision LCR meter (HP 4284A). In addition, leakage current and charge retention measurements were performed using a HP4156A LCR meter. The charge retention measurement was per-formed using the C–t method.16)After programming/erasing at 8 V for 10 s, the capacitance was measured at a fixed voltage [ðVFB1þVFB2Þ=2] with varying retention time. From the variation of capacitance with retention time, the relative flat-band voltage can be deduced. Therefore, the variation of flat-band voltage in the program state and erase state can be plotted against retention time. To estimate the total number of stored electrons in the capacitor, C–V curves were also immediately measured by a voltage sweep with sufficiently fine steps after programming/erasing at 8 V for 10 s, respectively. Hereafter, this method is called the ‘‘sweeping method’’. The Pd nanocrystal shape and density were determined by transmission electron microscopy (TEM) analysis. To determine whether or not the nitrogen atoms diffuse into dielectrics, the determination of atom concen-tration was conducted by AES.

3. Results and Discussion

After Pd deposition on HfAlO/Si using an E-gun system, Pd nanocrystals can be distinctly observed in the as-deposited film, as shown in Fig. 2(a). This observation is similar to the growth of Au on SiO2,5) and the density of as-deposited Pd nanocrystals on the HfAlO film is 1:87  1012_/cm2_. According to the TEM figure, many Pd metal islands have not yet separated well into regularly shaped nanocrystals. The relaxation of the film stress in the deposited metal layer and the surface energy minimization drive the formation of new nanocrystals during the following annealing process.5) Therefore, the nanocrystal density and size vary linearly with increasing fabrication temperature of Pd nanocrystals, as shown in Fig. 2(b). For retention measurement, the C–t method is adopted.16)_{Although the C–t method can provide}

a correct retention characteristic, it has difficulty in obtaining the initial memory window owing to an inevitable delay after discharging. Therefore, to obtain the total number of stored charges after charging, the sweeping method with sufficiently fine voltage steps is adopted. For the sample without plasma, typical C–V curves with the voltage swept from 8 to 8 V and then back to 8 V were obtained, as shown in Fig. 3(a). This indicates an accelerating increase of the C–V loop for the sample annealed at 700
_{C. By the C–t} method, after programming/erasing, the initial memory window increases at a higher rate from 500 to 600 to 700
_C (6.8 to 8 to 11.6 V), compared with the linear variation of Pd NC density, as shown in Figs. 3(b) and 2(b), respectively. For the Pd NC samples fabricated at 600 – 700
_{C without} subsequent treatment, the leakage current densities are similar to each other (see Figs. 7 and 8). Therefore, in addition to the Pd NC density and leakage current paths, the induced neutral traps in the HfAlO film also play an important role in the initial memory window of the sample at a higher fabrication temperature of Pd NCs. In other words, a higher Pd NC fabrication temperature will induce more

neutral traps around Pd NCs, and this will affect the initial memory window. Al acts as a network modifier by breaking Al–O–Al bonds and producing nonbridging oxygen centers in a HfAlO film.17) It is considered that neutral traps originate from nonbridging oxygen centers and that more thermally induced neutral traps in HfAlO around Pd NCs are obtained with increasing annealing temperature. Some researchers reported that some intrinsic traps in Hf-based oxides can be obtained after deposition and that these intrinsic traps are used in NVM application.18,19) _{On the}

basis of previous mechanisms10–13,18,19) _{and the thermally}

induced neutral traps mentioned above, the schematic of a defect model is shown in Fig. 4. It is considered that the intrinsic traps in the HfAlO film, the leakage current paths in the SiO2 blocking film/HfAlO film, and the thermally induced neutral traps in the HfAlO film around Pd NCs affect the memory window and retention characteristics.

After manufacturing a TaN/SiO2/Pd NCs/HfAlO/Si/Al structure, some samples were subjected to N2 plasma treatment in the HDPCVD system at 300
_{C for 3 min. To} determine whether or not the nitrogen atoms diffuse into dielectrics, the analysis of atom concentration for the SiO2/ HfAlO/Si structure is conducted by AES analysis, and the results are plotted in Fig. 5(a). Compared with the observa-tion in the sample without N2 plasma treatment, more nitrogen atoms appear in the SiO2 blocking layer and at the

(a) (b)

As-deposited

Fig. 2. (a) TEM photograph of Pd nanocrystals in as-deposited sample. (b) Density of Pd NCs as a function of Pd NC fabrication temperature.

SiO2/HfAlO interface. Compared with the C–V loop in Fig. 3(a), a smaller C–V loop can be found for the sample subjected to N2 plasma treatment, as shown in Fig. 5(b). To investigate the detailed mechanism of memory character-istic, some samples were annealed at 300
_{C for 3 min in} N2 ambient after manufacturing the TaN/SiO2/Pd NCs/ HfAlO/Si/Al structure. Hereafter, this process is called the ‘‘R300’’ process. For different subsequent processes, the

initial memory window as a function of Pd NC fabrication temperature is shown in Fig. 6. According to the defect model in Fig. 4, many defects affect the initial memory window. To determine which factor dominates the initial memory window, the leakage current densities of all the Pd nanocrystal

P-Si TaN

SiO2

HfAlO

Neutral traps around Pd NCs

Leakage current paths Leakage current paths

Intrinsic traps

Fig. 4. Schematic of defect model for explaining the retention charac-teristics. Gate voltage (V) -10 -8 -6 -4 2 0 2 4 6 8 10 Normalized capacitance 0.0 0.2 0.4 0.6 0.8 1.0 500 °C (-8V-->+8V) 500 °C (+8V-->-8V) 600 °C (-8V-->+8V) 600 °C (+8V-->-8V) 700 °C (-8V-->8V) 700 °C (-8V-->+8V) (a) (b) Etch time (s) 0 200 400 600 800 1000 Counts 0 2000 4000 6000 8000 10000 12000 14000 16000

Sample with N2 plasma

Sample without N2 plasma

SiO₂/HfAlO/Si structure

SiO₂

Hf atom detected

Fig. 5. (a) Profile distribution of nitrogen concentration with sputtering time determined by AES technique. (b) Typical C–V curves with the voltage swept from 8 to 8 V and then back to 8 V for the samples with N2 plasma treatment.

Pd NC fabrication temperature (°C)

500 600 700

Initial memory window (V)

2 4 6 8 10 12 14

Control w/o subsequent treatment Samples with subsequent R300 process

Samples with subsequent N2 plasma

Fig. 6. Initial memory window as a function of Pd NC fabrication temperature for all samples with different subsequent processes.

Pd NC fabrication temperture (°C)

450 500 550 600 650 700 750

Initial memory window (V)

6 7 8 9 10 11 12 Faster increase Gate voltage (V) -10 -8 -6 -4 -2 0 2 4 6 8 10 Nomalized capacitance 0.0 0.2 0.4 0.6 0.8 1.0 500 °C (-8V-->+8V) 500 °C (+8V-->-8V) 600 °C (-8V-->+8V) 600 °C (+8V-->-8V) 700 °C (-8V-->+8V) 700 °C (+8V-->-8V) (a) (b)

Fig. 3. (a) Typical C–V curves with the voltage swept from 8 to 8 V and then back to 8 V for the samples without subsequent treatment. (b) Initial memory window as a function of Pd NC fabrication temperature for the samples without subsequent treatment.

samples at 8 V are measured and shown in Figs. 7 and 8, respectively. It is found that the subsequent 300
_{C annealing} in N2 ambient creates additional leakage current paths in dielectrics and leads to higher leakage current densities. However, the nitrogen atoms can passivate leakage current paths in dielectrics, thereby leading to lower leakage current densities for the samples with subsequent N2 plasma treatment. Compared with that observation in the samples without subsequent treatment, further nitrogen diffusion near the metal TaN/SiO2 interface results in lower leakage current densities at 8 V due to gate injection, but slightly higher leakage current densities are found at +8 V due to the thermal stress in dielectrics around the Pd NCs for the samples with subsequent N2 plasma treatment. Similarly to the samples without subsequent treatment, the other samples show small variations of leakage current densities with different Pd NC fabrication temperatures. Although the leakage currents of the samples subjected to the R300 process are always higher than those of the control samples, the initial memory windows are similar to each other at the same Pd fabrication temperature. Therefore, it is considered that the Pd NC density, the intrinsic traps in the HfAlO film, and the induced neutral traps in the HfAlO film around the

Pd NCs dominantly determine the initial memory window. Owing to nitrogen diffusion, the number of thermally induced neutral traps in the HfAlO film around the Pd NCs is reduced and lower initial memory windows are observed for the samples with subsequent N2 plasma treatment. For the 500
_{C annealed sample with N}

2 plasma treatment, more nitrogen atoms can diffuse into the traps beneath Pd NCs owing to the fewer thermally induced neutral traps in the HfAlO film around the Pd NCs. Therefore, a larger reduction in the number of the neutral traps beneath Pd NCs results in a clearer variation of VFB during charging.

Figure 9 shows the final memory window after discharg-ing for 1800 s as a function of different Pd NC fabrication temperature. In contrast to the initial memory window, the final memory window decreases with increasing Pd NC fabrication temperature. Previous research indicates that the trap-assisted tunneling in SiO2dominates charge loss due to thermal stress in the SiO2 film.9,10) The leakage current through Hf-based dielectrics dominated by trap-assisted tunneling has been reported.17) _{In this work, the leakage}

current density of a TaN/25 nm SiO2/Pd NCs/5 nm HfAlO/ Si structure is much lower than that of a TaN/Pd NCs/5 nm HfAlO/Si by at least 7 orders of magnitude. It is considered that the charging and discharging mainly occur between Pd nanocrystals and the Si substrate through the HfAlO tunneling layer for all the annealed samples. The leakage current densities of the TaN/Pd NCs/HfAlO/Si structures with different Pd NC fabrication temperatures at 8 V are shown in Fig. 10. Results indicate that the leakage current densities for different Pd NC fabrication temperatures are similar to each other for the samples subjected to N2plasma treatment and the R300 process, but the final memory window for the samples with N2plasma treatment is always larger than that for the samples with the R300 process. Therefore, the Pd NC density, the intrinsic traps in the HfAlO film, and the thermally induced neutral traps in the HfAlO film around the Pd NCs dominantly determine the variation of the final memory window at different Pd NC fabrication temperatures. After N2plasma treatment, a clear improvement of the final memory window due to the reduction in the number of thermally induced neutral traps

Pd NC fabrication temperature(°C)

450 500 550 600 650 700 750

Leakage current density (A/cm

2) 1e-8 1e-7 1e-6 1e-5 1e-4

Samples w/o subsequent treatment Samples with subsequent R300 process

Samples with subsequent N2 plasma

Vg = +8 V

TaN/SiO2/Pd NCs/HfAlO/Si structure

Fig. 7. Leakage current densities under +8 V gate bias for the samples with three different subsequent processes.

Pd NC fabrication temperature (°C)

450 500 550 600 650 700 750

Leakage current density (A/cm

2) 1e-9 1e-8 1e-7 1e-6 1e-5

Samples w/o subsequent treatment Samples with subsequent R300 process

Samples with subsequent N2 plasma

Vg = -8 V

TaN/SiO₂/Pd NCs/HfAlO/Si structure

Fig. 8. Leakage current densities under 8 V gate bias for the samples with three different subsequent processes.

Pd NC fabrication temperature (°C)

450 500 550 600 650 700 750

Final memory window (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Samples w/o subsequent treatment

Samples with subsequent N2 plasma

Samples with subsequent R300 process

Obvious improvement

Fig. 9. Final memory windows for the samples with three different subsequent processes.

by nitrogen passivation for the samples fabricated at 600 – 700
C can be observed. During charging, most charges are captured in the thermally induced neutral traps instead of in Pd NCs for the samples fabricated at 700
C, and the charges are easily released from these traps. For the samples with subsequent N2 plasma treatment, a large reduction in the number of neutral traps is observed and more charges are stored in the Pd NCs. This results in the improvement of the final memory window. However, the improvement of the final memory window is limited because of the lack of nitrogen passivation for the samples with the subsequent R300 process. Compared with the samples annealed at 600 – 700
_{C, the samples fabricated at 500
C have fewer} thermally induced neutral traps that are due to the lower thermal stress from Pd NCs. According to Fig. 10, the number of leakage current paths is reduced after the N2 plasma process or 300
_{C annealing. It is also considered that} the number of intrinsic traps in the HfAlO film can be reduced by thermal densification. Moreover, the intrinsic traps in the HfAlO film dominate the variation of flat-band voltage for the samples annealed at 500
_{C. Therefore, the} final memory window of the sample without subsequent treatment is larger than that for the samples subjected to N2 plasma treatment and the R300 process for the samples fabricated at 500
_{C, Experimental results indicate that N}

2 plasma treatment can effectively passivate the thermally induced neutral traps resulting from the thermal stress during Pd NC formation, which leads to a better retention characteristic of the samples with higher fabrication temper-atures of Pd NCs (600 – 700
_C).

4. Conclusions

Pd nanocrystals can be successfully embedded in a TaN/ SiO2/HfAlO/Si structure. For the 600 – 700
C-fabricated

samples, the thermally induced neutral traps in the HfAlO film around Pd NC play an important role in determining the memory window. Moreover, N2 plasma treatment can effectively reduce the number of thermally induced neutral traps resulting from the thermal stress during Pd NC formation and achieve a better retention characteristic. For the Pd NC samples fabricated at 500
C, the intrinsic traps play an important role in memory characteristic and the final memory window is reduced by thermal densification. Acknowledgments

The authors would like to thank all staff members of NDL for their valuable technical support and discussion. This work was supported by Alchip Company under contract No. 9621071A, the National Nano Device Laboratories, R.O.C., under contract No. NDL 98-C05M2G-023, and the National Science Council under contract No. NSC-98-2218-E-009-010.

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Pd NC fabrication temperature (°C)

450 500 550 600 650 700 750

Leakage current density (A/cm

2) 1e-5 1e-4 1e-3 1e-2 1e-1 1e+0 1e+1 1e+2 1e+3

Samples w/o subsequent treatment

Samples with subsequent N2 plasma

Samples with subsequent R300 process

Vg = -8 V

TaN/Pd NCs/HfAlO/Si structure

Fig. 10. Leakage current densities under 8 V gate bias for the TaN/ Pd NCs/HfAlO/Si structure with three different subsequent processes.