Characterization and Modeling of On-Chip
Spiral Inductors for Si RFICs
Chuan-Jane Chao, Member, IEEE, Shyh-Chyi Wong, Member, IEEE, Chi-Hung Kao,
Ming-Jer Chen, Senior Member, IEEE, Len-Yi Leu, and Kuang-Yi Chiu
Abstract—The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.
Index Terms—Equivalent lumped circuit, inductors, modeling, skin effect.
I. INTRODUCTION
T
HE SURGING demand of silicon-based radio frequency integrated circuits (RFICs) has raised tremendous interest in on-chip passive components. The on-chip spiral inductor is one of the key elements in monolithic RFIC designs such as amplifiers, mixers, filters, and oscillators [1]–[3]. Some essen-tial features for integrated inductors include scalability in layout design, high quality factor, high self-resonant frequency ( ), large inductance range with small inductor size, and good RF models.Scalability of inductance values is important for optimized layout design. A methodology for scaling the inductance versus layout parameters is needed, with layout parameters including number of turns, coil width and spacing, and guard ring place-ment. There are also composite rules, which include parallel combination and series combination to maximize scaling range. A high quality factor is critical. The quality factor is impor-tant in that it is an index of contained electromagnetic energies (versus dissipated energy), provided to filters [2], [3] and to os-cillators at tuned frequency [2], and an index of the impedance matching efficiency in front-end amplifiers [1], [2]. The quality factor can be degraded by parasitic resistance [4], [5] from lines and substrate, as well as reduced self-resonant frequency. The self-resonant frequency is the upper bound for an inductor to
Manuscript received May 30, 2000. This work was performed while S.-C. Wong and C.-H. Kao were with Winbond Electronics Corp., Hsinchu, Taiwan, R.O.C.
C.-J. Chao and M.-J. Chen are with the Institute of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan 300, R.O.C. (e-mail: ccchao1@winbond.com.tw; mjchen@rpl.ee.nctu.edu.tw).
S.-C. Wong and C.-H. Kao are with the Ali Labs Inc., Taipei, Taiwan, R.O.C. (e-mail: scwong_home@yahoo.com; austin_kao@ali.com.tw).
L.-Y. Leu and K.-Y. Chiu are with Winbond Electronics Corp., Hsinchu, Taiwan, R.O.C. (e-mail: lylu@winbond.com.tw; kychiu@winbond.com.tw).
Publisher Item Identifier S 0894-6507(02)01037-0.
be functional, determined by the parasitic capacitance resulting from the substrate and between coils. Both the quality factor and self-resonant frequency are major elements determining the al-lowed inductance range. As both parasitic resistance and capaci-tance can degrade inductor performance, developing methods of minimizing their induced loss is important in RFIC technology. The design of an on-chip inductor requires simultaneous opti-mization of scaling, quality factor, and self-resonant frequency, while still having a small silicon area for the sake of chip size.
In addition to inductance characteristic optimization, high-frequency models are also important for circuit design. RF models based on lumped equivalent-circuit [5]–[7] have successfully been developed [2]. A major shortcoming of these lumped models is that they cannot model high frequency characteristics very well because of the impacts of inherent connection wires’ inductance and substrate capacitance [2], [5]–[7]. These works also ignored the frequency dependence of metal lines or substrate resistance at high frequencies due to skin effect [18]. In the works of Yoon [8] and Burghzrtz [9], a frequency-dependent resistance element was used to describe the resistance change due to the skin effect in the coil conductor and in the substrate. Nevertheless, the parameters for this resistance are hard to be determined or implemented into circuit simulators [10]–[12].
In this paper, we present a complete set of characterization of on-chip inductors in a BiCMOS process with two-level metal layers. Our works include the following: a) Give complete char-acterization and scaling rules of various inductor schemes with their dependencies of inductance and quality factor on geom-etry parameters. The parameters include inner opening diam-eter, number of turns, and coil conductor width and conductor interturn spacing, substrate contact guard ring distance, and par-allel and series inductors. b) To raise the quality factors of in-tegrated inductors by reducing substrate loss, a novel inductor configuration with a floating well underlaying is presented. It will be shown that this configuration can significantly improve the quality factor without reduction and without extra area-consumption. c) For accurate circuit simulation, a novel model is developed to model the substrate skin effect and eddy current effect and associated frequency-dependent resistance and induc-tance. The new model adopts a parallel combination of a resistor and an inductor on the signal-through path. The lumped-circuit approach is easy for parameters extraction and for SPICE im-plementation. This set of inductors can be easily implemented by generic CMOS or BiCMOS processes without extra implant or masking steps, which is important for low cost silicon sys-tems [9].
Fig. 1. Top view of a planar spiral inductor.
This paper is organized as follows: In Section II, the com-plete study of spiral inductor design and scaling is presented, where the characteristics of inductance, quality factor, self-res-onant frequency ( ), and frequency at max are discussed. In Section III, the performance and noise improvement using the floating well are discussed and a detailed study of substrate iso-lation in P-well, N-epitaxial layer, and floating N-well are also presented. In Section IV, a novel inductor model with substrate skin effect and eddy current effect is given. Section V concludes the paper.
II. SPIRALINDUCTORDESIGN ANDSCALINGEFFECT A. Experimental Setup
A 0.6- m double-layer metal BiCMOS technology is used to fabricate the on-chip spiral inductors. The N-type epilayer resistivity is 0.5 ohm cm, the substrate resistivity is 10 ohm cm, the thickness of Metal-1 and Metal-2 are about 0.7 and 1 m, respectively, and the oxide thickness between Metal-2 and the substrate is 2 m. A typical layout representation of a planar spiral inductor is shown in Fig. 1. The inductor is a three-turn Metal-2 square inductor. Metal-1 terminal is defined as port 1 and Metal-2 terminal is defined as port 2.
The configurations of the inductor include a variety of num-bers of turns ( ), inner opening diameters ( ), coil conductor widths ( ), conductor interturn spaces ( ), substrate contact guard ring distances ( ), parallel-inductors, and series induc-tors. The substrate contact guard ring is used as a grounded wall shorted to the substrate in order to prevent the noise coupling in RFIC.
Scattering parameters are measured using on-wafer two-port G-S-G RF probes and an HP8510C Network Analyzer. Pad par-asitic is de-embedded by subtracting out open pattern’s -pa-rameters. The measured frequency range is from 100 MHz to 20 GHz. The inductance ( ) and quality factor ( ) are extracted from the de-embedded -parameters using
Inductance imag (1)
Quality Factor imag (2)
(a)
(b)
Fig. 2. (a) Normalized inductances at 900 MHz for various inductor configurations withL = 5:5 nH. (b) Normalized inductances at 900 MHz only for inductors in parallel and in series. The hollow circles show calculated trends of 1/1, 1/2, 1/3, and 1, 12 2, 1 2 3, respectively. The rms error between the trend and measured inductance is 6.1%.
B. Inductor Design and Characterization
1) Inductance: The normalized inductances at 900 MHz for various inductor configurations are shown in Fig. 2(a). Here, is the inductance of a single inductor configuration, with
, m, m, m, and
m. is 5.5 nH at 900 MHz. Fig. 2 shows the inductance dependence on the number of turns ( , 3, 4, 6, 8), inner opening diameter ( m, 89 m, 114 m, 164 m), coil conductor width ( m, 10 m, 13 m, 15 m), conductor interturn space ( m, 4 m, 6 m), substrate contact guard ring distance ( m, 10 m, 20 m, 30 m, 200 m), the number in parallel (single, two in parallel, three in parallel), and the number in series (single, two in series, three in series). In-ductance can be raised by the increase of , , or and the decrease of or . Inductance has a strong dependence on the number of turns ( ) and inner opening diameter ( ). The in-crease with can be attributed to the increased coil-to-ground capacitance and so-induced reduction of frequency at Qmax. The increase with behaved as expected, as a result of higher substrate parasitic resistance with larger [13]. These results are useful for the optimization of inductance. On the right-hand side of Fig. 2(a), the inductances are shown to be proportional to the number of inductors in series and inversely proportional to the number of inductors in parallel. The proportionality is
Fig. 3. Measured inductance at 100 MHz (solid squares) with number of turns (N). The solid line is the regression trend line.
Fig. 4. Measured inductance at 100 MHz (squares) with inner diameters (A). The solid line is the linear trend line.
demonstrated by comparing the trend line (trend line calculated by addition or reciprocal addition) with the measured data as shown in Fig. 2(b), giving a root mean square error of 6.1% be-tween measured data and trend line. This allows for designing an inductor using a multiple of available inductors and also al-lows for constructing a complete inductance library based on a simplified inductor database.
Fig. 3 shows measured inductance at 100 MHz versus the number of turns and an extracted trend line. The equation of trend-line exhibits that inductance of a square spiral inductor is proportional to , note that the exponent 1.76 is close to 5/3 as suggested by the empirical formula for printed board circuits [14]–[16]. This empirical formula in [14] showed that induc-tance is proportional to the square root of total area of inductor, implying that the inductance of a square spiral inductor should be linearly proportional to the inner opening diameter ( ); this agrees well with our experimental data shown in Fig. 4. In order to provide a complete guideline on inductor scaling, a monomial expression [22] based on geometry parameters , , , and can be obtained as
(nH) (3)
where, as extracted at 900 MHz, , ,
, , , , the outer
diameter , the average
diameter (or the full ratio) and the unit of , , , and is m. The maximum error between (3) and measurement data is 9.4% and the rms error is 7.7%.
2) Quality Factor, Frequency at Q , and Self-Resonant Frequency: The quality factor for an on-chip spiral inductor in-creases as the frequency inin-creases because of increased stored energy and then drops drastically when the frequency closes to the self-resonant frequency ( ). The quality factor reaches a maximum when the frequency approaches to a value that is close to , namely, . A spiral inductor must have its higher than its application frequency for RFIC design. High quality factor and good are essential for a spiral in-ductor.
Fig. 5 shows normalized ( , measured at 900 MHz),
normalized ( , measured at ), the
fre-quency at ( ), and the self-resonant frequency for various inductor configurations. The and are
measured from the inductor with and m,
m, m, and m, giving
and . To consider a 900-MHz application from Fig. 5(c), spiral inductors with or number in series 3 are not recommended as their are almost lower than 900 MHz. Inductors with and an inner diameter smaller than 114 m can be used for the 1.9-GHz design.
When normalized for inductors with or the number in series 3 are ignored, as shown in Fig. 5(a), increases monotonically with increased , , , and with decreased and the numbers in parallel. Compared with dependence on dimensions, however, shows an opposite dependence on , , and the number in parallel, as shown in Fig. 5(b). This is because depends strongly on . That is, increases until the self-resonant effect is initiated which pushes out the storage energy inside the inductor and pulls the inductor into a self-resonant state with frequency being increased to . The initiation of the self-resonant effect is about at a frequency of approximately , which also is the frequency . As a result, is significantly influenced by . To explore the dependence on each design parameter, the following can be observed: i) increases but decreases with increased [Fig. 5(b)]; this is obviously due to decreased [Fig. 5(d)] re-sulting from increased coil to ground capacitance. ii) An inner opening diameter gives a similar dependence as . iii) The increases with increased (coil to guard ring spacing) resulting from increased substrate resistance and reduced sub-strate parasitic capacitance and hence both and in-crease. Figs. 2(a) and 5 show the reduced inductance, self-reso-nant frequency, and quality factor with reduced substrate contact guard ring distance ( ), as discussed in Section II-B. Our re-sults agree well with the claim of [19] in that the guard ring can reduce noise, but mirror effect can reduce the inductance, hurt the self-resonant frequency, and degrade quality factor. (iv) The parallel combination of inductors shows increased due to larger effective separation from coils in parallel to the guard ring. On the contrary, inductors in series show decreased and because of a larger coil-to-substrate capacitance.
Fig. 5. (a) NormalizedQ at 900 MHz where Q = 1:9, (b) normalized Qmax where Q = 2:45, (c) frequency at Q , and (d) self-resonant frequency for various inductor configurations.
Fig. 6. MeasuredQ versus frequency for various metal widths (W = 8, 10, 13, 15m).
For the optimization of inductor quality factor, the substrate effect on the of the inductor can be derived based on a sim-plified one-port circuit model shown in Fig. 7. See (4) shown at the bottom of the page. In (4), as is much less than 1
for conventional inductor and frequency is low, the is close to , which results in -independent value. The de-pendence of on at high frequency is different in a low region and high region. As frequency increases in the low region, the can be simplified to
which results in degraded with increased .
In a high region, where the is much
larger than and , the approaches
, which
gives increased with increasing . In addition, we get smaller degradation versus frequency from the ideal value ( ) with increasing . Based on (4), taking the derivative of with respect to , we can obtain the
Quality Factor imag real
Fig. 7. A simplified one-port physical model of an on-chip spiral inductor. The inductance and series resistance of the spiral is represented byL and
R , respectively. The oxide capacitance between the spiral and the substrate
is modeled byC . The resistance of the substrate is modeled by R .
giving the worst in (4) by setting the derivative to zero. The can be solved analytically as follows:
(5)
The realization of dependence on is very useful for the optimization of with appropriate substrate engineering.
It is observed that the frequencies and have dif-ferent dependencies on metal width from Fig. 5(c) and (d). The versus frequency for various metal widths is shown in Fig. 6, which exhibits that larger metal width significantly improves at lower frequency, but also induces lower . It is recom-mended to use instead of as a gauge of evaluating spiral inductor performance.
For the purpose of providing a guideline on scaling , an-other monomial expression is developed to describe at 900
MHz to be , with ,
, , , , .
The maximum error by comparison with measurement data is 16.0% and the root mean square error is 11.5%. This formula can be used for inductor geometry within the span of the orig-inal database.
III. ISOLATIONCHARACTERIZATION ANDIMPACT ON
INDUCTORS A. Improvement With Floating Well
The propagation characteristic of an Si–SiO micro-strip con-figuration is a primary energy loss element of the planar spiral inductor [17]. This loss is more pronounced for a large inductor hanging over large silicon land. Among various loss mecha-nisms [18], for silicon technology (which uses moderately con-ductive substrate and is usually operated at frequency around several GHz) the skin-effect mode is of particular interest. Note that here, for resistivity of 0.1 ohm cm (with a skin depth of
Fig. 8. Schematic view and cross sections of FW-inductor structure.
Fig. 9. Inductance and quality factor for inductors on P-well and floating N-well.
m at 1 GHz) and substrate thickness of 1000 m, the boundary frequency for the skin effect mode is GHz, while for the slow wave mode it is GHz [18]. Under the skin-effect mode, the silicon substrate begins to act as a lossy conductor wall and the longitudinal currents are close to the Si–SiO interface. Therefore, reducing the substrate loss can efficiently enhance the quality factor. In what follows, we propose a novel inductor structure to retard the longitudinal current and reduce the substrate loss by adding a floating-well (FW) to increase substrate ac resistance.
Fig. 8 shows the schematic view of an FW-inductor structure. The FW-inductor is similar to a conventional on-chip planar spiral inductor and the only change is to add a floating well junction layer under the inductor and inside the noise-reduction grounded guard ring wall. The floating well junction layer be-haves as a dc-isolation layer with high ac-resistance to reduce the substrate loss; hence, the quality factor is raised.
According to our experimental data, the inductances and quality factors for an inductor on P-well and an FW-inductor with a floating well underlaid are shown in Fig. 9. As observed
(a) (b)
(c) (d)
(e)
Fig. 10. (a) Layout of an open pattern on P-well layer or epilayer. (b) Layout of an open pattern on FW-structure. (c) MeasuredS with frequency for open patterns on P-well layer, N-epilayer, and FW-structure. (d)S reduction compared to open pattern with both FW and guard ring of: 1) solid-squares, on P-well without FW and guard ring, and 2) solid-circles, with FW only. (e) Simulated substrate conductance trend versus frequency on P-well layer and FW-structure by using Medici, where simulated current flow lines at 1 GHz are shown in the insets. The lengths of trajectoriesa-a and b-b are not scaled.
from the curve of in Fig. 9, the quality factor is improved about 31% for frequency below 1 GHz and increases to 3.07 from 2.37, which is 29% up, at 1.8 GHz. Some improvement is observed for the self-resonant frequency. There is no obvious difference for inductance at
lower frequency. Current flow in the substrate beneath the spiral would cause negative mutual coupling and thus a reduction in the low frequency inductance of the spiral. The unaffected low frequency inductance indicates that the substrate current induced by the magnetic field is small [20]. The improvement
(a)
(b)
Fig. 11. (a) Conventional inductor lumped model for on-chip spiral inductor and (b) new proposed lumped model with the addition of a combination ofL andR in parallel.
in is due to the increased substrate resistivity induced by the floating N-well and associated junction depletion layer. Furthermore, to quantify the increase of the effective substrate resistance by using FW structure, we compare the to that of an inductor on N-epi layer. The of an inductor on the FW is a little higher but very close to that on the N-epi layer with the difference within 2% below 1 GHz. The floating well structure can improve by increasing effective substrate resistance of well layer from 0.1 ohm cm (P-well resistivity) to equivalently 0.5 ohm cm (epilayer resistivity). A detailed study of the substrate resistivity enhancement using a floating N-well will be presented in the next subsection. Moreover, to obtain further improvement for other components, a complete study of substrate isolation with floating well, P-well, and N-epitaxial layer will also be presented.
B. Substrate Isolation Effects
RF signal isolation to prevent coupling noise through substrate is important for spiral inductor in silicon-substrate technology. Improved RF isolation can be achieved by using a grounded substrate guard ring surrounding the inductor [19] or by using higher resistivity ( ohm cm) N-epitaxial layer in our experiment [3]. To study the isolation effects, as shown in Fig. 10, three structures are designed: open pads on P-well, open-pads on N-epi wafer without any well [both as shown in Fig. 10(a)], and open pads with a floating N-well (FW), which
(a)
(b)
Fig. 12. Normalized inductance versus frequency for inductors with (a) various numbers of turn and (b) various inner diameters.
is surrounded by P-well, between pads [Figs. 10(b) and 8]. The pads are of a dimension of 80 m 80 m, configured with M2 and M1 stacked together with large vias. The distance between the two open pads is 574.2 m. Based on scattering parameter measurement with 0-dB input signal level, we obtain 10-dB improvement of at 3 GHz for an open pattern on N-epilayer without well implantation ( ohm cm) compared to that on a P-well implantation layer ( ohm cm). However, the improvement of using only N-epilayer decreases at a fre-quency higher than 10 GHz, indicating that the high-frefre-quency harmonics cannot be blocked by bulk with higher resistivity.
Compared to using a higher resistivity substrate, the struc-ture with both a substrate grounded guard ring and a floating N-well inside, as shown in Fig. 10(b), can give a much better isolation characteristic even for frequency above 10 GHz. The at 3 GHz for the open pattern of FW-inductor configura-tion is 15 dB lower than that on P-well and 5 dB lower than N-epi bulk, as shown in Fig. 10(c). Moreover, the isolation is more improved at a frequency higher than 10 GHz; note that 4-dB improvement at 10 GHz is shown on N-epi layer, even the isolation difference between on N-epi and on P-well vanishes. In Fig. 10(d), the difference of between an open pattern on FW-structure with surrounding guard ring and another one on FW only, marked as the solid-circles, shows the reduction induced by guard ring. The solid-squares show the reduc-tion of the open pattern with FW-structure and guard ring that
Fig. 13. Measured and simulatedS , S , S , S , inductance and quality factor for two port configuration, for inductor with N = 4 and A = 64 m. All parameters for the lumped model are shown in the parameter list table.
is compared to that on P-well. An open pattern on FW-struc-ture with guard ring shows better noise ( ) decrease than that with FW only, though the FW only pattern also shows reduced versus the one on P-well (without FW and guard ring) for a frequency below or close to 3 GHz. Note that the improve-ment of isolation from FW is because the FW forms a depletion
layer at the sidewall with low conductance to behave as a barrier to eliminate coupling signal and noise dispersion through sub-strate, which is effective for lower frequency. However, the FW has to be used together with a guard ring surrounding the FW at a frequency higher than 3 GHz for effective noise elimi-nation. In this frequency range, the guard ring is the main cause
of noise elimination because surrounding the guard ring can efficiently absorb the longitudinal currents, which flow along a trajectory close to the silicon surface. It should be noted that an FW without guard ring shows degraded noise isolation because of the reduced noise pickup by ground line ( tab) induced by the FW depletion layer at edge. The reduced pickup rela-tively enhances the noise signal propagated to port-2 ( ). Fur-thermore, an inductor on the FW shows 31% improved quality factor compared to a conventional inductor as mentioned in Sec-tion III-A. Based on these two improvements, the FW-inductor is recommended for better RF isolation and performance.
These noise improvements using an FW can be verified using MEDICI [21] simulation as shown in the insets of Fig. 10(e), where at 1 GHz, the peak current density from anode to cathode on a silicon surface decreased by ten orders in the FW (com-pared to the P-well structure). In these insets, for the P-well structure, the conductance characteristic between two surface nodes - is simulated; for the FW configuration, the conduc-tance characteristic between one surface node outside FW and another node inside FW ( ) is simulated. To observe this im-provement for various frequencies, note that in Fig. 10(e), the anode-to-cathode conductance of the FW structure decreases significantly under 10 GHz and is still half an order smaller than that of the P-well structure from 10 to 100 GHz. This simulation intends to show the change of substrate conductance’s charac-teristic inducing by FW, but it cannot give the exact variation quantity of the effective substrate resistance.
IV. SPIRALINDUCTORMODEL FORSKINEFFECT
Several equivalent-circuit models have been developed with conventional configurations and successfully used to model most on-chip spiral inductors [6], [13], [20] for designing RF ICs. In Fig. 11(a), the spiral coil structure is represented by an ideal inductance , external connection wires inductance , and , a series resistance and an interwire capacitance . The shunt parasitics result from a combination of oxide capacitance ( and ) between spiral coil and substrate and substrate parasitics ( , , , and ). Correlated with previous works [6], [13], [20], and are introduced in Fig. 11 to model inevitable external connection wires’ inductance in real circuit layout.
Fig. 12(a) and (b) shows the normalized inductance ( (frequency) MHz ) versus frequency for inductors with various numbers of turn and various inner diameters. Here, for inductors with fewer numbers of turn and smaller inner diameter, the inductance reduction with frequency becomes more apparent. This phenomenon is induced by the substrate skin effect and increased negative mutual inductance, which form frequency-dependent inductance and resistance [9], [17]. For spirals in CMOS technology, the skin effect mode is the dominating propagation mode near the first resonant frequency [17], [18]. In other words, the substrate begins to behave as a lossy conductor wall. The loss effect can be incorporated into a frequency-dependent series resistance. When frequency increases, under skin-effect mode, the longitudinal current
Fig. 14. Simulated frequency dependence of real part and (imaginary part/!) of input impedance forR and L in parallel, where the R and L values are listed in the table in Fig. 13.
near Si–SiO interface will lower the inductance. Because the skin depth (2.6 m) of Al metal layer [15] at 1 GHz is larger than metal-2 thickness, the skin effect in metal layer could be ignored for our experiment. The conventional lumped model in Fig. 11(a) cannot model correctly the inductance reduction and the series resistance increase characteristics with a frequency increase. In previous works [8], [9], a series frequency-dependent resistance was added to describe the resistance change due to the substrate skin effect, but this model is not easily performable into circuit simulator and lacks the eddy current effect and parameter extraction methodology. In this work, a simplified lumped model is presented to address the characteristic of frequency-dependent inductance and resis-tance simultaneously. Here, one resisresis-tance and inductor have been adopted into the main inductor current path, with and combined in parallel as shown in Fig. 11(b). At low frequency, signal passes through , , and and propagates between port 1 and port 2. At a higher frequency, the signal will be traveling less through due to increased impedance, but more through instead, representing the ef-fect of increased energy loss. The frequency dependences of the real part and the normalized imaginary part (imaginary part/ ) of input impedance for and in parallel are shown in Fig. 14, which demonstrates the quantities of the series resis-tance’s increase and the inducresis-tance’s reduction with increased frequency to model the skin effect and the eddy current effect. Here, the and values are from the parameters list table in Fig. 13. The power loss at is equivalently the power loss in the substrate due to the skin effect. For an inductor with and m, the agreement of inductance and quality factor between measurement and simulation is good, as shown in Fig. 13. The inserted table in Fig. 13 shows all parameters used to form a lumped model for this inductor. The errors of both real part and an imaginary part for four two-port S-parameters are below 10% for frequency lower than 7.6 GHz. This model can be used for various inductor configurations. Furthermore, from the aspect of device modeling, this model is easy to be extracted and implemented into circuit simulators.
above 3 GHz for noise improvement. Noise propagation and isolation effects in various substrate types are also investigated including P-well, N-epitaxial layer, and floating well. Finally, a circuit simulation model has been developed to consider the frequency-dependent series resistance and inductance induced by the skin effect and eddy current effect.
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Chuan-Jane Chao (M’99) received the B.S. and M.S. degrees from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1990 and 1992, respectively, all in electronics engineering. She is currently pursuing the Ph.D. degree in electronics engineering at NCTU.
From 1992 to 1998, she was with Taiwan Semi-conductor Manufacturing Corp., Hsinchu, Taiwan, R.O.C., as a Principle Device Engineer in device engineering, responsible for SPICE modeling and device characterization. Since October 1998, she has been with Winbond Electronics Corp., Hsinchu, R.O.C., where she worked on device modeling and characterization, process reliability, and ESD/Latch-up protection design. Her research interests include the areas of device and interconnect modeling, characterization, and reliability.
Shyh-Chyi Wong (S’87–M’88) received the B.S. degree in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, in 1985 and 1989, respectively.
From 1989 to 1993, she was with Analog Devices Inc., Wilmington, MA. From 1993 to 1995, she was with Taiwan Semiconductor Manufacturing Corp. (TSMC), Hsinchu, R.O.C., as the Manager of the Device Department. From 1995 to 1998, she was with the Department of Electronics Engineering, Feng-Chia University, Taichung, Taiwan, R.O.C., as an Associate Professor. Since 1998, she worked at Winbond Electronics Corp., Hsinchu, R.O.C., as the Director of Device and Reliability Division. From 1999 to 2001, she was with TSMC as the Senior Program Manager of Mixed-Signal and RF Program in R&D. In October 2001, she joined Ali Labs as an Associate Vice President. Her research interests include device and interconnect modeling, RF technology development and component design, high-frequency characterization, device reliability, and analog and RF circuit design. She has published 55 technical papers and holds 13 U.S. patents and eight R.O.C. patents.
Chi-Hung Kao was born in Taiwan, R.O.C., in 1970. He received the B.S. degree from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., in 1994, and the M.S. degree from National Cheng Kung Univer-sity, Tainan, Taiwan, R.O.C., in 1998, all in electrical engineering.
From 1998 to 2000, he was with Winbond Electronics Corp., Hsinchu, as a Device Engineer for SPICE modeling and characterization of various MOS devices, circuits, and process. Since 2000, he was with Taiwan Semiconductor Manufacturing Corp., Hsinchu, R.O.C., as the Senior Device Engineer for mixed signal and RF processes. In January 2002, he joined Ali Labs Inc. as an R&D manager. His research interests are in the area of RF device modeling and characterization.
Ming-Jer Chen (S’78–M’85–SM’98) received the B.S. degree in electrical engineering with highest honors from National Cheng-Kung University, in 1977, and the M.S. and Ph.D. degrees from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, R.O.C., in 1979 and 1985, respectively, all in electrical engineering.
Since 1985, he has been with the Department of Electronics Engineering, NCTU, where he is a Pro-fessor. From 1987 to 1992, he was a Principle Consul-tant at Taiwan Semiconductor Manufacturing Com-pany (TSMC), where he led a team to build process window and design rule. In 1996 and 1997, he enabled the ERSO/ITRI video A/D converters and the TSMC mixed-mode CMOS processes, respectively. His current research inter-ests include nanoscale reliability physics and next-generations electronics. He has graduated six Ph.D. students and has been granted four U.S. patents and six Taiwan patents.
Professor Chen is a Co-Winner of the 1992 and 1993 Chinese Young Engineer Paper Award and a Co-Winner of the 1996 Acer Distinguished Ph.D. Disserta-tion Award. He is a member of Phi Tau Phi.
Len-Yi Leu was born in Hsinchu, Taiwan, R.O.C., in 1961. He received the B.S. degree in electrophysics, in 1983, and the M.S. degree in electronics in 1985, both from National Chiao Tung University, Taiwan, R.O.C. In 1990, he received the Ph.D. degree in elec-trical engineering from University of Southern Cali-fornia.
From 1990 to 1995, he worked for Fairchild Research Center, National Semiconductor. During this period, he involved the development of process integration, device characterization, TCAD simula-tion and reliability/failure analysis of 0.8m and 0.5 m Advanced BiCMOS (ABiC) technology. From 1995 to 1996, he worked for S3 Incorporation as a Foundry Account Manager in charge of yield enhancement and technology evaluation of different foundries with the capability of 0.6m, 0.5 m and 0.35m technologies. Presently, he is working for Winbond Microelectronics Corp. as the Director of Logic Technology Division. He is heavily involved in the process development, device modeling and device reliability of advanced RF CMOS, BiCMOS, high voltage LDMOS, flat cell, standalone flash, and embedded flash technologies.
Kuang-Yi Chiu was born in Kaohsing, Taiwan, R.O.C. He received the B.S.E.E. degree from National Cheng Kung University, Taiwan, R.O.C., in 1966, the M.S.E.E. degree from National Chiao Tung University, Taiwan, R.O.C., in 1968, and the Ph.D. degree in materials science from University of Southern California, Los Angeles, in 1974.
He was at Northrop Research and Technology Center, Los Angeles, from 1973 to 1979 where he worked on radiation effects on MOS devices. He joined Hewlett Packard Company, Palo Alto, CA in 1979, as a Department Manager responsible for R&D and manufacturing of submicrometer CMOS VLSI circuits. He joined Winbond Electronics Corp. in 1995. From 1997 to 1998, he was the President of Worldwide Semiconductor Manufacturing Corp. He is presently the Executive Vice President of Winbond Electronics Corp. and the President of Winbond Electronics Corporation America. He has more than 20 years of experience in management and engineering of silicon VLSI products including device and process R&D, manufacturing, and reliability. He has presented or published more than 70 technical papers in international scientific and technical journals and conferences and holds seven U.S. patents.
