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A flexible mixed-signal/RF CMOS technology for implantable electronics applications
View the table of contents for this issue, or go to the journal homepage for more 2010 J. Micromech. Microeng. 20 045017
(http://iopscience.iop.org/0960-1317/20/4/045017)
J. Micromech. Microeng. 20 (2010) 045017 (8pp) doi:10.1088/0960-1317/20/4/045017
A flexible mixed-signal/RF CMOS
technology for implantable electronics
applications
C Y Hsieh
1, C S Chen
2, W A Tsou
2, Y T Yeh
1, K A Wen
2and L-S Fan
1 1Institute of NEMS, National Tsing Hua University, Hsinchu, Taiwan, Republic of China2Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan,
Republic of China E-mail:lsfan@ieee.org
Received 16 November 2009, in final form 7 January 2010 Published 17 March 2010
Online atstacks.iop.org/JMM/20/045017
Abstract
A novel post-CMOS fabrication process has been developed to transform a 0.18 μm 1P6M mixed-signal/RF CMOS (complementary metal oxide semiconductor)-integrated circuit chips fabricated on an 8 inch SOI (silicon-on-insulator) wafer into flexible devices sandwiched between biocompatible material (10 μm parylene-C on both sides in this case) and enables future implementation of implantable and fully integrated electronic devices. The
functionality of the flexible integrated circuits is demonstrated by a low phase noise RF CMOS VCO (voltage-controlled oscillator) circuit in a ring oscillator configuration that operates at a few hundred MHz to GHz. We report here the associated post-processing technology to make these flexible IC chips and the characterization of both MOS transistors and the demonstration circuit on the flexible IC chip under bending stresses.
(Some figures in this article are in colour only in the electronic version)
1. Introduction
Implantable electronic devices have drawn increasing attention for their applications in clinical diagnosis/monitoring and medical care [1]. The better these small, biocompatible, integrated-circuit devices are integrated with various micro sensing devices, the more medical applications they can be applied to (e.g. implantable sensors for monitoring blood pressure and flow and RF ID+ tags, artificial retina, etc). The additional characteristics of flexibility of these integrated devices are frequently desirable for many medical applications such as conforming to a curved surface, squeezing inside a stent, a small catheter tube or attaching them to soft tissues. However, most previous research on flexible thin-film electronic devices focused on the media applications. These include electronic paper, portable displays, etc based on organic thin film transistors technology. Although promising in the future, currently transistors based on these organic flexible materials typically show low mobility (from μ ∼ 10 cm2 V−1 s−1) [2] and low integration densities and thus limited signal processing capability. Recent developments
in the backside illuminated CMOS image sensor have a thinned silicon substrate which will make the device more flexible; however, the silicon thickness (presumably several times of the few micrometers absorption lengths of visible lights in silicon) and the process details are not disclosed. For medical implant applications that require some local signal processing capabilities, we have developed a flexible post-CMOS technology based on a standard 0.18 μm 1P6M mixed-signal/RF CMOS process on 8 inch SOI wafers. This post-fabrication process removes the majority of silicon substrates of the integrated circuits and replaces them with flexible parylene-C (poly-para-xylylene C) films which are used as the substrate layer as well as the passivation layer for the circuits. Although not limited to this polymer, parylene-C is chemically inert, biocompatible and can be deposited by the chemical vapor deposition process at room temperature. These features make parylene-C a convenient material for post-processing. We developed the post-fabrication process utilizing parylene-C material to make flexible and potentially biocompatible integrated circuits, and use both the MOS transistor devices and a CMOS circuit (a voltage-controlled oscillator) to verify
J. Micromech. Microeng. 20 (2010) 045017 C Y Hsieh et al
the feasibility of this fabrication technology. The effects of stresses on these transistors are characterized for both compressive stresses and tensile stresses in longitudinal and transverse directions [3].
The ISO/DIS 10993 set entails a series of standards for evaluating the biocompatibility of a medical device prior to a clinical study. Parylene-C is an FDA approved Class-VI implantable plastic material with a long history of being used in pace maker and other implantable electronic packages [4–8]. It was tested as a chronically stable microelectrode insulator [4–6], proven successful in CNS (central nervous system) implants with minimal gliosis [5, 7], tested for its blood compatibility as an electronics-coating polymer film [8] and showed excellent result in cytotoxicity tests. This paper focuses on the technology and the characterization of parylene-based flexible transistors, but the study of biocompatibility is not covered and it should be assessed before clinical study.
2. Fabrication process
The flexible CMOS microsystem fabrication process used to implement the MOS transistor is outlined in figure1. After the completion of a 1P6M 0.18 μm CMOS process on 8 inch SOI wafers with a 1 μm thick silicon epitaxial layer (figure1(a)), the wafers are processed in a few more post-processing steps to make them flexible and potentially biocompatible as following. The post-CMOS process begins by depositing a 10 μm thick biocompatible parylene-C material to cover the circuit area (figure1(b)). An adhesion promoter (silane A-174) is used to improve the adhesion of parylene to the silicon nitride passivation layer on the front circuit side. Parylene-C is selected due to its mechanical flexibility (Young’s modulus ∼3 GPa) and biocompatibility. The wafer is then bonded on the front side (already coated with the parylene-C layer) to a carrier substrate (figure 1(c)) in a wafer bonding machine. After bonding to the carrier substrate, the Si wafer substrate is mechanically thinned to a thickness of∼50 μm by a wafer lapping machine. The resulting surface micro-crack damages induced during the lapping process are removed by a silicon chemical etching (such as dry XeF2 etching processes) with
the buried oxide layer as the etch stop (figure 1(d)). Now the remaining silicon substrate is 1 μm thick. To protect the backside and balance the residual and in-use thermal stresses of the front-side parylene-C film, the backside substrate is coated by another parylene-C layer of the same 10 μm thickness (figure1(e)). The adhesion promoter (silane A-174) is again used to improve the adhesion of parylene-C to the back substrate side. The remaining 1 μm thick silicon substrate in the region of dicing lanes is etched away before this second parylene deposition, so that the parylene-C layers on both sides of the wafer touch each other in this region and individual dies can be separated by a surgical knife.
To be able to characterize the transistors and circuits performance in a probe station, we open its electrical pads, although pads are not needed for passive circuit application. For this characterization purpose, the sandwiched structure is again bonded on the silicon substrate side to a carrier substrate (figure1(f )), and the pads are opened (figure1(g)) by oxygen
(a) (b) (c) (d) (e) ( f ) (g) (h)
Figure 1.Fabrication process of a biocompatible flexible IC: (a) the SOI wafer with fabricated MOS transistors; (b) parylene coating on the front circuit side; (c) bonding the SOI wafer to a carrier substrate on the front side; (d) Si substrate is removed; (e) parylene deposited on the backside; (f ) transfer of the wafer to another carrier substrate; (g) pad opening; (h) debonding SOI chip from the carrier substrate.
plasma RIE etch with the AZ 9260 photoresist as the masking material defining the pad opening area. The etching rate of parylene-C is 0.73 μm min−1 when the oxygen plasma was controlled at 200 W, 50 sccm and chamber pressure at 150 mtorr.
Finally, the flexible 8wafers are de-bonded from carrier wafer (figure1(h)) and can be cut into individual dies. The flexible CMOS wafers are sandwiched between and passivated by two parylene-C layers. The sandwiched structure consists of parylene-C film, silicon device layer (∼1 μm thick) of the SOI wafer and parylene-C film. Since the remaining silicon device layer of the processed SOI wafer is only∼1 μm thick, the circuit chip is semi-transparent even to light of shorter wavelength with photon energy more than the silicon band gap as shown in figure 2 with a piece of the flexible wafer placed in front of a color display (it also indicates that the flexible technology described in this paper will not be used in an optimized imaging sensor. An optimized imaging sensor needs thicker semiconducting layers of at least several photo absorption lengths in thickness to be efficient in photo-electron conversion.) Figure3shows the flexible CMOS wafer piece released from the carrier wafer after completing the post-process and cut into a stripe, and the slight curling of substrate piece was caused by both the residual stresses of
Figure 2.A semi-transparent flexible CMOS wafer piece (5 cm× 3 cm) after the process.
Figure 3.A biocompatible flexible CMOS wafer after the process (2 cm× 5 cm).
CMOS surface layers (oxide and metallization layers) and the stresses induced by the post-CMOS process. Since the maximum stress experienced by the chip under a bending to a fixed radius of curvature is proportional to the thickness of the chip, the very thin chip can be curled into a small radius of curvature. Repeating tests indicate that a stress level of (±) 100 MPa can be applied to devices safely. As shown in figure4, a flexible CMOS wafer piece (∼1.2 cm × 1.2 cm) can
be curled into a cylindrical shape and inserted into a 4 mm ID (inner diameter) glass capillary tube to simulate the possible environment of potential applications such as inside a stent. The corresponding maximum stresses on the IC and devices in this case are around 180 MPa.
3. Characterization of the flexible transistors
The fabricated transistors have a channel length L= 0.18 μm, gate oxide thickness is 42 ˚A and channel width W = 25 μm. The test n-channel and p-channel field-effect transistors were fabricated on (1 0 0) silicon and the chips were made flexible by the above post-CMOS process. As shown in figures5(a) and (b) for n-channel and p-channel transistors, the current to voltage characteristics were measured by a semiconductor parameter analyzer HP4156C in a probe station before and after the flexible post-processing, with the flexible transistor
Figure 4.A flexible CMOS wafer piece (∼1.2 cm × 1.2 cm) curled into a cylindrical shape and inserted into a 4 mm diameter glass capillary tube.
Table 1.The measured threshold voltages of transistors before and after post-processing.
Threshold voltage (V) Transistor type Before process After process
NMOS 0.567 0.560
PMOS 0.537 0.528
devices bonded to a carrier substrate in the latter case. The red lines are the characteristics of the MOS transistor measured before the post-processing, whereas the blue lines indicate the MOS transistor drain current to drain voltage curve measured after the post-processing. A slightly variation of the transistor drain current (less than 15%) after the post-processing steps was observed presumably due to enhanced bending from residual stresses of CMOS thin-film stack and interface defects created during the post-processing steps [11,12]. The residue stresses of the metal (typically tensile) and oxide (typically compressive) stack of the CMOS deform the silicon substrate. This deformation will increase when the majority bulk of the silicon substrate is removed and this enhanced deformation induces further stresses on transistors and cause mobility change.
The threshold voltages of MOS transistors were obtained by measuring the I–V characteristics at a low drain to source voltage of|Vds| = 0.1 V with a linear extrapolation method
[10]. From the standard expression of the drain current of an n-channel MOSFET in the linear region [9],
Id = (μnCox) W L (VGS− Vt)VDS− 1 2V 2 DS , (1) where μnrepresents the carrier mobility in the channel and Cox
is the oxide capacitance. Vt, VGS and VDS are the threshold
voltage, voltage between gate to source and drain to source respectively. The transistor threshold voltages are derived from the x-intercepts of equation (1) at Vt = VGS−VDS2 , and
the values before and after the post-processing steps for each type of MOSFETs are listed in table1.
Since the implantable and flexible microsystems are intended to operate under external mechanical stresses, the effects of bending stresses on the MOS transistors are characterized. When a transistor is under mechanical stresses,
J. Micromech. Microeng. 20 (2010) 045017 C Y Hsieh et al
(a)
(b)
Figure 5.The measured transistor characteristics of drain current versus drain voltage before and after post-processing steps for (a) channel length 0.18 μm n-type MOS and (b) channel length 0.18 μm p-type MOS.
Figure 6.The schematics of the 4PB fixture used to generate uniform stress between the inner props.
the energy band structure will change, and thus the effective mass of carriers and the associate density of states, etc will vary accordingly. A four-point-bending (4PB) test setup as shown in the schematics of figure6is used to apply external mechanical stresses uniformly between the two inner points on the flexible chips and the actual 4PB fixture is shown in figure7.
A uniform uniaxial stress between the middle two props is established on the surface and it can be shown to be
σ = 3(L− d)F
ht2 , (2)
Figure 7.Actual 4PB fixture used in the experiment.
when the beam deformation is small and the dimensions of t and h are small in comparison to d and L, where t denotes the thickness of the plate, h the width of the plate,
F the applied force, L the distance between the two upper
Figure 8.Normalized transconductance change versus applied stress of n-type MOS transistors under tensile and compressive stress in both the longitudinal direction and transverse direction relative to the transistors’ channel direction.
props and d the distance between the two lower props. The applied stress can be either tensile or compressive depending on whether d < L or d > L. The transconductance of the MOS transistors and the threshold voltages are extracted from its I-V characteristics when the channel and immediate surrounding region is under tensile or compressive stress (between −100 MPa and 100 MPa) in both longitudinal and transverse directions in reference to the channel length direction. Both n-type and p-type MOS transistors with channel length L = 0.18 μm and the gate oxide thickness is 42 ˚A were used for stress characterization. A piece of the flexible IC containing these individual MOS transistors was bonded onto a rectangular silicon strip 500 μm in thickness. We kept the applied mechanical stress within (±) 100 MPa to avoid cracking the Si strip initiated from edge defects which occurred when the stress was approaching 200 MPa. The calibration of 4PB fixture was carried out by using a strain gauge (Vishay C061117-C) and Keithly 2410. The calibrated four-point bending jig is adapted to a shielded probe station to apply controlled uniform stresses (tensile or compressive) on the sample and the I-V characteristics are measured.
The drain current expression of n-channel MOSFET in the linear region is expressed as in equation (1) above, and we get the threshold voltage from the x-intercept of the Id
versus VGS curves and the electron mobility from the slope
Slope= μnCox(W/L) VDS.
The variation of threshold voltage and transconductance under stress can be measured from the slope and intercept of transfer characteristics of the transistor in the linear region as a function of applied stress. The measured percentage change of transconductance versus stresses relation is shown in figures8
and9. This normalized transconductanceGm
Gm variation of the
flexible MOS transistors under stresses can be fit by a linear relationship with the uniaxial stresses in both longitudinal and
Figure 9.Normalized transconductance change versus applied stress of p-type MOS transistors under tensile and compressive stress in both the longitudinal direction and the transverse direction relative to the transistors’ channel direction.
Table 2.Stress effects on a 0.18 μm MOS transistor. Piezo NMOS devices PMOS devices parameters (×10−12Pa−1) (×10−12Pa−1) IIL 266 −69.4 IIT 131 50.3 transverse directions as Gm Gm = T (orL) σ, (3)
where Lis the longitudinal piezo-coefficient and T is the
transversal piezo-coefficient. It is also shown that∼(±) 3% variation of transconductance change per 108 Pa stress in
the longitudinal direction has been observed roughly twice of that in the transverse direction. However, the PMOS transistor changes only (±) 1% variation of transconductance. Table 2 summarizes the piezo-coefficients of the flexible transistors. The threshold voltage is found to only have small sensitivity to stress as shown in figure10. These parameters will be used for pre-compensations in circuits design based on this technology.
4. Flexible circuit implementation and
characterization
A low phase noise CMOS voltage-controlled oscillator in ring oscillator configuration is made on the flexible substrate as shown in the die photo figure11to assess the functionality of the flexible circuits after the post-processing. The oscillator circuit consists of four stages of differential pairs and each stage contains six p-MOS and three n-MOS transistors. The numbers of series connection stage alter the oscillation frequency caused by the delay of the oscillation signal. Figure 12 shows the schematic circuits of the tested ring oscillator. These four differential pairs in each stage consist of both p-MOS and n-MOS transistors as shown in
J. Micromech. Microeng. 20 (2010) 045017 C Y Hsieh et al
(a)
(b)
Figure 10.Measured MOS threshold voltage under (a) compressive and (b) tensile stress for both n- and p-type transistors in longitudinal and transverse directions.
Figure 11.The die photo of the voltage-controlled oscillator made on the flexible substrate to assess the effect of post-CMOS processing described in the text (1130 μm× 610 μm).
figure13with the sizes of the MOS transistors labeled. The differential pair circuit uses p-MOS transistors of the channel width of W = 16 μm, 6 μm and 3 μm, channel length L = 0.5 μm, and n-MOS transistors with the channel length and
Figure 12.The schematic diagram of the ring oscillator configuration with 0/1 represents the input signal. Notice the cross-over of the wiring in the middle for this four-stage ring oscillator to make the oscillation.
width of 32 μm, 0.34 μm and 2 μm, respectively. Figure13
shows four differential pairs connection, where VB is the bias voltage and VC is the tuning voltage which controls the output resistance of p-MOS differential pair. Frequency is controlled by changing the VB bias voltage and hence the delay through each n- and p-MOS transistors. The frequency spectrum was measured by a spectrum analyzer E4407B. The center
Figure 13.The circuit diagram of each differential pair stage in figure12. The input VB is the bias voltage and VC is the tuning voltage which controls the output resistance of p-MOS differential pair.
Figure 14.The measured VCO frequency spectrum has the center frequency at 1.08 GHz.
frequency of the oscillator is 1.085 GHz and power dissipation is 16 mW. The phase noise measured before and after this transform process is−100.8 dBc Hz−1and−98.83 dBc Hz−1 respectively. Figure14shows the oscillation frequency before and after the post-processing. The oscillation frequency varies from 1.015 GHz to 750 MHz when the tuning voltage changes from 0.4 V to 0.9 V as shown in figure15. Figure16shows the induced changes of oscillation frequency due to external stresses when the tuning voltage is fixed at 0 V. The oscillation frequency increases under compressive stress and decreases under tensile stress. Figure17shows the tuning of oscillation frequency under external stresses. This RF circuit was used with a simple division circuit for the frequency band of Medical Implant Communications Service (MICS) for 402–405 MHz, ISM band, which is an ultra-low power, unlicensed, mobile radio service band for transmitting data in support of diagnostic or therapeutic functions associated with implanted medical devices.
Figure 15.The measured characteristics of oscillation frequency versus tuning voltage before and after post-processing.
Figure 16.Measured oscillation frequency change under external stress.
Figure 17.Measured oscillation frequency and bias voltage versus different stress conditions.
5. Summary and discussion
We have demonstrated a micro fabrication technology to make flexible 0.18 μm 1P6M mixed signal/RF CMOS
J. Micromech. Microeng. 20 (2010) 045017 C Y Hsieh et al
circuits for medical implant applications. Functionality of electronic devices and circuits are demonstrated with MOS transistors and GHz CMOS RF VCO made by this flexible technology. RF components can be implemented using this technology. Further implementation of CMOS-compatible MEMS components will allow the realization of compact and fully integrated implantable microsystems. Since these implantable devices will be used in some physical environments with applied external stresses and stress is known to change transistor characteristics [13–16], stress effects on these electronic devices and circuitry are characterized for pre-compensation in the circuit designs. Although the threshold voltages change very little for both nMOS and pMOS, the electron mobility in the n-channel device increases linearly with both longitudinal and transverse tensile stresses within the applied stress range reported here. The hole mobility in the p-channel device increases linearly with applied transverse stresses but decreases linearly with applied longitudinal tensile stresses. (When the applied stresses change sign to compressive, the effects also change reversely.) The transconductances of the nMOS and pMOS transistors in the ring oscillator change with the applied stresses, and this influences the charging and discharging time of the gates of the following stage and thus the resonant frequency. This can be applied to applications such as implantable RF stress sensors using these flexible CMOS circuits without additional transduction elements.
Acknowledgment
The authors would like to thank UMC and TSMC for supporting 80.18 μm 1P6M mixed-signal/RF CMOS wafer fabrication.
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