Effect of bottom electrodes on dielectric relaxation and defect analysis of (Ba0.47Sr0.53)TiO3 thin film capacitors

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Effect of bottom electrodes on dielectric relaxation and defect

analysis of (Ba

0.47

Sr

0.53

)TiO

3

thin ®lm capacitors

M.S. Tsai, T.Y. Tseng

*

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30050, Taiwan Received 13 April 1998; received in revised form 10 July 1998; accepted 14 July 1998

Abstract

The dielectric relaxation and defect analysis of (Ba0.47Sr0.53)TiO3(BST) thin ®lms deposited on various bottom electrodes, such as Pt, Ir,

IrO2/Ir, Ru, RuO2/Ru before and after annealing in O2ambient was investigated. Through the measurement of dielectric dispersion as a

function of frequency (100 Hz f 10 MHz) and temperature (278C T 1508C), we studied the trapping dielectric relaxation and defect quantity of the ®lms, and proposed an equivalent circuit on the basis of the capacitance, admittance and impedance spectra. A shallow trap level located at 0.005±0.01 eV below the conduction band was observed from the admittance spectral studies in the temperature range of 27±1508C. The origin of dielectric relaxation and defect concentration was attributed to the existence of the grain boundary defect, interface defect and shallow trap level in the ®lms. An equivalent circuit was established which can well explain the AC response and identify the contribution of defects on electrical properties of BST thin ®lm. From the viewpoint of trapping phenomena and dielectric relaxation analyses, we propose Ir as the optimum material for bottom electrode to withstand the post-annealing treatment. # 1998 Elsevier Science S.A. All rights reserved.

Keywords: Bottom electrodes; Dielectric relaxation; Defect analysis; Barium strontium titanate; Thin ®lm capacitors

1. Introduction

Barium strontium titanate (Ba0.47Sr0.53)TiO3(BST) thin

®lms are one of the most promising materials for practical use in the capacitor of giga-bit dynamic random access memories (DRAMs) because of its high dielectric constant, low leakage current density, high dielectric breakdown strength, paraelectric perovskite phase do not exhibit fati-gue, aging and the ease of composition control [1±9].

There are at least four possible defects, namely, the interface-defect at metal/BST Schottky junction [10], the grain boundary defect, oxygen vacancies and conduction electron existing in the metal/BST/metal capacitors, which may lead to dielectric relaxation as a function of frequency. The complex plane analysis is a valuable tool for the characterization of dielectric relaxation in ceramic capaci-tors. A semicircular ®t of the AC data (Cole±Cole plot) in any plane suggests an appropriate equivalent R±C circuit that represents the observed spectra. Several works were recently carried out using this technique in thin ®lm capa-citors such as RuO2/BST [11], RuO2/PZT [12] and Pt/BST

[13] to explain the nature of dielectric relaxation.

The bottom electrode materials greatly affect the elec-trical characteristic of the BST thin capacitor [14,15]. However, systematic studies of the effect of AC electrical response of BST thin ®lms on various bottom electrodes are still lacking. In this work, we have investigated the effects of bottom electrodes (Pt, Ir, IrO2/Ir, Ru, RuO2/Ru) during

deposition on the AC electrical response and the realistic equivalent circuit by three complex planes (capacitance, impedance and admittance) analyses in BST thin ®lms without and with post-annealing, and propose them as optimum electrode materials. This paper also reports the observed shallow trap level and the total defect quantity of interface defect and grain boundary defect using admittance spectroscopy, which helps in better understanding of the effect of dielectric relaxation on electrical properties of BST ®lms.

2. Defect traps in BST

The defect often leads to dielectric relaxation as a func-tion of frequency, in which the dielectric constant decreases and loss tangent increases with increasing frequency. The defect traps of perovskite titanates may include three major

*Corresponding author. E-mail: [email protected]

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categories: grain boundary defect [16,17], interface defect at BST/metal interface [16,17] and shallow trap level [18,19]. In the case of grain boundary defect, it is considered that the grain boundary in dielectric ceramics represents a resistor R and the grain is a thin insulating layer C. There are many such RC series equivalent circuits in parallel throughout the ceramic. Based on the equivalent circuit analysis it indicates that the grain boundary plays a prominent role in the relaxation of ceramics. The grain boundary defect exists within the non-stoichiometry grain boundary and the domi-nant defect is the oxygen vacancy. In the case of interface defect, it exists within the forbidden gap due to the inter-ruption of the periodic lattice structure. The positively charged oxygen vacancies with relatively high mobility, electromigrate toward the cathode under DC electric ®eld. The oxygen vacancies then pile up at the front of the cathode and are compensated by the electron injected from the cathode. On the other hand, at the anode, an electrode reaction leads to generation of oxygen gas and electrons, leaving oxygen vacancies behind, and may cause an oxida-tion of electrode material. The reducoxida-tion reacoxida-tion leads to a growth of an n-conducting cathodic region toward the anode, and to an increase of electronic conductivity. The net result is that the space charge accumulation at grain boundaries and interface of BST/metal reduces the barrier height at grain boundaries and interface barrier height, and increases the leakage current and forms the dielectric relaxation. The details are given in reference [17].

The current induced by grain boundary defects is attrib-uted to Poole±Frenkel conduction [10], and the current induced by interface defects is attributed to the Schottky emission [10,17]. The grain boundary defects and interface defects can be also determined by DC measurement and stress [10,17]. The energy of grain boundary defects and interface defects is about 0.25±0.35 eV [10] which is one order larger than the thermal energy (kT) 0.026±0.032 eV at 27±1008C, where k is the Boltzmann constant. Hence, the emission rate (grain boundary defect and interface defect) may be affected slightly by the temperature and approach nearly independent of temperature.

The shallow trap level can be determined under small-signal AC stress applied at various temperatures [19]. A level is referred to as an electron trapping state, when the predominant charge exchange is between the conduction band and the trap level. Under small-signal AC stress applied at the Schottky junction, the depletion layer width varies about its equilibrium position due to trapping and detrapping of electrons from the oxygen vacancies or shal-low trap level, denoted by Et[20]. The shallow trap level is

near the conduction band, and hence its emission rate will be affected by temperature.

The band-diagram before contact for the Pt±BST±Pt system is shown in Fig. 1(a) where the BST ®lm has smaller grain size [14] and the work function of Pt is 5.6 eV. Fig. 1(b) indicates the diagram for the Ru (bottom elec-trode)±BST±Pt (top electrode) system in which the BST

®lm has a larger grain size [14] and the work function of Ru is 4.8 eV. The electron af®nity of BST is assumed to be 4.1 eV and the energy bandgap is 3.5 eV [21]. Fig. 2(a) shows the energy band after contact and the creation and

Fig. 1. The energy band situation in (a) Pt±BST±Pt, (b) Ru (bottom electrode)±BST±Pt (top electrode) system before contact.

Fig. 2. Schematic band diagram for BST thin film capacitor for explaining (a) conduction and defect and (b) the catch and escape of the carriers on defects.

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migration of defects, such as oxygen vacancies. The symbol `-' represents the electron captured by oxygen vacancy accumulated at the interface. The BST ®lm on Pt has a large area of grain boundaries due to small grain size, and the grain boundaries would depress the oxygen vacancy migration which leads to the formation of the n-conducting region [16]. The barrier height at the interface of BST/Pt is larger such that there is higher resistance for the deteriora-tion of the Schottky barrier. However, under a relatively high ®eld, the migration and pilling up of oxygen vacancies near the cathode certainly lower the resistance of the Schottky junction. Fig. 2(b) indicates the catch and escape of the carriers in the grain boundary defect, interface defect and shallow trap level under the applied small-signal AC stress. The interface defect and grain boundary defect need larger escape-energy than the shallow trap level.

3. Complex-plane analysis

The electrical behavior of a capacitor may be expressed in terms of the admittance (Y) and impedance (Z) of a unit cube (with parallel plane electrodes) which can be de®ned by the following equations Y I!=V! Gp! jBp! (1) Z V!=I! Rs! jXs! (2) Y j! C! j! C0_{ÿ jC}00_j!C 0 "0ÿ j"00 (3) Comparison of Eqs. (1)±(3) shows that the following relations hold,

Gp! !C00 !C0"00 (4)

Bp! !C0 !C0"0 (5)

where ! is the angular frequency, I(!) and V(!) the elec-trical current and applied voltage as a function of !; Gp(!)

and Bp(!) the parallel relative real admittance

(conduc-tance) and imaginary admittance as a function of !; Rs(!)

and Xs(!) the series relative real impedance (resistance) and

imaginary impedance (reactance) as a function of !; C0the

geometric capacitance in free space; "0_{and "}00_{the relative}

real and imaginary dielectric constant; C0 _{and C}00 _{the real}

and imaginary capacitance.

Fig. 3 shows the variation of C0_{and C}00_{of BST deposited}

on Pt with frequency in the measurement temperature range of 27±1508C. Resonance was observed at a frequency between 1 and 10 MHz. From this result, we can explain the large increase in the dielectric loss, as shown in Fig. 10(a). The resonance frequency for thickness mode is determined by electromechanical coupling factor and should be in the range of 1±10 GHz for BST ®lms with a thickness of 0.5 mm. Therefore, the resonance observed in BST ®lms cannot be attributed to piezoelectric resonance [9]. Another resonance can arise from the resonance of an

electrical equivalent circuit. Fig. 4 shows the capacitance (C(!)) complex plane of BST deposited on Pt at various temperatures. We proposed a practical equivalent circuit for BST capacitors, as shown in Fig. 5 [22]. The resonance frequency of the electrical equivalent circuit !re(C0 0) is

determined by the following equation:

!reC0 0 LeqCeqÿ1=2 (6)

Fig. 3. Frequency dependence of relative real capacitance (C0_{), imaginary}

capacitance (C00_{) of BST thin films deposited on Pt bottom electrode at}

various temperatures.

Fig. 4. Complex capacitance plot (C) of BST thin films deposited on Pt bottom electrode at various temperatures.

Fig. 5. The schematic equivalent circuit model for BST capacitor at frequency range from 100 Hz to 10 MHz.

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where Leqand Ceqare the inductance and the capacitance of

the equivalent circuit. The capacitance (Ceq) of the

equiva-lent circuit is mainly determined by the capacitance of the BST ®lm. The inductance (Leq) of the equivalent circuit is

determined by the conductivity of the electrode and BST ®lm. But the resonance is not observed in BST ®lms with a different range of capacitances, supporting the argument that the origin of the resonance is the equivalent circuit [9]. Therefore, this phenomenon is due to electrical resonance which is related to the electrode area of the ®lms (255 mm diameter). Fig. 6 shows that the Leqat 100 KHz for Pt, Ir,

IrO2/Ir, Ru, RuO2/Ru and Ir(6008C) (BST on Ir annealed at

6008C for 20 min O2 ambient after deposition) bottom

electrodes at 278C. And Leq values of Pt, Ir, IrO2/Ir, Ru,

RuO2/Ru and Ir(6008C) are about 1±14 mH. These Leq

values are the same at the frequency range from 100 Hz to 1 MHz.

The physical difference between relaxation and reso-nance lies in the fact that the latter corresponds to an oscillatory time domain response, where the discharge current changes signs periodically, and this is associated with the presence in the system of two complementary forms of energy storage. In R±C±L circuit the capacitance stores electrostatic energy while the inductance stores the magnetic energy, in its mechanical counterpart, the com-pliance stores potential energy, the inertia stores kinetic energy. In the case of an electromagnetic wave we have electrostatic and magnetic energies in the components of the electric and magnetic ®elds of the wave. These two energies may interchange, producing periodic oscillations which are damped through the dissipative processes, represented by the resistance R gradually reduce the total energy of the system. The other types of circuit consisting only of capa-citances and conductances, cannot transfer energy to another form and therefore give in the time domain a continuous decay without overswing into the other sense of current ¯ow. The resistance (Req) of the equivalent circuit

is determined by the resistance of electrode, grain boundary defect and interface defect.

The impedance (Z) of the equivalent circuit (Fig. 5) is Z Req j!Leq 1=j!Ceq (7)

For the frequency range of 100 Hz f 1 MHz, the value of inductance can be neglected, because the !Leqvalue is 1±

2 order smaller than the l/!Ceq value. Hence, we can

simplify the equivalent circuit consisting of only capaci-tance (Ceq) and resistance (Req). Fig. 7 shows the impedance

(Z) complex plane plots of BST deposited on Pt at various temperatures. Fig. 8 shows the admittance (Y) complex plane plots of BST deposited on Pt at various temperatures. These Z and Y complex quantities can be expressed in terms

Fig. 6. Inductance of various bottom electrodes at frequency 100 kHz.

Fig. 7. Complex impedance plot (Z) of BST thin films deposited on Pt bottom electrode at various temperatures.

Fig. 8. Complex admittance plot (Y) of BST thin films deposited on Pt bottom electrode at various temperatures.

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of Gpand Cp. Cpand Gpare the equivalent parallel

capa-citance and conductance of the entire circuit.

Z! ReZ jImZ Rs jXs (8)

Y! ReY jImY Gp j!Cp (9)

The admittance (Y) data forms a semicircle, as shown in Fig. 8. Hence, the series RC combination appears to be a satisfactory representation of AC response for the frequency range of 100 Hz f 1 MHz. On the basis of Z and Y planes analysis [22,23], we proposed a practical equivalent circuit for BST capacitors, as shown Fig. 9. The Rel

repre-sents the electrode resistance, Cvis the frequency-dependent

capacitance due to the grain, and Rv is the

frequency-dependent resistance due to grain boundary and interface. The frequency-dependent resistance Rvand capacitance Cv,

where Cvis parallel with Rvcan be determined as follows

[23]:

Gp!; T aT !n 1=Rv (10)

Bp!; T bT !n !Cv (11)

n 1 ÿ 2= (12)

Rs!; T AT !ÿn (13)

where n is a constant, a and b are the coef®cients as a function of temperature, and is the depression angle of a semicircular response in the impedance (Z) and admittance (Y) complex planes. Thus by assuming an exponential distribution of Gp(!,T) and Bp(!,T), we are able to transform

the total impedance into an equivalent circuit containing frequency dependent resistor, Rv, in parallel with a

fre-quency dependent capacitor, Cv. The exponent n, which

is extracted from the depression angle and suggested to be associated with the loss degree of the material, shows a temperature dependence similar to that of a useful para-meter extracted from the AC conductivity-frequency mea-surements [24].

4. Experimental

BST thin ®lms were deposited on metals/SiO2/(100)Si

(with Pt, Ir, IrO2/Ir, Ru and RuO2/Ru as bottom electrodes)

by RF magnetron sputtering. The starting p-type silicon wafer was cleaned by a standard initial cleaning process and chemically etched in a dilute HF solution. The 100 nm thick SiO2 layer was thermally grown at 10508C in a

dry oxidation furnace. The metal layers on SiO2/Si

sub-strate with a thickness of 100 nm were deposited using a separate RF magnetron sputtering system. The Pt, Ir and IrO2 ®lms were prepared at a ®xed power of 50 W

(power density is 2.55 W cmÿ2_{), constant pressure of}

5 mTorr a substrate temperature of 3508C. The Ru and RuO2 ®lms were prepared at a ®xed power of 100 W

(power density is 5.1 W cmÿ2_{), constant pressure of}

10 mTorr and substrate temperature of 3508C. IrO2 and

RuO2 ®lms were formed by RF magnetron sputtering

with Ar and O2 mixture in the mixing ratio of 4:1. The

measured resistivities of Pt, Ir, IrO2, Ru and RuO2 were

about 16.9, 27.1, 67, 228 and 370 m cm, respectively, at room temperature.

The BST (Ba/Sr 0.5/0.5) targets with a diameter of 3 in. and a thickness of 1/4 in. were synthesized using standard solid-state reaction process. The sputtering chamber was evacuated to a base pressure of 2 10ÿ6_Torr.

All ®lms were prepared at a ®xed power of 100 W (power density is 2.26 W cmÿ2_{) and constant pressure of 10 mTorr}

which was maintained by a mixture of argon and oxygen in the mixing ratio of 1 : 1 with a total ¯ow of 20 sccm. All the BST ®lms have the same thickness of around 80 nm. The substrate temperature of the sputtered BST ®lms was at 5008C. The composition of BST thin ®lms is Ba/Sr 0.47/0.53. The compositional difference between target and thin ®lm is due to sputtering yield. After deposition, the BST thin ®lms were post-annealed at temperatures ranging from 5008C to 7008C in O2

atmo-sphere using a quartz tube furnace (FN) for 20 min. Finally, the 50 nm thick top Pt electrodes with diameters of 165, 255 and 350 mm were sputter-patterned by the shadow mask process.

The ®lm thickness was determined by ellipsometry. The structure was characterized by X-ray diffraction (XRD, Siemens D5000). On the basis of XRD data, the average grain size was determined by using Scherrer's formula [6]. The surface roughness and morphology were examined by atomic force microscopy (AFM, Digital Instruments Nano-Scope III). The capacitance±voltage (C±V) characteristics were measured on the metal±insulator±metal (MIM) struc-ture by measuring the capacitance at 100 kHz as a function of a swept positive-to-negative voltage bias. Dielectric constant of the ®lms was calculated from the capacitance measured at 100 kHz without bias voltage. The admittance and impedance spectra were measured as a function of frequency with a Hewlett±Packard (HP) 4194A impedance gain phase analyzer and the temperature was varied from 27 to 1508C. The AC electrical data, in the form of parallel capacitance and conductance, were recorded in the fre-quency range of 100 Hz±10 MHz at an AC signal amplitude of 0.1 V.

Fig. 9. The schematic equivalent circuit model for BST capacitor at frequency range from 100 Hz to 1 MHz.

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5. Results and discussion

The bottom electrode had a pronounced effect on the dielectric constant and the leakage current density of the BST ®lms measured at 100 kV cmÿ1_{with a delay time of}

30 s. It has been indicated in a previous study that the BST ®lm deposited on Ru bottom electrode had a maximum dielectric constant of 548 and leakage current density of 3.94 10ÿ7_{A cm}ÿ2 _{[14]. The BST ®lm deposited on Pt}

bottom electrode had the minimum dielectric constant of 219 and leakage current density of 2.2 10ÿ8_{A cm}ÿ2_{. The}

leakage current of BST thin ®lms was expected to be affected by contact potential barrier and polarization loss. The details were described before [14]. It has also been shown that the dielectric constant and leakage current of BST thin ®lms were dependent on the post-annealing temperature. The BST ®lms deposited on Pt, Ir, IrO2/Ir

and RuO2/Ru after post-annealing were more stable than

BST on Ru. From the viewpoints of the dielectric constant, leakage current and reliability, the optimum material for the bottom electrode with post-annealing is Ir. The details were given in reference [15].

Fig. 10(a) shows the variation of "0_{, "}00_{, and loss tangent}

(tand "0_="00_{) of BST deposited on Pt with frequency in the}

measurement temperature range of 27±1508C. The "0

decreases from a high value at low frequency to a low value at high frequency and the curve has an in¯ective point. The "0 _{becomes a negative value after in¯ective frequency}

because the inductance (Leq) of the equivalent circuit

deter-mined by the conductivity of the electrode dominates. And the "0 _{decreases with increasing temperature before the}

in¯ective frequency because the Curie temperature of BST (Ba/Sr 0.47/0.53) is lower than room temperature. The "00 _{and loss tangent have the same peak values at}

frequencies (!re reÿ1) about 3.89, 3.95, 4.00 and

4.15 MHz, at temperatures 278C, 508C, 108C and 1508C, respectively. The peak frequency (!re), which was reported

to be located near the emission rate of a trap [18,19], increases with increasing temperature. But the dielectric constants ("0 _{and "}00_{) are almost independent of the}

tem-perature and frequency for the frequency range of 100 Hz f 1 MHz, as shown in Fig. 10(b), and the details will be mentioned later.

The conductance Gp of a Schottky junction can be

described as a sum of the shallow trap conductance Gts,

the deep trap conductance Gtd(grain boundary defect and

interface defect) and DC component GDC[18,19],

Gp!; T GDC Gtd! Gts!; T (14)

By applying a small AC signal and varying the tempera-ture, the peak of Gp/! vs. ! or "00vs. ! (Eq. (4)) occurs when

the angular frequency of an AC signal equals the emission rate (en) of electron transition in the trapping state [18,19].

The time dependence of the charge transition is expressed via the relation,

ÿ1

re !re en en0expÿEcÿ Et=kT (15)

where !rethe peak frequency, rethe relaxation time, Ecthe

energy at the bottom of the conduction band, k the Boltz-mann constant, Et the shallow trap level energy. Fig. 11

shows the Gp/! vs. ! of BST/Pt thin ®lm at various

temperatures. The peak frequency (!re) increases with

increasing temperature. On the basis of Eq. (15), the activa-tion energies, (Ecÿ Et), can be obtained from the slopes of

the linear regions of the plots ln(!re) vs. 1000/T (Fig. 12),

respectively, in the BST deposited on Pt, Ir, IrO2/Ir, Ru,

RuO2/Ru, and Ir(6008C) on the basis of the Arrhenius

plot. Fig. 13 depicts the (Ecÿ Et) values of BST deposited

on various bottom electrodes. The measured (Ecÿ Et)

values of Pt(5.14 meV), Ir(4.19 meV), IrO2(5.13 meV),

Fig. 10. Frequency dependence of relative real dielectric constant ("0_{), imaginary dielectric constant ("}00_{) and loss tangent (tan "}00_="0_{) of BST on Pt at}

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Ru(10 meV), RuO2 (5.81 meV) and Ir(6008C)(4.42 meV)

are smaller than the thermal energy (kT) 25.9 meV at 278C. The electrons in the trap states gain suf®cient energy at room temperature and exchange between the conduction band and the shallow trap level. The shallow trap level cannot trap any electrons which can move freely between the conduction band and the shallow trap level. Therefore, the effect of the shallow trap level can be neglected at the normal temperature range of DRAM operation: 0±708C ambient and 0±1008C on chip. From the viewpoint of the trapping phenomena, the contribution of the shallow trap level on the electrical properties of BST thin ®lm would be absent for the frequency range of 100 Hz f 1 MHz, and the details were mentioned later. Hence, we propose that the shallow trap level term is not included in the equivalent circuit of BST thin ®lm in the frequency range of 100 Hz f 1 MHz. The equivalent circuit of BST thin ®lm has contribution from the grain, grain boundary defect and interface defect of BST/metal.

Fig. 14(a)±(c) show the Gp(!,T) and Bp(!,T) of BST thin

®lms deposited on Pt, Ir and Ru with frequency (100 Hz f 1 MHz) at various temperatures. The Gp

and Bpapproach is independent of the temperature, so that

the a(T) and b(T) values can be expressed as a constant at various temperatures, the Cvand Rv can be almost

inde-pendent of the temperature for 100 Hz±1 MHz on the basis of Eqs. (10) and (11). The result is the same with Fig. 10(b). The log(Gp) vs. log(!) curves are almost parallel to the log

(Bp) vs. log(!) curves, from which we can obtain the n

values. Hence, the contribution of the shallow trap level on the electrical properties of BST thin ®lm is absent for the frequency range of 100 Hz f 1 MHz because Cvand Rv

can be almost independent of the temperature. Therefore, the equivalent circuit of BST thin ®lm has contributions only from grain, grain boundary defect and interface defect of BST/metal.

Table 1 lists the related parameters of the equivalent circuit of the plots shown in Figs. 7±9 and 14 at various temperatures. The frequency dependent resistance Rvand

capacitance Cvwere calculated on the basis of Eqs. (10) and

(11). The electrode resistance Rel of various bottom

elec-trodes increases with increasing temperature because metal resistance increases with increasing temperature. The elec-trode resistance Relof Ru has the maximum value because

the Ru electrode may be slightly oxidized during BST deposition at high oxygen ratio, as indicated from XRD and SIMS data [14,15]. As the n values of BST on Pt, Ir, IrO2/Ir, RuO2/Ru and Ir(6008C) approached 1, the measured

Cv except the Ru case will be almost independent of

frequency (100 Hz f 1 MHz), as shown in Fig. 15. The result is same with Fig. 10(b). The n value of BST on Ru is 0.475, the Cvwill decay with increasing frequency

(Fig. 15) and the slope is ÿ0.59 which is about (nÿ1) value. Hence, the BST on Ru has larger dielectric relaxation. The measured Rsof BST deposited on various bottom electrodes

decreases with increasing frequency, as shown in Fig. 16,

Fig. 11. G(!)/! of BST on Pt as a function of frequency at various temperatures.

Fig. 12. An Arrhenius plot of ln(!re) vs. 1000/T of BST deposited on various bottom electrodes for obtaining the trap activation energy (Et).

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Fig. 14. The Gp(!,T) and Bp(!,T) of BST thin films deposited on (a) Pt, (b) Ir and (c) Ru with frequency at various temperatures.

Table 1

Calculated parametric values of the equivalent circuit shown in Figs. 7±9 and 14 at various temperatures extracted from analyses of the Y and Z planes

Bottom electrode Pt Ir IrO2/Ir Ru RuO2/Ru Ir(6008C)

a (S sn_radÿn₎ _{6.26 10}ÿ11 _{9.95 10}ÿ11 _{6.69 10}ÿ11 _{4.26 10}ÿ6 _{1.06 10}ÿ10 _{1.52 10}ÿ10 b (S sn_radÿn₎ _{1.89 10}ÿ9 _{2.51 10}ÿ9 _{1.98 10}ÿ9 _{2.82 10}ÿ6 _{2.34 10}ÿ9 _{5.6 10}ÿ9 n 0.96928 0.96479 0.96715 0.47556 0.97017 0.93861 278C Rel() 12.14 17.98 9.4 83.9 34.4 17.9 (degree) 2.559 3.06 2.96 50.46 2.277 1.75 508C Rel() 13 18.6 9.5 88.4 35.2 18.74 (degree) 2.718 3.06 2.97 50.46 2.277 1.75 1008C Rel() 13.9 19.68 9.6 95.1 36.52 20.47 (degree) 2.719 3.06 2.96 50.47 2.278 1.75 1508C Rel() 15.3 20.6 9.7 102.2 38 22.52 (degree) 2.718 3.06 2.96 50.46 2.279 1.75

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and the slope of BST/Ru is ÿ0.42 which is about ÿn value. On the basis of Eq. (13), the activation energies can be obtained from the slopes of the linear regions of the plots, log(Rs) vs. 1000/T (Fig. 17) for the BST deposited on Pt, Ir,

IrO2/Ir, Ru, RuO2/Ru, and Ir(6008C), respectively, on the

basis of the Arrhenius plot. The values of Rs are almost

independent of the temperature.

The resistance (Req) of the equivalent circuit is

deter-mined by the resistance of the electrode, grain boundary defect and interface defect. The resistance (Req) consists of

contribution from Rvand Rel. Rvis the frequency-dependent

resistance due to grain boundary and interface. The grain boundary defect and the interface defect of BST/metal are considered to be a donor when it becomes neutral or positive by donating an electron. When an AC voltage is applied the

defect levels move up or down with respect to the valence and conductance bands while the Fermi level remains ®xed. A change of charge in the defect occurs when it crosses the Fermi level. The value of Gp/! is C00by Eqs. (10) and (4).

Once C00_{is known (Fig. 3), the defect density is obtained by}

using the relation Ddf C00=qA, where A is the metal plate

area and q the elementary charge [25]. Fig. 18 shows the defect density of grain boundary defect and interface defect of BST deposited on various bottom electrodes. The defect density of BST on Ru is larger than that of other bottom electrodes. Hence the dielectric relaxation of BST on Ru is more serious than those of BST deposited on other bottom electrodes. The results (Fig. 18) have a good agreement with the results shown in Figs. 15 and 16.

The depression angle of a semicircular response in the impedance (Z) and admittance (Y) complex planes is

non-Fig. 15. Capacitance Cvof BST thin films deposited on Pt, Ir, IrO2/Ir, Ru, RuO2/Ru and Ir(6008C) with frequency at room temperature.

Fig. 16. Resistance Rsof BST thin films deposited on Pt, Ir, IrO2/Ir, Ru, RuO2/Ru and Ir(6008C) with frequency at room temperature.

Fig. 17. An Arrhenius plot of Rsvs. 1000/T of BST deposited on various bottom electrodes for obtaining the activation energy.

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zero, which corresponds to the distribution of relaxation time as reported [26] and re¯ects the degree of uniformity in the conductance relaxation. Joncher [27] showed that is related to the extent of the screening effect caused by the hopping charges when it cannot follow the changes of polarization brought about by an alternating electric ®eld. The values of BST of Pt, Ir, IrO2/Ir, Ru, RuO2/Ru and

Ir(6008C) are about 2.7, 3.06, 2.97, 50.46, 2.27 and 1.75 degree, respectively, at various temperatures (Table 1). The value of BST on Ru has the maximum value. That means the BST on Ru has larger loss degree of the material. On the other hand, the value of BST on Ir(6008C) has the minimum value. Therefore, the BST on Ir(6008C) presents smaller screening effect. Taking account of a DRAM appli-cation, the dielectric relaxation would result in less than 10% loss of storage charge during the refresh cycle. From the viewpoints of the dielectric constant, leakage current, trapping phenomena, dielectric relaxation, the depression angle and leakage resistance, the optimum material for the bottom electrode with post-annealing is Ir, because the BST on Ir(6008C) has a large dielectric constant, smaller dielec-tric relaxation and larger leakage resistance, as shown in Figs. 15 and 16.

6. Conclusions

The trapping dielectric relaxation and defect quantity of BST thin ®lms deposited on various bottom electrodes, such as Pt, Ir, IrO2/Ir, Ru, RuO2/Ru before and after annealing

in O2 ambient were explored through the measurement

of dielectric dispersion as a function of frequency (100 Hz f 10 MHz) and temperature (278C T 1508C). An equivalent circuit was proposed on the basis of the admittance and impedance spectra, which can well explain the AC response and identify frequency-dependent resistance on the electrical properties contributed by the defects of BST thin ®lm. A shallow trap level located at 0.005±0.01 eV below the conduction band was observed from the admittance spectral studies in the temperature range of 27±1508C. The grain boundary defect and interface defect existed in the ®lms were the major origin of dielectric relaxation and defect concentration. From the viewpoints of the dielectric constant, leakage current, trapping phenom-ena, dielectric relaxation, and the depression angle, Ir is the optimum material for the bottom electrode with post-annealing.

Acknowledgements

The authors gratefully appreciate the ®nancial support from the National Science Council of ROC under project no. NSC 86-2112-M009-028.

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