Characterization of Highly Strained nFET Device Performance
and Channel Mobility with SMT
Chih-Cheng Lu,zJiun-Jia Huang, Wun-Cheng Luo, Tuo-Hung Hou, and Tan-Fu Lei
Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsin-Chu 300, Taiwan
This paper compares and analyzes the strained negative channel field effect transistor共nFET兲 device performance and the channel mobility behavior obtained by the stress memorization technique共SMT兲 using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current–voltage characteristics, transconductance, carrier mobility, and interface state共Dit兲 are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhance-ment in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations.
© 2010 The Electrochemical Society. 关DOI: 10.1149/1.3416923兴 All rights reserved.
Manuscript submitted December 28, 2009; revised manuscript received February 22, 2010. Published May 5, 2010.
Historically, improvements in the performance of metal-oxide-semiconductor field-effect transistors共MOSFETs兲 have relied on the aggressive reduction of physical geometries as guided by physics-based scaling rules.1However, the increase in channel impurity con-centration and the raise in vertical field required to control the short channel effect共SCE兲 actually degrade the carrier mobility and tran-sistor performance. As the industry approaches the physical limita-tions of the traditional scaling techniques, alternative approaches for improving device performance have become increasingly attractive. Among the most promising of these techniques is the production of high mobility silicon channel structures most commonly accom-plished using strained silicon technology. Strained silicon technol-ogy has emerged as one of the leading approaches to enhance the performance of today’s highly scaled semiconductor devices. This technology has been adopted in production since the 90 nm process node,2and apparently this technology will continue through future generations. The strain can be induced either uniaxially or biaxially and strongly depends on integration challenges and the ability to maintain and control enhancement in aggressively scaled devices.
Many strained silicon approaches have thus been developed to enhance carrier mobility.2-4 Among these emerging approaches, uniaxial strained silicon technologies have become the mainstream for electron and hole mobility improvement especially under high oxide electrical field conditions.3,4For instance, a highly tensile ni-tride capping layer integrated as a contact etch stop layer共CESL兲 has been greatly utilized in advanced MOSFET fabrication owing to the resulting uniaxially tensile mechanical stress created in the nega-tive channel field effect transistor共nFET兲 channel and the resulting electron mobility enhancement.5,6
Another novel channel strain enhancement technique utilizing nitride dielectric deposition, commonly known as stress memoriza-tion technique共SMT兲, was first proposed by Chen et al.7SMT im-proves nFET performance by depositing a sacrificial tensile nitride stressor on top of the nFET poly gate electrode and source–drain 共S/D兲 after the S/D implantation. The nitride layer covers the nFET regions during subsequent dopant activation annealing and is stripped off after the activation annealing has been completed, re-sulting in a higher drive current. The presence of the stress from the SMT nitride capping layer during the S/D activation anneal results in plastic deformation, displacing the silicon atoms in the transistor channel from their equilibrium position. The silicon atoms remain in their new positions after the anneal is complete, in effect “memoriz-ing” the tensile stain in the channel, resulting in nFET device im-provement. Furthermore, when combined with the strained CESL
technique, SMT provides additional strain to the n-channel,8 creat-ing prospects for uscreat-ing strained silicon technology to achieve the device performance targets of aggressively scaled complementary metal oxide semiconductor design rules.
While a detailed understanding of the SMT process remains the subject of active debate, recent works have suggested that the im-proved nFET performance results from the inherently memorized tensile stress in the n-channel by the mechanism described above.7-10 Therefore, to understand and maximize the benefit ob-tained from the highly strained nitride on the silicon channel, SMT strained nFET device performance including threshold voltage共Vt兲, transconductance, electron carrier mobility, and the associated interface-state density Dit, have been characterized by electrical measurement techniques. Moreover, the wafer bowing measure-ments are presented, quantifying the evolution of stress throughout the entire SMT fabrication process.
Experiment and Characterization
The devices were fabricated in the National Nano Device Labo-ratories共NDL兲 on 6 in. 共150 mm兲 Si wafers using a conventional MOSFET process flow including local oxidation of silicon isolation, gate oxide, spacer, S/D implantation, thermal annealing, and Al met-allization processing, as listed in Fig.1. All the nFET devices char-acterized in this study had 3 nm thick gate oxide thermally grown in a vertical furnace and a 150 nm thick N+poly-Si layer as the gate electrode. After gate dielectric and gate electrode deposition and patterning, desired ion species were implanted through a deposited 100 A plasma-enhanced tetraethyl orthosilicate共TEOS兲 screen oxide to form the N+ S/D region. This screen oxide was employed to reduce the N+region junction depth.
Before the S/D activation annealing, an SMT process flow for the strained nFET similar to that proposed by Chen et al.7 was em-ployed. After S/D annealing, a permanent stress was created in the channel region, resulting in strain-enhanced carrier mobility. For the SMT strained nFET nitride capping layer, a⬃110 nm tensile ni-tride film was deposited on the whole device structure including the poly gate and the S/D region. The SMT strain generation obtained from nitride films deposited by two different chemical vapor depo-sition共CVD兲 processes are compared in this study. The first type of nitride film was deposited under a high temperature 780°C 共hereaf-ter denoted as HT-SiN兲 Low Pressure Chemical Vapor Deposition 共LPCVD兲 system using a batch-type furnace tool, and thus the HT-SiN nitride film coated both the front and back sides of the wafer. On the other hand, the second nitride film was deposited at a rela-tively low temperature共hereafter denoted as LT-SiN兲 300°C process condition using a single-wafer plasma-enhanced chemical vapor
z
deposition共PECVD兲 system with NH3, N2, and SiH4as the main reaction gases, thus depositing the LT-SiN nitride film only on the front side of the wafer.
Afterward, to facilitate metallization, the SMT nitride films were removed using a wet chemical etchant H3PO4. Passivation was per-formed by depositing a 300 nm thick TEOS oxide, followed by patterning and etching of contact holes, and finally by metallization. After a completion of the metallization processes, the wafers were annealed at 400°C in a forming gas ambient and the electrical char-acteristics of the fabricated devices were measured. The nominal device dimension evaluated was a gate length of 0.4 m and a width of 10 m. The device characteristics were measured using a semiconductor parameter analyzer 共HP 4156A, plus Agilent ICS software兲. The threshold voltage was determined by the constant drain current method when the drain current equals 10−7 W/L共A兲.11 The linear and saturation mode threshold voltages, Vt_linand Vt_sat, were extracted at drain voltages of 50 mV and 2 V, respectively.
The thicknesses of the LT-SiN and HT-SiN films were measured by a SOPRA ellipsometer. Fourier transformation infrared reflectiv-ity共FTIR兲 spectra were also measured to provide information con-cerning the bonding structure of the SMT nitride films. The FTIR spectra were obtained by subtracting the absorbance obtained before deposition from that measured after deposition using a Bio-Rad QS-300 spectrometer.
Wafer curvatures or bowing measurements were performed using a Tencor FLX-2320 thin-film stress metrology instrument, and film stress was subsequently obtained by transforming this wafer curva-ture using a conversion equation such as Stoney’s formula.12For highly scaled modern semiconductor devices, such wafer level thin-film residual stress characterization is crucial, and the strain level remaining in the device itself is a major factor in determining the final electrical characteristics, yield, and reliability. This curvature measurement technique was also applied to the patterned electrical wafers to characterize the generated SMT strain.
Results and Discussion
Film properties of LT-SiN and HT-SiN.— Generally speaking, compared to LPCVD films, PECVD materials have a much lower thermal budget, and their film properties can be tuned and controlled over a much wider range by varying appropriate process parameters. In this work, the LT-SiN is formed at 300°C by PECVD with a
mixed gas containing SiH4, NH3, and N2, while the HT-SiN is formed at 780°C in an LPCVD furnace with a mixed gas containing SiH2Cl2and NH3.
TableI depicts the LT-SiN and HT-SiN nitride film thicknesses before and after S/D annealing. The typical as-deposited nitride thicknesses共measured on unpatterned monitor wafers兲 were ⬃1150 and⬃1100 A for LT-SiN and HT-SiN, respectively. However, after annealing, the thicknesses of both nitride films reduced to ⬃1050 A. The calculated thickness shrinkage rate after annealing for the LT-SiN is⬃12% compared to ⬃3% for that of the HT-SiN. For strain nitride for CESL application,5,6the magnitude of the thin nitride film stress is one of the key properties that can determine the device performance and reliability lifetime. The deposition tool and process parameters largely determine the type and level of ni-tride stress that develops on the wafer. Because of its simplistic nature, the curvature measurement scheme is traditionally the most widely acknowledged method, and the film stress is determined by converting the measured curvatures using Stoney’s equation,12 as formulated in Eq.1. A highly stressed film causes wafer deforma-tion, as schematically drawn in Fig.2
= E 6共1 − 兲 ts2 tf
冉
1 R1 − 1 R2冊
关1兴 where is the film normal stress, E is the elastic modulus of the substrate, tsis the substrate thickness, tfis the film thickness, is Poisson’s ratio of the substrate, and共1/R1− 1/R2兲 is the local cur-vature caused by intrinsic stress before and after film deposition.SMT nitride stress and stress change behavior before and after annealing are measured and shown in TableII. All stress levels are positive, indicating tensile stress. The LT-SiN shows a relatively large increase in tensile stress⬃700 MPa 共360–1050 MPa兲, while the HT-SiN shows a much smaller 60 MPa stress increase共1010– 1070 MPa兲.
The representative SiN layer FTIR spectra after CVD deposition and after S/D annealing are shown in Fig. 3. The FTIR analysis results obtained on LT-SiN and HT-SiN films are shown in Fig.3a andb, respectively. The chemical bonding present in CVD deposited nitrides has been characterized by FTIR according to Lu et al.13The dominant spectral feature in each film is at approximately Device LOCOS Isolation
Gate Define LDD Implantation Spacer
S/D Implantation
SMT SiN Dep (Strained LT-SiN or HT-SiN) S/D Annealing for Dopant Activation SMT SiN Removal Al Metalization SMT SiN Poly Gate Spacer
Figure 1. 共Color online兲 SMT process flow. The SMT process deposits a nitride layer over the gate before annealing. The presence of this nitride layer during the subsequent S/D annealing acts to increase tensile strain in the nFET channel. Though this SMT nitride is removed after the annealing, the stress memorized in the channel region remains, and mobility of electrons increases.
Table I. Measured nitride thickness and associated thickness shrinkage rate (%) before and after S/D activation annealing. Thickness
共A兲 LT-SiN HT-SiN
As deposited 1163 1075 After annealing 1028 1044 Thickness shrinkage共%兲 11.6 2.9 Bow R R R R tf ts tf ts rr
Figure 2. 共Color online兲 Bow is characterized in terms of the curvature of the substrate, which is the height difference between the center and the edge of the wafer resulting from the wafer manufacturing process or the presence of a residually stressed thin film on one side of the wafer. In Fig.2, the film is under positive共tensile兲 stress, and the R 共radius of curvature兲 is positive. Therefore, the bow is also positive according to Eq.2.
820–850 cm−1 and is associated with the Si–N asymmetric bond-stretching mode. The remaining features in these spectra are due to vibrations involving hydrogen atom motion: 共i兲 a N–H bond-stretching mode at⬃3350 cm−1,共ii兲 a N–H bond-bending mode at ⬃1150 cm−1, and 共iii兲 a Si–H bond-stretching mode at ⬃2150 cm−1, respectively.
The as-deposited LT-SiN spectrum of Fig.3ashows substantially stronger Si–H and N–H bonds compared with the as-deposited HT-SiN spectrum of Fig.3b. This results from the higher deposition temperature of the LPCVD process. Hydrogen atom is more mobile and active and less likely to remain in a stable Si–H or N–H bond. The FTIR spectra for nitrides with LT-SiN and HT-SiN after S/D annealing are also shown in Fig.3aandb, respectively. We observe that the intensities of the Si–H and N–H bond peaks become negli-gible after annealing, suggesting hydrogen removal during the S/D activation anneal.
The change is much more dramatic in LT-SiN because of the large amount of hydrogen initially incorporated during the
deposi-tion of the PECVD film. The magnitude of the reducdeposi-tion in hydro-gen content is directly responsible for the irreversible increase in the tensile stress of the film due to the volume reduction, as reported by Hughey and Cook.14-16As observed in Fig. 3a, the FTIR spectra show a reduction of the N–H and Si–H bond peaks, which agrees with this scenario. This phenomenon is typical of the LT-SiN formed by PECVD and is well correlated with the LT-SiN film’s massive stress change toward a tensile equilibrium state after hydrogen re-moval, as shown in TableII. Apparently, the smaller stress change observed in TableIIfor the HT-SiN layer is mainly due to less initial hydrogen concentration during nitride layer deposition and less hy-drogen bonding change, as indicated by the FTIR spectra in Fig.3b. Device wafer bow measurement.— Wafer bowing refers to the curvature of the wafer substrate, i.e., the height difference between the center and the edge of the wafer. A graphical description of wafer bow is shown in Fig.2and formulated in Eq.2
Bow =共兩R兩 −
冑
R2− r2兲sign共R兲 关2兴 where R is the radius of curvature and r is the scan distance.When applying strain silicon technology to increase carrier mo-bility, wafer bow is a key metrology item for chipmakers as they transition to production on 300 or 450 mm wafer sizes because larger wafers can bow, or bend, more than twice as much as the 150 mm wafers used here on the deposition of a given film. The larger global wafer bow accumulates larger stress on the wafer and in-creases the device’s susceptibility to film cracking, delamination, and electrical performance degradation, which would all negatively impact transistor structural integrity and can result in serious circuit yield loss.
Wafer bow can be modulated by the presence of a stressed thin film deposited on the wafer. Therefore, wafer bow is a quantitative index for the bending共curvature兲 of a wafer during the device fab-rication processes. For instance, wafer bow due to electroplated cop-per films with different copcop-per seed layers has been studied.17 Fur-thermore, previous observations by Yu et al.18have also revealed a correlation between the wafer bow height and defect injection into strained epitaxial SiGe upon activation laser and rapid thermal an-nealing共RTA兲 annealing. This study further indicates that the final wafer curvature was determined by the initial shape of the wafer plus the deformation caused by the subsequent fabrication pro-cesses.
To successfully apply SMT technology, it is essential to utilize wafer bow measurement to understand the SMT strain behavior and to minimize the SMT strain induced defect creation and/or strain relaxation after annealing when large SMT strain is present. Because any wafer has some initial curvature and surface irregularities are caused by several front–end processing steps occurring before SMT, a curvature measurement was performed before the deposition of the SMT capping nitride film. Further curvature measurements were performed after each of the subsequent SMT process steps such as nitride film deposition, RTA for S/D annealing, and nitride strip. These data were compared to the initial curvature. Figure4plots the increased wafer bow at each SMT process step and demonstrates that wafer curvature represents the SMT strain generated in the fab-ricated silicon device. The LT-SiN SMT film stress causes signifi-cantly higher levels of curvature in device wafers after SMT depo-sition and the subsequent S/D activation annealing. It indicates that wafers processed with SMT using LT-SiN are significantly warped compared to those processed with HT-SiN. This is likely because HT-SiN is processed with a double-sided coating furnace batch sys-tem, so the stress from the HT-SiN films on the front and back sides of the wafer cancel each other out to produce much less macro-scopic wafer bending. This does not imply that there is no SMT strain generated by HT-SiN. However, with SMT processing using LT-SiN, the wafer bow is increased further after S/D activation an-nealing due to the large increase in film stress reported in TableII. Recrystallization of amorphized silicon upon thermal annealing leads to strain and stress generation in the silicon material itself.19-22 Table II. Measured nitride stress variation before and after S/D
activation annealing. Stress
共MPa兲 LT-SiN HT-SiN
As deposited 360 1010 After annealing 1050 1070 Delta stress 690 60 $ EV RUE DQF H DX $ EV RUE DQF H DX $ EV RUE DQF H DX $ EV RUE DQF H DX $V 'HSRVLWHG /76L1 $V 'HSRVLWHG /76L1$V 'HSRVLWHG /76L1 $V 'HSRVLWHG /76L1 /76L1 $QQHDOOLQJ /76L1 $QQHDOOLQJ/76L1 $QQHDOOLQJ /76L1 $QQHDOOLQJ 6L+ 6L+ 6L+ 6L+ 1+ 1+ 1+ 1+ 6L1 6L16L1 6L1 1+ 1+1+ 1+ :DYHQXPEHU FP :DYHQXPEHU FP :DYHQXPEHU FP :DYHQXPEHU FP (a) :DYHQXPEHU FP :DYHQXPEHU FP :DYHQXPEHU FP :DYHQXPEHU FP $ EV RUED QF H DX $ EV RUED QF H DX $ EV RUED QF H DX $ EV RUED QF H DX $V 'HSRVLWHG +76L1 $V 'HSRVLWHG +76L1 $V 'HSRVLWHG +76L1 $V 'HSRVLWHG +76L1 +76L1 $QQHDOOLQJ +76L1 $QQHDOOLQJ +76L1 $QQHDOOLQJ +76L1 $QQHDOOLQJ 6L+ 6L+ 6L+ 6L+ 1+ 1+1+ 1+ 6L1 6L16L1 6L1 1+ 1+ 1+ 1+ (b)
Figure 3. 共Color online兲 共a兲 LT-SiN film FTIR analysis results before and after S/D activation annealing. FTIR spectra indicated features associated with13共i兲 the Si–N asymmetric bond-stretching vibration at 820–850 cm−1 and共ii兲 the bond-bending vibration of the N–H group at ⬃1150 cm−1,共iii兲 the bond-stretching vibration of the Si–H group at⬃2150 cm−1, and共iv兲 the bond-stretching vibration of the N–H group at⬃3350 cm−1. 共b兲 HT-SiN film FTIR analysis results before and after S/D activation annealing. HT-SiN sample contains much less Si–H and N–H bonds than those of LT-SiN samples in共a兲.
Because the transistor’s poly-silicon gate and the S/D region were all amorphorized after high dosage S/D implantation, this increased tensile wafer curvature after annealing is likely to result from the SMT capping nitride film stress change and the strain exerted by the recrystallization of the amorphized S/D regions upon S/D activation annealing. Nevertheless, wafer warpage continues to exist even after the SMT nitride is subsequently removed, both for wafers processed with SMT by LT-SiN and for those with HT-SiN. This can be viewed as the generation of the SMT strain, which remains present in the wafer after completing the SMT process. Moreover, as the electron mobility in the channel can be increased by tensile strain in the in-plane longitudinal direction and by compressive strain in the out-of-plane vertical direction according to the piezoresistance model,2,4,23 this “memorized” SMT strain in the poly-Si gate and S/D region can thus enhance the electron mobility and the nFET drive current.7-10
nFET device mobility and SCE characterization.— In addition to the enhanced wafer curvature exerted by the memorized strain, as shown in Fig.4, electrical characterization was preformed to study the impact of SMT on nFET device共W/L = 10/0.4 m兲 transcon-ductance and mobility. Figure 5plots the linear transconductance Gm_linimprovement resulting from the HT-SiN SMT process. Com-pared to LT-SiN process, a maximum Gm_linenhancement of around 13% under a drain voltage of 50 mV is obtained. The nFET field-effect electron mobility, measured at a drain voltage of 50 mV by the conventional split capacitance–voltage 共C-V兲 method,24 is shown in Fig.6. The maximum field-effect electron mobilities are 292 and 264 cm2/V s, respectively, in these two samples. Similar
to the findings in Fig.5, the field effective mobility of the device with the HT-SiN SMT is also over 10% higher than the one of the device integrating LT-SiN. In Fig.5and6, there is an obvious trans-conductance and carrier mobility improvement when HT-SiN is used as an SMT layer. These results clearly suggest that the HT-SiN SMT process induces a higher permanent stress in the channel re-gion, and the electron mobility is thus enhanced after completing S/D annealing. Thus, it can also be concluded from this work that the “optimized” SMT process can further enhance nFET carrier mo-bility and device performance, as previously reported.7,9,10The re-tained transconductance Gm_linand mobility improvement, even af-ter the removal of the stressor film, can be attributed to a stress “memorization” effect.
The linear and saturation threshold voltages共Vt_linand Vt_sat兲 are plotted as a function of channel length in Fig. 7. Regarding SCE control, neither HT-SiN nor LT-SiN films demonstrate a significant nFET Vtroll-off from a long channel共L = 10 m兲 down to a short channel 共L = 0.4 m兲, which indicates that processing with the capped SMT nitride improves nFET SCE performance by retarding n-type dopant diffusion upon subsequent activation annealing.8 Moreover, drain induced barrier lowering共DIBL兲 can be calculated from Eq.3as the threshold voltage difference between linear and saturation modes, divided by the difference in the applied drain volt-age -1 0 1 2 3 4 5 6 7
Pre SMT After SMT SiN Dep
After Annealing
After SiN Strip
In cr eas ed W a fe r Bo w (µµµµ m) LT-SiN HT-SiN
Figure 4. 共Color online兲 Increased device wafer bow height measured on patterned wafers at different SMT stages to evaluate the SMT strain behav-ior. nFET W/L=10/0.4µµµµm 0 100 200 300 400 500 600 0 0.2 0.4 0.6 0.8 1
Gate Overdrive Vg-Vt(Volt)
Tr a ns c ond uc ta n c e (µµµµ S ) HT-SiN, Vd=50mV LT-SiN, Vd=50mV +13%
Figure 5. 共Color online兲 Measured 10 ⫻ 0.4 m nFET Gm_lin at Vd = 50 mV. There is an⬃13% improvement in the peak value of Gm_linwith the adoption of HT-SiN as the SMT capping layer.
150 170 190 210 230 250 270 290 310 0.2 0.6 1 1.4 1.8 2.2 2.6 3 Eeff(MV/cm) Mo b il it y (cm 2/V -s e c ) HT-SiN LT-SiN +11%
Figure 6. 共Color online兲 Measured 10 ⫻ 0.4 m nFET mobility at Vd = 50 mV. There is an⬃11% improvement in the peak value of electron mobility with the adoption of HT-SiN as the SMT capping layer.
0.35 0.4 0.45 0.5 0.55 0.6 0.1 1 10
nFET Gate Length (µµµµm), W=10µµµµm
Th re s h ol d V ol ta ge Vt (V o lt) HT-SiN Vt_lin HT-SiN Vt_sat LT-SiN Vt_lin LT-SiN Vt_sat Vt_linearextracted at Vd=50mV Vt_satextracted at Vd=2V
Gap is less than 15mV
Gap is less than 25mV
Figure 7. 共Color online兲 Measured W = 10 m nFET Vt as a function of channel length; LT-SiN as SMT capping layer improves nFET SCE with less Vtroll-off.
DIBL =⌬Vt/⌬Vds= 1000*共Vtlin− Vtsat兲/共2 − 0.05兲 共mV/V兲 关3兴 The calculated DIBL is plotted as a function of channel length in Fig.8. DIBL reflects the influence of the drain voltage on the carrier potential in the channel.25The slightly increased DIBL by HT-SiN observed in Fig.8 can be attributed to increased dopant diffusion encroaching from the S/D extension during the deposition of HT-SiN due to its higher deposition temperature. Therefore, to lower the DIBL and improve the SCE performance, a lowered thermal budget process is always preferred to suppress dopant diffusion.
A large shift in the threshold voltage Vt can often indicate a change in the device’s dopant distribution profile or the generation of bulk traps or interface states11due to unoptimized stressor pro-cessing techniques, which can adversely impact device performance without strain engineering benefits. However, from the threshold voltage data in Fig.7, the linear threshold voltage共Vt_lin兲 difference between wafers processed by the HT-SiN and LT-SiN SMT pro-cesses is less than 15 mV, and the saturation threshold voltage 共Vt_sat兲 difference is also less than 25 m V. Such small Vt_lin and Vt_satdifferences between HT-SiN and LT-SiN SMT processes sug-gest that the enhanced thermal budget by the furnace deposition system does not significantly deteriorate S/D dopant distribution in the transistor itself.
Interface-state Dit characterization by high–low C-V measure-ment.— As predicted by Matthiessen’s rule in Eq. 4,26 there are several key factors that contribute to the carrier transport mobility variation. The interface state is a major factor influencing inversion channel electron mobility, in which the maximum mobility depends on the interface-state density
1 effective = 1 lattice + 1 impurity + 1 Dit + 1 surface_roughness 关4兴 Therefore, the high–low C-V technique27is utilized to characterize the density of interface traps Dit. The measured Ditresults in Fig.9 indicate that the interface quality deteriorated with LT-SiN when the trap energy range共EC− E兲 is greater than 0.25 eV, where ECis the energy of the conduction band edge and E is the interface-state energy. At the same time, the LT-SiN and HT-SiN SMT processes have comparable Toxvalues, extracted from C-V analyses, and simi-lar threshold voltage values, as previously shown in Fig.7. As the MOSFET parameters are related through interface states and oxide traps near the interface, the increased interface trap Ditgenerated at the oxide/silicon substrate interface under inversion mode, as shown in Fig.9, can lead to the reduced transconductance in Fig.5and the lowered electron mobility in Fig.6. Therefore, to further improve the nFET device performance, the SMT process should be optimized with respect to these parameters.
Relevance of SiN film properties on electrical measurement re-sults.— As shown in Fig.9, when the double-sided HT-SiN was utilized as the SMT capping layer, it reduced the density of interface states. Hence, both the nFET transconductance in Fig. 5 and the electron mobility in Fig.6were improved. Thus, interfacial quality degradation must be considered with the adoption of advanced ni-tride films in pursuing performance gain for SMT technology.
Intrinsic stress results from the microstructure created in thin films when the atoms of these thin films are deposited on the sub-strate via various kinds of deposition tool and processes. Thus, the thin film’s formation process environment, deposition rate, and im-purities determine the sign and magnitude of the residual stress in the silicon substrate and, more specifically, in the silicon devices fabricated. As the LT-SiN is formed by a PECVD technique at a low temperature, it incorporates a higher hydrogen concentration com-pared to HT-SiN.13,14The resulting LT-SiN nitride layer has substan-tially higher Si–H and N–H bonding concentrations compared with an HT-SiN nitride layer formed at a high temperature, resulting in a larger stress increase after annealing.14Moreover, the higher tem-perature condition in a furnace system used to fabricate HT-SiN can help to passivate the dangling bonds at the interface. Thus, a lower Ditlevel can be achieved by HT-SiN compared to that formed by LT-SiN.
From the physical property point of view, the HT-SiN nitride is thermally stable because the layer is formed with less hydrogen bonding, as evidenced in Fig.3b, exhibits little thermal stress varia-tion, as shown in Table II, and shows lower thickness shrinkage upon annealing, as shown in TableI. At the same time, HT-SiN is deposited on both the front and back sides of the wafer, and thus the stress changes from the two sides of the wafer cancel each other out. Therefore, wafer bowing can also be suppressed, with less curvature induced after S/D RTA, as shown in Fig.4. Such unique physical properties prevent the cracking phenomena and reduce the stress applied to the underlying layer, and less gate edge damage during the SMT formation process can be expected, as illustrated in Fig.10. Moreover, from the chemical property point of view, the forma-tion of N–H bonds is more desirable than that of Si–H bonds as less hydrogen atoms evolved from the higher temperature nitride upon thermal annealing. This is because the bonding strength of N–H共4.7 eV兲 is larger than that of Si–H 共3.9 eV兲,28and Si–H is more likely to release hydrogen after bond breakage compared to a N–H bond. In this respect, Yamamura et al. also confirmed that their novel strained CESL SiN, with a reduced amount of unstable Si–H bonds and incorporating more stable N–H bonds, is able to improve gate oxide interface quality and NBTI performance.29
It has been reported that excess released hydrogen can lead to 0 10 20 30 40 50 60 0.1 1 10
nFET Gate Length (µµµµm), W=10µµµµm
DI B L (m V /V) HT-SiN LT-SiN
Figure 8.共Color online兲 Calculated W = 10 m nFET DIBL. Slightly im-proved DIBL at reduced gate length nFET devices can be observed with LT-SiN as the SMT capping layer.
1.0E+10 1.0E+11 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 EC-E (eV) Dit (# /c m -2 eV -1 ) Dit HT-SiN Dit LT-SiN W/L = 50/50µµµµm Cit= (1/CLF- 1/Cox) -1 - (1/CHF- 1/Cox) -1 Dit= Cit/ q
Figure 9.共Color online兲 Measured interface-state density 共Dit兲 characteris-tics as a function of trap energy near the conduction band edge using 50 m square MOS capacitors by high–low C-V technique.27The interfacial quality is degraded with the adoption of LT-SiN as the SMT capping layer when trap energy range共EC− E兲 is greater than 0.25 eV, where ECis the energy of the conduction band edge and E is the interface-state energy.
Si/SiO2interface quality degradation Dit.30-33Hydrogen plays a cru-cial role in the fabrication of high quality Si/SiO2 interfaces in MOSFET electronic devices in that the interface-state buildup at the device’s substrate/oxide interface is highly related to the transport of atomic hydrogen during its fabrication, and suppression of hydrogen transport aids in improving the electrical integrity of devices.30,31 Because hydrogen is always present in the oxides of these transis-tors, the interface is unavoidably exposed to the hydrogen depassi-vation process. As hydrogen atoms impinge on the Si共111兲/SiO2 interface to depassivate the Si–H bond, the dangling Si bond and resulting interface traps can thus be formed via the chemical reac-tion in Eq.5shown below32,33
Si − H + H→ Si • + H2 关5兴
For the SMT application here, the hydrogen concentration evolved from the SMT nitride can also influence the interface quality. Be-cause the HT-SiN film incorporates less hydrogen and creates fewer Si–H bonds, it is much more compositionally stable. Less hydrogen is released upon annealing, as shown by the FTIR spectra in Fig.3b, and less interfacial degradation is obtained共Fig.9兲. The mechanism responsible for this improvement is illustrated schematically in Fig. 10a. On the contrary, LT-SiN involves large quantities of hydrogen, which will be released upon annealing, as confirmed by the FTIR in Fig.3a. Because the gate oxide quality at the gate edge has already been weakened by the mechanical stress exerted by the wafer bow due to the LT-SiN film’s stress increase upon thermal annealing, as illustrated in Fig.10b, the interface is especially vulnerable to hy-drogen attack with hyhy-drogen diffusion paths though the poly gate, spacer, and S/D region 共Fig.10b兲, resulting in a higher Dit level 共Fig.9兲.
Conclusion
In this paper, the SMT strain silicon technique has been experi-mentally studied for two different nitride films with respect to film stress, wafer curvature, nFET device performance, transconduc-tance, and mobility. Moreover, the influence of interface states on the characteristics of nFET devices and the associated electron mo-bility behavior with these two different kinds of capping nitrides have also been quantitatively analyzed.
In this study, nFET Vtand DIBL have a similar level when using HT-SiN or LT-SiN for SMT application. Nevertheless, nFET devices with higher device performance, carrier mobility, and lowered interface-state density can be fabricated by the HT-SiN as the SMT capping nitride. The lowered Dit level achieved by HT-SiN as the SMT capping nitride is likely because共i兲 HT-SiN has less hydrogen
in nitride itself,共ii兲 HT-SiN is more thermally stable with low thick-ness shrinkage and its stress is stable upon S/D annealing, and thus 共iii兲 less wafer curvature is induced to suppress gate edge damage.
It is generally but not always true that a higher stress film depos-ited onto the transistor can produce a high mobility channel, nor is it always guaranteed that an improved device performance can be ob-tained with such a higher film stress when adopting strain silicon technology. This is because that excess force may lead to stress relaxation, permanent wafer deformation, or transistor structural damage. Furthermore, interface-state degradation must be balanced with the adoption of advanced nitride films for SMT in pursuing further nFET performance gain.
Acknowledgment
The authors thank all the team members in the NDL for their excellent support of device fabrication and electrical characteriza-tion and for many stimulating technical discussions.
National Chiao Tung University assisted in meeting the publication costs of this article.
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Figure 10.共Color online兲 共a兲 Top and 共b兲 bottom. Schematic illustration of wafer bending inducing gate edge damage and interfacial quality deteriora-tion due to high stress change in the SMT capping nitride in共b兲.
