A Low-Cost Jitter Measurement Technique for BIST Applications

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A Low-Cost Jitter Measurement Technique for BIST Applications

∗

Jui-Jer Huang, and Jiun-Lang Huang

Graduate Institute of Electronics Engineering / Department of Electrical Engineering

National Taiwan University

Taipei 106, Taiwan

Abstract

In this paper, we present a technique to measure the RMS period jitter of the signal under test. In the proposed ap-proach, the lead/lag relationships between the signal under test and two delayed versions of itself are compared. The collected information corresponds to two points along the jitter’s cumulative distribution function (CDF) curve from which the RMS period jitter value can be derived. Cur-rently, SPICE simulation results show less than 5% error for RMS jitter values ranging from 40 to 60 ps.

1. Introduction

Measuring high-speed clock jitters is a difﬁcult task. It usually relies on expensive ATE (automatic test equipment) and can easily consume long test time. Furthermore, the situation is getting worse as the trend of system integration onto a single chip continues. One promising solution to al-leviate these problems is built-in self-test (BIST). Since on-chip BIST circuitry can be made close to the signal sources under test, accessing embedded signals becomes much eas-ier and not limited by the bandwidth of the I/O pins. The main concern of BIST is the incurred area/performance overhead and the achievable test accuracy.

Many research efforts have been devoted to jitter testing. In [5], the authors employ a variable delay line to record the 15.9% and 84.1% points of the jitter’s cumulative dis-tribution function (CDF) curve from which the RMS jitter value can be derived. (The jitter is assumed to be a gaus-sian random variable.) The main advantage is that the BIST circuit is fully digital. The main limitation, on the other hand, is that the measurable jitter is limited by the gate de-lay available in the IC technology. High-resolution time-to-digital techniques can also be used for jitter measurement. For example, the work in [3] achieves high-resolution jit-ter measurement with a vernier delay line. The drawback ∗_{This work was partially supported by the National Science Council of}

Taiwan, R.O.C., under Grant No. NSC91-2215-E-002-040.

is the large hardware overhead and the stringent delay line linearity requirement. In [8] and [7], an analytic signal method to extract peak-to-peak and RMS jitter is proposed and validated with commercial processors. The technique can reduce the test time signiﬁcantly, but is not suitable for BIST applications. The method is further extended in [9]. In [2], the authors propose to use the jittery signal as the clock signal to an ADC which samples a sinusoidal signal. This way, the jitter information can be extracted from the ADC outputs. The technique reported in [1] intends to solve the linearity problem in [3] by using a component-invariant vernier delay line. The main limitation is the associated long test time. To resolve this problem, the authors also propose a test time reduction method at the expense of more hardware. In [6], the authors solve the delay line linearity problem by characterizing the non-linearity and incorporat-ing this information durincorporat-ing the analysis phase, which may lead to long test time.

In this paper, we propose an RMS period jitter measure-ment technique for BIST applications. Assuming that the jitter is a gaussian random variable, RMS jitter is charac-terized by comparing the phase relationships (lead or lag) between the signal under test and two delay versions of it-self. This way, two points on the jitter’s CDF curve are obtained from which the RMS jitter value is derived. The proposed jitter measurement circuitry is quite simple. It consists mainly of a variable delay with two delay values, a sense-ampliﬁer based phase comparator, and an inverter for delay measurement. Currently, SPICE simulation shows promising results: an average error of less than 5% for 40-50 ps RMS jitter. We will implement a prototype chip to further validate the proposed technique.

This paper is organized as follows. In Section 2, we introduce the proposed technique, including the basic idea and the corresponding circuit implementation. In Section 3 we will present the simulation results. Implementation is-sues are discussed in Section 4, and we conclude this paper in Section 5.

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A B A' d 1 0.5 S S' d T

Figure 1. The basic idea.

2. The proposed technique

Assuming that the period jitter associated with the signal under test is a gaussian random variable, the objective of the proposed technique is to derive the period jitter’s RMS value. (The gaussian distribution assumption is in general true for a mature design.) In the following discussion, for convenience, the term “jitter” will correspond to “period jit-ter.”

2.1. The basic idea

Denote byS the signal under test, and J the associated jitter. To obtain the statistical information ofJ, our idea is to compare the phase relationships (lead or lag) betweenS and two delayed versions of itself. For each delay amount, the probability that S leads depends on two factors: the amount of delay andJ. In fact, as will be seen later, the two probabilities correspond to two points on J’s CDF curve, from whichRM SJ, the RMS value ofJ, can be derived.

In Fig. 1,S is the signal under test, Sis a delayed ver-sion ofS by d, and A, B, A are all rising edges. (A cor-responds toA delayed by d.) Clearly, if S is jitter free, then the phase relationship betweenAandB depends sorely on the value ofd, i.e., Awill always lead/lagB if d is chosen to be less/greater thanT , the ideal period of S.

However, in the existence ofJ, B will deviate from its ideal position (relative to A). As a result, the relationship betweenA andB is no longer invariant—B may lead or lagAdepending on the jitter value associated with the pe-riod[A, B]. The probability p that B leads Ais a function ofd and RM SJ(J is assumed to be gaussian). This can be seen from the CDF curve (top of Fig. 1). For example,ifd equalsT , p will be 0.5, and as d increases/decreases, p ap-proaches one/zero. Also, whenRM SJincreases, the CDF curve becomes ﬂatter andp increases for d < T and de-creases ford > T .

In the proposed technique, this probability is measured

twice for two different values of d. From the two prob-abilities and the difference of the two d’s, RM SJ can be derived.

2.2. Deriving the RMS jitter value

Letd1andd2be the two delays we use, andp1andp2

the measured probabilities. d1,d2and the jitter values,j1

andj2, they map to on the jitter’s CDF curve satisfy the following relationship:

ji= di− T

Knowing∆d = d₁− d₂, p1, andp2, RM SJ can be derived in the following way. (Note that actual values ofd1

andd2need not be known.)

1. Solve for x1 andx2 that satisfy FX(x1) = p1 and

FX(x2) = p2whereFX(x) is the normalized gaus-sian CDF.

2. Since∆j = ∆d, RMS_J= _x∆d

1−x2.

BecauseFX(x) has no known closed-form solution, x1

andx2may be obtained by using a lookup table or the ap-proximation function which is due to Brjesson and Sund-berg, 1979 [4]. The maximum absolute error in the approx-imation is given as 0.27% for anyx ≥ 0. In BIST applica-tions, if on-chip resources are insufﬁcient for such compli-cated computation, one may rely on external ATE to solve forx1andx2. It should be noted that the choices ofj1and

j2values affect the achievable measurement accuracy.

To determine the properj1andj2values, Matlab

simu-lations are performed for different combinations ofj1and

j2. Based on the results, we choose j1 = −RMSJ and j2 = RMSJwhich correspond tod1 = T − RMSJ, and d2= T + RMSJ. The Matlab simulation results also show that, for 1 GHz signal, the allowable deviations ofd1andd2

are about 100 ps for 5% measurement error. The allowable deviations increase if one increases the numbers of phase comparisons.

In [5], the authors also derive the RMS jitter value from the CDF curve. Compared to their method, ours only need to sample two points along the distribution function curve. This way, the jitter measurement circuit can be made sim-pler; however, it also incurs higher post-processing efforts, i.e., solving the inverse of the normalized CDF.

2.3. The BIST circuitry implementation

The proposed jitter measurement circuitry is shown in Fig. 2. The main components are:

Variable delay d. The variable delay d has two different

delay values,d1andd2, controlled by the signal

“de-lay ctrl.”

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Signal under test, S ⼾@N ⼾@D ⼾@D Phase comparator to counter to counter delay_ctrl variable delay d S' S

Figure 2. The proposed BIST circuitry.

Inverter. In the calibration mode, the inverter together with

the variable delay forms a ring oscillator whose oscil-lation period can be measured using a counter.

Phase comparator. The phase comparator determines

whether the rising edge ofS leads or lags that of S. Its output is high ifS leads S, and low otherwise.

Counter. The counter serves two purposes. During the

cal-ibration mode, it facilitates the measurement of ∆d. During the measurement mode, it keeps track of the number of timesS leads Safter a number of compar-isons.

Control switches. The control switches are properly

opened or closed to set the BIST circuitry into different operation modes.

2.4. The BIST circuitry operation modes

The BIST circuitry has two operation modes: the cali-bration mode and the measurement mode.

Calibration mode. In the calibration mode,φmis low and φc is high. This way, the inverter together with the variable delay forms a ring oscillator. Let the inverter delay bedinv. The “delay ctrl” signal is set to low and high to measure the corresponding oscillation periods (d1+ dinv) and (d2+ dinv), respectively. Thus, ∆d is simply the difference of the two measurements.

Measurement mode. In the measurement mode, φm is high andφc is low. The phases ofS and Sare com-pared N times for low and high “delay ctrl” values, and the number of times S leads S, denoted by n1

andn2 respectively, are counted and stored for later

analysis.

2.5. The measurement ﬂow

The jitter measurement ﬂow consists of the two BIST cir-cuitry modes and a following analysis phase. In the analysis

phase,∆d, p₁, andp2are ﬁrst derived:

∆d = (d1+ dinv) − (d2+ dinv) , and p1= n1

N, p2= n2

N

x1andx2are then derived using the approximation func-tion. Finally,RM SJis computed:

RM SJ= ∆d x1− x2

3. Experimental results

3.1. Simulation setup

Currently, we have validated the method using SPICE simulation. (We are working on the hardware validation part.) As we have mentioned in Sec. 2.2, the value of∆d and positions of ji’s must be carefully selected to ensure high accuracy. In this experiment, the signal under test is a 1 GHz clock signal (whose rise and fall times are both 150 ps), and we choose 40 ps as the target RMS jitter value. Thus, the design goals of the variable delay are:

d1= T − RMSJ= 960 ps d2= T + RMSJ= 1, 040 ps

N is set to 1000. Thus, a total of 2,000 phase comparisons are made.

3.2. Simulation results

In the calibration mode, the measured(d1+ dinv) and (d2+ dinv) values are 1,152 ps and 1,230 ps, respectively. Thus, we have∆d = 78.7 ps which is quite close to desired value of 80 ps and the SPICE measurement result 76.74 ps. The simulation results for different RMS jitter values are shown in Table 1. In Table 1, the ﬁrst column lists the injected RMS jitter values, the second and third columns are n1 and n2 respectively, the fourth column is ∆x =

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Table 1. Simulation Results Error RMS jjitter (ps) n1 n2 ∆x Result (ps) ps % 30 99 866 2.395 32.8601 2.8601 9.53 40 154 813 1.9084 41.2387 1.2387 3.10 50 204 775 1.5828 49.7220 0.2780 0.56 60 239 712 1.2688 62.0271 2.027 3.38 70 293 684 1.0237 76.8780 6.878 9.82

(x1− x2), and the last two columns are the absolute and

relative errors. From then1andn2values, we can see that

d1andd2are not symmetric about 1,000 ps. The RMS jitter

measurement errors are within 5% for 40–60 ps RMS jitter.

4. Discussion

Both the Matlab and the spice simulation results show that the measurement errors of this technique increase if the actual RMS jitter value is far away from the target value, which seems to be a limitation. (Recall that the choices of d1andd2 depend on the target RMS jitter value.) Indeed,

this makes the proposed technique unsuitable for charac-terization testing. However, the technique can work well in pass/fail testing if one uses the jitter specification as the target RMS jitter value. This way, the accurate measure-ment around the test specification reduces the chance of mis-classifying devices close to the specification. On the other hand, for devices well above or below the test specifi-cation, the measurement error is small enough so that they won’t be mis-classified, either.

Deviations ofd1 andd2 from their desired values due to process and/or temperature variation can also lead to test inaccuracies. To solve this problem, we may modify the variable delay so that it has more than two different delay values. This way, if only two of the delay values are close to the desired values, the test accuracy can be ensured. (The quality of a delay value is judged by its correspondingp value which indicates its position in the CDF curve.)

Another design-related issue is the phase comparator and the counter when the signal under test is in the GHz range. To relieve the performance requirement, one can choose to make the phase comparison in everyk signal periods. No-tice that this is different from dividing the signal under test byk.

5. Conclusion

In this paper, we present an RMS period jitter measure-ment technique intended for BIST applications. By com-paring the phases of the signal under test and two of its de-layed versions, information about the jitter’s CDF curve is

extracted and RMS jitter can thus be derived. Since only two points on the CDF curve are needed, the test circuitry is quite simple. Spice simulation results show less than 5% error for RMS jitters ranging from 40 to 60 ps. We are currently designing a prototype chip to further validate the technique. In the future, we will develop a fully digital im-plementation of the proposed technique to further reduce the circuit complexity.

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