most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.
Index Terms—Compression, DFT, low power, scan chain, test data volume.
I. INTRODUCTION
The rapid increase of chip design technology leads a dramatic growth of scan cells. It makes the large scale chip designs require larger test data volume and longer scan chains. In order to reduce the test data volume, researchers are actively pursuing new solutions to test data compression. On the other hand, the large number of scan cells may generate a huge number of switching activities in the test mode, which may never have been generated in the normal mode [1], [2]. The peak and average power resulting from those extraordinary switching ac-tivities in the test mode may cause the chip malfunction and decrease its reliability [2], [3], which implies another yield and cost loss. Un-fortunately, an effective test data compression scheme may not nec-essarily be an effective power minimization scheme. For example, the linear feedback shift register (LFSR) reseeding approach [4] utilizes the random-fill property for don’t care (X) bits to achieve high encoding efficiency while introducing many switching activities. Since LFSR re-seeding technique provides many transitions, [30] uses rere-seeding and mask technique to achieve low power test. Therefore, to develop a test compression scheme targeting both high compression ratio and large test power reduction is an important goal in test area.
A. Previous Works
Many proposed approaches are dealing with test power reduction. [13] applies Minimum Transition Fill (MT-fill) technique to achieve low test power, and this method minimizes the transitions in one scan chain. [33] considers the successive test pattern to fill the X bits in test pattern, this approach can also reduce test power. In addition, [7], [12] apply reorder techniques to reduce the test power by minimizing the transition count among the test data. Moreover, [7]–[9], [16], [27] use
Manuscript received November 01, 2008; revised March 16, 2009; accepted-March 29, 2009. First published September 01, 2009; current version published July 23, 2010. This work was supported in part by the National Science Council of Taiwan under Grant No. NSC98-2220-E-009-057, NSC 97-2220-E-009-001 and -004..
The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan.
Digital Object Identifier 10.1109/TVLSI.2009.2021061
On the other hand, test data volume can be reduced by compression techniques. It is another way to solve the test data problems, and it sometimes provides low power testing. Due to the necessity of test volume reduction, various techniques have been developed. For example, statistical and Huffman encoding in [5], [6], [15] are used for test volume and test application time reduction. [5] uses 4-bit blocks and encodes test patterns to Huffman code by calculating the pattern frequency. [6] uses run-length (technique in [18]) encoding and Huffman encoding technique to compress data. The basis of run-length encoding lies in encoding a long data string by counting the number of repeated characters or patterns. Nine-code encoding technique is applied in [14] to compress test data. It uses 9 code words to encode data. There are some methods which use structure and memory base scheme to encode test data. In reconfigurable switch structure, [24] applies fewer bits to reconfigurable switch block. [23] provides an inverter-interconnect based decompression network to decode the test data. Broadcast approach in [22], [26] uses broadcaster to distribute few control bits and generates large number of bits to internal scan chains. The Multi-layer Data Copy (MDC) scheme’s method in [25] duplicates the test data inside the chip. [21], [31] uses dictionary based method with memory to encode test data.
For unification solutions, [11], [14] use finite state machine (FSM) mechanism and various kinds of data compression techniques to reduce scan power, test data volume, and test time. [10] modifies run length and combines resource partition to achieve low power and small test data volume. [11] also combines Golomb coding (technique in [19]) to deal with the power and volume issues.
B. The Proposed Schemes
In order to deal with the shift-in power and test data volume prob-lems, we define the decoders with fixed (F) or variable (V) input (I) and output (O). We can have 4 choices: FIFO, FIVO, VIFO, VIVO. However, the FIFO scheme has less flexbility than VIFO in the input, which may cause some unnecessay input bits on the decoders. Since FIFO will reduce the compression effiency, we will not implement the FIFO scheme. The other scheme which we will not implement is the VIVO scheme since it needs some constraint to reduce the complexity in implementation. We implement the FIVO scheme which is a pseudo VIVO scheme. In fact, we define the maximum fan-out as constraint in the FIVO scheme. If the number of output bits is larger than the de-fined maximum fan-out number, we will reduce the input number bits and the input number becomes variable. After the preliminary analysis, we choose fixed output (VIFO) and fixed input (FIVO) schemes to be implemented in this work. Our methodology consists of 3 steps: define the solution scheme, deal with the complex and simple patterns seper-ately, and adjust the final solution. With this methodology, these two schemes present different behaviors. The compressed scan units of the VIFO scheme have fixed number of output bits but variable number of input bits. The compressed scan units of the FIVO scheme have fixed number of input bits but variable number of output bits.
Fig. 1. Compressed scan unit and decoders structure in our fixed output scan chain architecture. The number of scan cells inside compressed scan unit de-pends on the optimization stage shown in Section III.
Fig. 2. Our FIVO scan chain architecture including compressed scan units. A compressed scan unit is provided with n-bit decoder (n = 3 in this illustration), which maps to several number of scan cells in normal scan chain. The last scan unit may not be equal to n in some cases.
The rest of this paper is organized as follows. We describe the concept and the difference between these two schemes in Section II. Sections III and IV express the detail optimization methodology of these two schemes. The experimental results of these two schemes are shown in Section V. We conclude this paper in Section VI. The preliminary version of this paper can be found in [27].
II. SELECTIVEPATTERNCOMPRESSION FORPOWER ANDTESTDATA REDUCTION
We have proposed two schemes using compression techniques to reduce test data and power. Each of the proposed schemes applies its optimization flow to achieve low power and small test data volume respectively. The proposed selective scan chain architectures are shown in Fig. 1 and Fig. 2. We intend to divid all of the test patterns into two groups: first group of test patterns is used for compressed scan chain (CSC), the shift-in patterns are compressed form; second group of test patterns is used in normal scan chain (NSC), the shift-in patterns are not compressed. In this architecture, CSC uses the first group of test patterns which has more X bits to manipulate. X bit ratio is the ratio of the X in a single pattern length (SPL). In this paper, we use X bit omit ratio as an indicator to separate the test patterns: if X bit ratio of a test pattern is smaller than X bit omit ratio, the pattern belongs to NSC group. Otherwise the test pattern belongs to CSC group.
Compressed patterns need special decoders to decode them and the decoders of these two schemes are different. The fixed-output-bit ver-sion is shown in Fig. 1. Its decoders have fixed number of bits for output. Fig. 1 is the 1 unit-to-4 scan cells structure. Each compressed scan unit handles four output bits. The number of scan cells inside compressed scan unit depends on the optimization stage described in Section III.
Fig. 3. Pattern selection stage example. This case uses 0.3 as X-bit omit ratio to select the test pattern. (a) Is original test pattern set which has 17 test patterns. (b) Is selected patterns for NSC. (c) Is selected patterns for CSC.
Another scheme has a fixed number of bits in the input. It means that the decoders of this scheme has a fixed number of input bits but the decoder’s output bit number is variable. For example, Fig. 2 shows 3-bit decoder structure with original scan chain and compressed scan chain. It provides23 conditions of coding results. Each condition provides decoding results to the normal scan cell as test data. The number of scan cells in each condition depends on the optimization stage shown in Section IV.
These schemes can be applied to multiple scan chains structure, which provide very low power consumption. Using multiple scan structure can skip many unnecessary transitions in long scan chain.
III. VIFO SCHEMEOPTIMIZATIONMETHOD
This section will introduce the optimization methodology on test data and power in VIFO scheme. The methodology consists of scan chain partition and three stages. Scan chain partition is to divide the original single scan chain to multiple scan chains. The three stages are pattern selection, pattern compression, and power optimization. The test patterns in the same partition will be processed via the following three stages. The first stage is pattern selection: it sets the X bit omit ratio in order to select the pattern for CSC. The second stage is pat-tern compression: it merges the test patpat-terns in the same segment of test sets. The third stage is power optimization stage. In this stage, it uses shorter pattern length and applies greedy search to find the smaller power consumption code in CSC segment by segment. Each X bit omit ratio provides one result for test data volume and power consumption. A. Pattern Selection Stage
This stage separates the test patterns into two groups by X bit omit ratio. If test pattern’s X bit ratio is smaller than given X bit omit ratio, this test pattern will belong to the NSC group, or it will belong to CSC.SP Lnewis the CSC test data length that comes from compressed scan unit (Fig. 1). Total original test size in equation (1) Original test sizetotal = P attern numberorg2SP Lorg and total new test size in equation (2) New test sizetotal =
NSC pattern number2SPLorg + CSC pattern number 2
SP Lneware used to calculate the test data volume in this paper. The example is shown in Fig. 3. There are 17 patterns in the original test pattern set (Fig. 3(a)). If we set X bit omit ratio as 0.3. We can get 3 patterns in NSC test data set (Fig. 3(b)) and 14 patterns in CSC test data set (Fig. 3(c)).
Fig. 4. VIFO scheme with a 4-bit encoding case in pattern compression stage. (a) is the compressed test pattern. (b) shows the index number of each segment. (c) shows the new test data results and the mapping code comes from (b). (d) shows one test pattern transformation from original test data to new test data.
B. Pattern Compression Stage
When the test patterns for CSC are determined, we use these pat-terns in compression stage. In this stage, we attempt to shrink coding size as small as possible. We use 4 bits as fixed output size to introduce the process. If the original test data length is 21 bits, we divide it to 6 segments. The compression procedure starts to compress test patterns from the first segment to the sixth segment. The next step merges pat-terns in each segment. For instance, this step will merge pattern XX11 and 1XX1 to pattern 1X11. We define TNC as the total number of com-pression results. If we getT NC 2, number of cells in compressed scan unit (CSU) is set to 1. This means we can use 1 input bit to control all of the test patterns in output. If we get2 < T NC 4, number of cells in CSU is set to 2. While we get TNC bigger than 8, we will not encode the segment. Fig. 4(a) is the compression result and the patterns come from the CSC test data set in Fig. 3(c). Fig. 4(a) shows the com-pression result and all Xs are replaced by 0 on compressed data after the compression process. Each compressed pattern is given a number as index. Through the compression procedure, the first and second seg-ment of compressed test data in Fig. 4(a) both need 2 bits to encode the whole segment. The third segment needs 3 bits to encode since the TNC in this segment is 8.
C. Power Optimization Stage
After the pattern compression stage, this subsection introduces the power optimization method to minimize the shift-in power in CSC. We apply greedy search method to find the lower power coding, because we set the bit before first bit of each pattern to 0. This stage maps new encoded data to the compressed pattern index. We use the example in Fig. 4(b) to explain this mapping. The first segment of Fig. 4(b) has 3 different compressed codes. The mapping code and index number can be found in Fig. 4(a). By finding all of the possible codes from the first segment to the last segment, we can get the final encoding result for CSC. The result is shown in Fig. 4(c). This stage calculates the smallest transition mapping from the first segment. The permutation of 3 bits, with 8 new encoded data, is 40320(8!). The optimization method tries to find all the permutations from the first segment to the last segment, and decides the fewest switching power encoding. The encoding result becomes new encoded data.
The first pattern in Fig. 4(b) shows that 030311 is the index number of the test pattern. This pattern maps to test result 000010100000110001010 and new test pattern 01000101010. The first 4 bits of the test result is 0000. It comes from the mapping number 0 in Fig. 4(b) and first segment of pattern 0000 in Fig. 4(a). The 5th to 8th bit of the test result is 1010. It comes from the mapping number 3 in the
three stages and different partitions go through these three steps in-dependently. Otherwise it consists of three stages. The three stages are pattern selection, pattern compression, and power optimization. Pattern selection is the same with previous scheme. We will reference from the previous one (Section III-A). Techniques in pattern compression and power optimization are different. We will focus on these two stages in this section. Similarly, all of the test patterns in the same partition go through these three stages.
Pattern selection method of FIVO scheme is the same with VIFO scheme. Test patterns for CSC are compressed by the pattern compres-sion stage. This stage contains merging, extending, and maximizing steps.
We use an example whenn = 3 to illustrate the procedure of this stage. The compression procedure starts to compress test patterns with 3 bits segment from the first bit of the CSC test pattern set. Each 3-bit decoder provides 8 different codes. Each code represents one com-pressed pattern which is merged from original test data. For instance, this step will merge pattern X11 and XX1 to pattern X11. Moreover, XX11, X111, 0111 will be merged to code 0111 in the same segment. If the total number of compression results is smaller then 8, it extends the segment to 4 bits. Until the total number of compression results is maximum but smaller than 8 or equal to 8, the results are encoded to 3 bits in CSC. Next, it starts to encode another 3 bits. At last, it may have 2 bits or 1 bit decoder at the end. If the number of compression results is 3 or 4, the results will be encoded to 2 bits. If the compression results equal to 1 or 2, the results will be encoded to 1 bit. We also limit the maximum number of one decoder output to 256. If the output number of a decoder achieves 256, we will finish processing this segment and the input number of this segment’s encoder may fewer than 3. Finally, we also can use 4-bit or 5-bit decoder that provides 16 or 32 different codes.
To be more specific, a realistic case is provided in this paragraph. This example shows 14 test patterns in CSC. The compression pattern number will equal or smaller then original pattern number after the merging step. Fig. 5(a) shows the compression results and all Xs after the compression are replaced by 0. Each compressed pattern is given a number as index. Through the compression procedure, the first segment of compressed test data in Fig. 5(a) applies 3 bits (6 codes) to encode 11 bits data.
In order to minimize the shift-in power with n-bit based encoding, the greedy search method are applied in each segment to find the lower power coding. Assume the initial state of the scan chain is 0, it will obtain the optimal solution(n = 3) and heuristically good solution (n > 3) after pattern selection and pattern compression stages. This stage maps new encoded data to the compressed pattern. The first column of Fig. 5(a) needs 6 different compressed codes to map. In Fig. 5(a), (b), (c), test result 00001000000 maps to 0 and 0 maps to new test pattern 110 in the first row first column of Fig. 5(b), (c). The CSC shift-in data will be 110 and the decoder will produce 00001000000 to NSC.
In this stage, we calculate the smallest transition mapping from first segment. The permutation of 3 bits, with 8 new encoded data, is
Fig. 5. FIVO scheme with a 3-bit encoding case in pattern compression stage. (a) Is the compressed test pattern of each segment. (b) Shows the index number of each segment. (c) Shows the new test data results and the mapping codes come from (b). (d) Shows one test pattern transformation from original test data to new test data.
TABLE I
VIFO SCHEMEEXPERIMENTALRESULTS INTESTPATTERNREDUCTION AND
POWERREDUCTIONUSINGMINTESTSET(ISCAS’89 BENCHMARKS)
40320(8!). The optimization method tries to find all the permutations from the first segment to the last segment, and decides the fewest switch power encoding. The encoding results become new encoded data. Since the permutations of 4 and 5 bits encoded data are very large, the computation time of optimization stage will be very long. Only to optimize the partial encoded data is recommended. The first row in Fig. 5(b) shows that 04 is the index number of the test pattern. This pattern maps to test result 000010000000100000001 and new test pattern 110001. The test result can be get from Fig. 5(a) by index. In this example, the index code 0 in the first column of Fig. 5(a) maps to 0000100000 and maps to 110 in Fig. 5(c). The index code 4 in the second column of Fig. 5(a) maps to 0100000001 and maps to 001 in Fig. 5(c). We also can perceive that all of the index codes 0 in the first column of Fig. 5(b) are maps to 110.
With the mapping method, we can get the CSC shift-in codes. Each row in Fig. 5(c) will be shifted into CSC. Fig. 5(c) is the power opti-mization result codes. We can observe that the compressed patterns are encoded to fewer bits of data. Fig. 5(d) shows a new test pattern (on the bottom), which is generated from original test pattern, to the com-pressed data mapping index, then to the comcom-pressed data in CSC. We can get the decoded results for NSC from Fig. 5(a).
V. EXPERIMENTALRESULTS
This experimental result section contains three subsections. The first subsection provides the experimental results of the VIFO scheme. The second subsection provides the experimental results of FIVO scheme. The third subsection provides the limitation of the proposed FIVO schemes. All of our experimental results use ISCAS’89 circuits. We
Fig. 6. (a) 4-bit VIFO scheme experimental results using one scan chain ar-chitecture with different omit ratio. New total test size is normalized to original test size. Power consumption is normalized to power of all X bits filled with 0. This shows that the scheme provides both power and volume reduction. (b) 3-bit FIVO scheme experimental results using one scan chain architecture with different omit ratio. The normalization parameters of (a) and (b) are the same.
TABLE II
FIVO SCHEMEEXPERIMENTALRESULTS INTESTPATTERNREDUCTION AND
POWERREDUCTIONUSINGMINTESTSET(ISCAS’89 BENCHMARKS)
also can integrate the method in [8] to have multiple scan chains and partition them to more sub scan chains, which provides lower power for large SoC designs than one long scan chain [27].1
A. Experimental Results of VIFO Scheme
We use 4 bits output scan unit as our experimental architecture which is shown in Fig. 1. The experimental results are shown in Table I and Fig. 6(a). Table I shows that different circuits need different X bit omit ratios to obtain the lowest test power. The caculation of total power consumption consists of shift in power in CSC, NSC, and transfer power from CSC and NSC. Using 55% as X bit omit rate in benchmark s38584, we can get 55% power and 55% test data volume. In Fig. 6(a), we observe that both power and data volume reduction are 45% at X bit omit ratio 55%. All of the results in Table I and Fig. 6(a) are normalized with the data of all X bits filled with 0. This technique achieves small test data size in each circuit and it has some power reduction percentage in these experimental results.
B. Experimental Results of FIVO Scheme
In our experimental results, different test data sets and circuits have different ratios to meet the lowest power and smallest test data volume. Fig. 6(b) shows the FIVO scheme result of circuit s38584. Users can apply X bit omit ratio to obtain the best power or the best compression. Fig. 6(b) shows the FIVO scheme result provides the lowest power about 49% at 30% X bit omit ratio in circuit s38584. It uses 130 of total 136 patterns in CSC. The smallest test data volume is about 31% at 65% X bit omit rate, and it uses 116 of 136 patterns in CSC. We can observe that the FIVO scheme provides better power and area re-sults than VIFO scheme from Fig. 6(a) and (b). Table II shows the best volume size results in each bench circuit.
Table III shows the Mintest set compression results. Although pre-vious works have smaller volume than ours in some circuits, our 5 bits FIVO scheme still provides good compression results in these circuits.
1This paper only deals with shift-in power. The power estimation method is
with gcc version 3.4.5. The programs run on the server with Intel(R) Xeon(R) 5160 3.00 GHz CPU and 32 GB memory. We check 40320(8!) cases in FIVO (3-bit) scheme. However, the permutations of 4 and 5 bits encoded data are very large, we only optimize partial of the encoded data at the optimization stage to achieve low power results.
VI. CONCLUSION
In this paper, we propose two schemes with related encoding methodology to reduce test power consumption and shrink test data volume. Experimental results of fixed input version show this scheme achieves better reduction rate of test data volume. We also compare the FIVO scheme with previous works, the results provide relatively small test data size. In addition, we implement the decoders in FIVO scheme and observe that we can get a feasible X bit omit ratio as tradeoff between volume, power, and area overhead. With acceptable hardware overhead, our approach is practical and can be applied in modern chip DFT designs.
ACKNOWLEDGMENT
The authors would like to thank all of the reviewers for providing precious comments to improve this paper.
REFERENCES
[1] A. Crouch, Design-for-Test for Digital IC’s and Embedded Core
Sys-tems. Englewood Cliffs, NJ: Prentice Hall, 1999.
[2] P. Girard, “Survey of low-power testing of VLSI circuit,” in Proc. IEEE
VLSI Test Symp., 2002, pp. 82–92.
[3] N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI
Circuits. Norwell, MA: Kluwer, 2003.
[4] B. Koenemann, “LFSR-coded test patterns for scan designs,” in Proc.
Eur. Test Conf., 1991, pp. 237–242.
[5] S. Kajihara, K. Taniguchi, I. Pomeranz, and S. M. Reddy, “Test data compression using don’t-care identification and statistical encoding,” in IEEE Int. Workshop Electronic Design, Test Appl., 2002, pp. 413–416.
[6] M. Nourani and M. H. Tehranipour, “RL-Huffman encoding for test compression and power reduction in scan applications,” ACM Trans.
Design Autom. Electron. Syst., vol. 10, no. 1, pp. 91–115, Jan. 2005.
[7] I. Lee, J. H. Jeong, and T. Ambler, “Two efficient methods to reduce power and testing time,” in Proc. Int. Symp. Low Power Electron.
De-sign, 2005, pp. 167–172.
[8] K. J. Lee, S. J. Hsu, and C. M. Ho, “Test power reduction with multiple capture orders,” in Proc. IEEE Asian Test Symp., 2004, pp. 26–31. [9] Y. Shi, N. Togawa, S. Kimura, M. Yanagisawa, and T. Ohtsuki, “Low
power test compression technique for designs with multiple scan chains,” in Proc. IEEE Asian Test Symp., 2005, pp. 386–389. [10] A. Chandra and K. Chakrabarty, “A unified approach to reduce SOC
test data volume, scan power and testing time,” IEEE Trans.
Com-puter-Aided Des. Integr. Circuits Syst., vol. 22, no. 3, pp. 352–362,
Mar. 2003.
[11] A. Chandra and K. Chakrabarty, “Low-power scan testing and test data compression for system-on-a-chip,” IEEE Trans. Computer-Aided Des.
Integr. Circuits Syst., vol. 21, no. 5, pp. 597–604, May 2002.
[12] L.-C. Hsu and H.-M. Chen, “On optimizing scan testing power and routing cost in scan chain design,” in Proc. Int. Symp. Quality
Elec-tronic Design, 2006, pp. 451–456.
techniques to control scan vector power dissipation,” in Proc. IEEE
VLSI Test Symp., 2000, pp. 35–40.
[14] M. Nourani M. Tehranipour and K. Chakrabarty, “Nine-coded com-pression technique with application to reduced pin-count testing and flexible on-chip decompression,” in Proc. Design, Automation, Test in
Europe, Mar. 2004, pp. 1284–1289.
[15] A. Jas, J. G. Dastidar, M. E. Ng, and N. A. Touba, “An efficient test vector compression scheme using selective Huffman coding,” IEEE
Trans. Computer-Aided Des. Integr. Circuits Syst., vol. 22, no. 6, pp.
797–806, Jun. 2003.
[16] L. Whetsel, “Adapting scan architectures for low power operation,” in
Proc. IEEE Int. Test Conf., 2000, pp. 863–872.
[17] A. Chandra and K. Chakrabarty, “Frequency-directedrun-length (FDR) codes with application to system-on-a-chip test data compression,” in
Proc. IEEE VLSI Test Symp., May 2001, pp. 42–47.
[18] S. W. Golomb, “Run-length encoding,” IEEE Trans. Inf. Theory, vol. IT-12, pp. 399–401, Dec. 1966.
[19] G. Seroussi and M. J. Weinberger, “On adaptive strategies for an extended family of Golomb-type code,” in Proc. Data Compression
Conf., 1997, pp. 131–140.
[20] Y. Shi, N. Togawa, S. Kimura, M. Yanagisawa, and T. Ohtsuki, “An efficient multiscan-based test compression technique for test cost re-duction,” in Proc. ACM/IEEE Design Automation Conf., Jul. 2006, pp. 653–658.
[21] C. S. Tautermann, A. Wurtenberger, and S. Hellebrand, “Data com-pression for multiple scan using dictionaries with corrections,” in Proc.
IEEE Int. Test Conf., Oct. 2004, pp. 926–935.
[22] L.-T. Wang, X. Wen, H. Furukawa, F.-S. Hsu, S.-H. Lin, S.-W. Tsai, K. S. Abdel-Hafez, and S. Wu, “VirtualScan: A new compressed scan technology for test cost reduction,” in Proc. IEEE Int. Test Conf., Oct. 2004, pp. 916–925.
[23] A. Orailoglu, W. Rao, and G. Su, “Frugal linear network-based test de-compression for drastic test cost reduction,” in Proc. Int. Conf.
Com-puter-Aided Design, Nov. 2004, pp. 721–725.
[24] H. Tang, S. M. Reddy, and I. Pomeranz, “On reducing test data volume and test application time for multiple scan chain designs,” in Proc.
IEEE Int. Test Conf., 2003, pp. 1079–1088.
[25] S. P. Lin, C. L. Lee, J. E. Chen, J. J. Chen, K. L. L, and W. C. Wu, “A multilayer data copy scheme for low cost test with controlled scan-in power for multiple scan chain designs,” in Proc. IEEE Int. Test Conf., 2006.
[26] A. R. Pandey and J. H. Patel, “An incremental algorithm for test gen-eration in Illinois scan architecture based designs,” in Proc. Design,
Automation, Test in Europe, 2002, pp. 368–375.
[27] C.-Y. Lin and H.-M. Chen, “A selective pattern-compression scheme for power and test-data reduction,” in Proc. Int. Conf. Computer-Aided
Design, 2007, pp. 520–525.
[28] G. Mrugalski, J. Rajski, D. Czysz, and J. Tyszer, “New test data de-compressor for low power applications,” in Proc. ACM/IEEE Design
Automation Conf., 2007, pp. 539–544.
[29] M. Elm et al., “Scan chain clustering for test power reduction,” in Proc.
ACM/IEEE Design Automation Conf., 2008, pp. 828–833.
[30] J. Lee and N. A. Touba, “LFSR-reseeding scheme achieving low-power dissipation during test,” IEEE Trans. Computer-Aided Des. Integr.
Cir-cuits Syst., vol. 26, no. 2, pp. 396–401, Feb. 2007.
[31] L. Li and K. Chakrabarty, “Test data compression using dictionaries with fixed-length indices,” in Proc. IEEE VLSI Test Symp., 2003, pp. 219–224.
[32] K. J. Balakrishnan and N. A. Touba, “Improving linear test data com-pression,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, pp. 1227–1237, 2006.
[33] J. Li, Q. Xu, Y. Hu, and X. Li, “On reducing both shift and capture power for scan-based testing,” in Proc. IEEE Asia South Pacific Design
