Al-SiO2-Y2O3-SiO2-poly-Si Thin-Film Transistor Nonvolatile Memory Incorporating a Y2O3 Charge Trapping Layer

ECS Solid State Letters, 2 (10) P83-P85 (2013) P83 2162-8742/2013/2(10)/P83/3/$31.00©The Electrochemical Society

Al-SiO

-Y

O

-SiO

-poly-Si Thin-Film Transistor Nonvolatile

Memory Incorporating a Y

O

Charge Trapping Layer

Tung-Ming Pan,a,z_{Li-Chen Yen,}b_{Somnath Mondal,}a_{Chieh-Ting Lo,}a_{and Tien-Sheng Chao}b a_{Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan}

b_{Department of Electrophysics, National Chiao Tung University, Hsinchu 30010, Taiwan}

In this letter, we investigate the structural properties and electrical characteristics of the Al–SiO2–Y2O3–SiO2–poly-Si (AOYOP) thin-film transistor (TFT) nonvolatile memory device. The composition of Y2O3charge-trapping layer was analyzed using X-ray photoelectron spectroscopy. The Y2O3 AOYOP TFT memory device exhibited a large memory window of 2.5 V, a long charge retention time of ten years with a minimal charge loss of∼15%, and a better endurance performance for P/E cycles up to 105_. © 2013 The Electrochemical Society. [DOI:10.1149/2.002310ssl] All rights reserved.

Manuscript submitted May 23, 2013; revised manuscript received July 5, 2013. Published July 13, 2013.

Low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) are widely used for active matrix liquid crystal dis-play and active matrix organic light emitting diode.1 _{With the rapid}

advance in the manufacturing technologies, the extent and complexity of circuit integration have been tremendously increased. The realiza-tion of integrating an entire system on the top of the panel is then being rigorously pursued by low-temperature process.2,3 _{With the}

increas-ing demand of system reconfigurability in advanced system-on-chip (SOC), many different memory functions are necessitated.4–6

Specif-ically, non-volatile memory (NVM) is crucial and, therefore, careful choice of the best NVM device to be integrated in the system is most important. Silicon–oxide–nitride–oxide–silicon (SONOS)–type flash memory device has received a considerable amount of interest in the electronics industry because of its non-volatility, low power consump-tion, and fast speed.7,8_{However, the erase saturation phenomenon and}

vertical stored charge migration9,10 _{for conventional SONOS–type}

memory open critical issues in device performance and reliability. Various technologies have been developed for improving the per-formance and reliability of SONOS–type memory. Chen et al. devel-oped a bandgap engineering of SiNxfilm to improve the retention and

endurance characteristics.11_{Lin et al. suggested the Hf-silicate film as}

the charge trapping layer deposited by cosputtering method for achiev-ing long retention time and good endurance.12 _{Recently, we have}

proposed and demonstrated an yttrium oxide (Y2O3) film as a good

candidate for charge trapping layer in flash memory technology.13,14

However, Y2O3thin film integrated in LTPS-TFT memory device has

not been reported. Moreover, Y2O3 film can also be considered as

one of the most promising candidate materials for LTPS-TFT mem-ory applications due to its large dielectric constant (13∼17) and wide bandgap energy (5.6 eV).15,16_{In this letter, we explore the structural}

properties and electrical characteristics of the Al–SiO2–Y2O3–SiO2–

poly–Si (AOYOP) TFT nonvolatile memory device integrated with an Y2O3charge trapping layer. This memory exhibits good electrical

characteristics, including large memory window, good retention time, and high endurance.

Experimental

The cross sectional view of the Y2O3 AOYOP TFT nonvolatile

memory is illustrated in Fig.1a. First, a 500 nm-thick thermal oxide was grown on the Si wafer by wet oxidation system to substitute the glass substrate. A 50 nm-thick amorphous-Si (α-Si) film for the chan-nel region was deposited at 550◦C by a low-pressure chemical vapor deposition (LPCVD) system. Subsequently, solid-phase crystalliza-tion was performed at 600◦C for 24 h in N2ambient for polycrystalline

channel formation. The source and drain (S/D) regions were doped by phosphorous ion implantation with a dose of 5× 1015_ions/cm−2

at 17 keV, then activated by furnace at 600◦C for 24 h. A∼10 nm tetraethyloxysilane (TEOS) silicon oxide film as a tunneling layer was deposited through LPCVD system. A∼3 nm-thick Y2O3 film

z_{E-mail:[email protected]}

was then deposited on the tunneling oxide by a physical vapor deposi-tion system. Another thin film of∼20 nm SiO2as a blocking oxide was

deposited by plasma-enhanced chemical vapor deposition (PECVD) at 350◦C. After creating the contact holes at S/D region, a 500 nm-thick Al was deposited by physical vapor deposition and patterned for gate and S/D contact pads. The length and width of the n-channel AOYOP TFT memory device were 10 and 10μm, respectively. The threshold voltage (VTH) values are obtained from the current-voltage

(transfer characteristics) curves at a fixed drain current value of 100 nA (100× W/L nA).

Results and Discussion

In order to analyze the physical properties of yttria charge trapping layer, the chemical elements were detected by X-ray photoemission spectroscopy (XPS). Figs.1band1cshow the Y 3d and O 1s spectra, respectively, of the Y2O3 charge trapping film with their

appropri-ate peak curve-fitting lines. The Y 3d double peaks (157.2 eV and 159.3 eV) shifted to higher binding energy by 0.4 eV relative to the Y2O3 reference position (156.8 eV and 158.9 eV).17 It may be

at-tributed to the formation of a silicate layer at the Y2O3-SiO2interface.

Fig.1cdepicts that the O 1s spectra of Y2O3film can be deconvoluted

into three peaks located at 529.5, 531.8, and 533 eV, corresponding to Y2O3, Y-silicate, and SiO2,17respectively. The intensity of O 1s peak

corresponding to silicate layer was larger compared to other peaks, indicating the formation of a thicker silicate layer between the Y2O3

and SiO2interface.

Fig. 2ashows the transfer characteristics of the Y2O3 AOYOP

TFT memory device following the P/E operations. The AOYOP TFT memory device exhibited good transistor behavior with a high Ion/Ioff

ratio of 5.3× 106_{. The field-effect mobility of 15.32 cm}2_{· V}−1_{· s}−1

and a subthreshold swing of 1.34 V/dec were obtained in the AOYOP TFT memory device. The TFT memory device was programmed by channel hot electron (CHE) injection method, whereas the erasing was carried out by band-to-band hot hole (BTBHH) injection to the device. After programming at the VGSof 10 V and the VDSof 10 V for

1 s, the threshold voltage shifted from 3.4 V (fresh device) to 5.6 V (programmed state). This can be attributed to the electron trapping in the charge trapping layer in the TFT memory device. The electron trapping can be explained by considering the band diagram presented in Fig.2b. The conduction band offset between the tunneling oxide and the Y2O3charge trapping layer is 2.3 eV. The large electric field in the

poly-Si channel of the TFT device creates impact ionized hot-electrons whose energy when exceeds the gate-oxide potential barrier (3.1 eV) can be injected to the gate oxide and Y2O3 charge trapping layer.

This electron trapping causes the IDS-VGScurve in Fig.2ato move to

the right, and thus increasing the VTHvalue after programming. After

erase operation of the TFT memory device, we can clearly observe that the IDS-VGS curve did not fully recover to the initial transfer

characteristic. This behavior might be due to the mismatch between the localized spatial distributions for the injected electrons and holes by using CHE programming and BTBHH erasing. The uncompensated

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P84 ECS Solid State Letters, 2 (10) P83-P85 (2013) 536 534 532 530 528 Y 2O3 Y-silicate SiO 2 (c) O 1s

).

u .

a(

yti

s

n

et

nI

Binding energy (eV)

Al gate

Buried oxide

n

_n

Si-substrate

Y

O

SiO

SiO

(a)

).

u .

a(

yti

s

n

et

nI

Binding energy (eV)

Figure 1. (a) Cross-sectional view of the AOYOP

TFT device memory structure using a Y2O3charge trapping layer. XPS spectra of (b) Y 3d and (c) O 1s for Y2O3charge trapping layers.

(b) 1.1eV 4.6eV 3.1eV 2.3eV 5.6eV 0.9eV 4.1eV

Poly-Si SiO2 Y2O3 SiO2 Al gate

-6 -4 -2 0 2 4 6 8 10 10-13 10-11 10-9 10-7 10-5 (a) W/L=10um/10um ) A( t n er r u c ni ar D Gate voltage (V) Fresh Program Erase

Figure 2. (a) Transfer characteristics of the AOYOP

TFT memory device. (b) Band diagram of the AOYOP TFT memory. 10-5 10-4 10-3 10-2 10-1 100 101 0 1 2 3 (b) V GS=-5V, VDS=10V V GS=-8V, VDS=10V V_GS=-10V, V_DS=10V V TH ) V( tfi h s Erasing time (s) 10-5 10-4 10-3 10-2 10-1 100 101 0 1 2 3 (a) V GS=10V, VDS=5V V GS=10V, VDS=8V V GS=10V, VDS=10V V TH ) V( tfi h s Programming time (s)

Figure 3. (a) Programming and (b) erasing

charac-teristics of AOYOP TFT memory devices.

charge will then cause the VTHto shift. Moreover, another important

parameter for memory read-out operation in the TFT memory device is the difference between the programming current (IPR) and the erasing

current (IER) at certain reading voltage. The IPR/IER current ratio of

programmed and erased state in AOYOP TFT device at the read-out voltage of 2 V is more than two-orders-of magnitude, which suffices for nonvolatile memory applications.

Figure3ademonstrates the program speed of the AOYOP TFT memory device, performed under three different stress conditions at VDS of 5, 8, and 10 V and VGSof 10 V for CHE programming. The

VTHshift is defined as the change in the threshold voltage of a TFT

memory device between the programmed and the erased states. At the larger programming bias at VGS= VDS= 10 V for 1 s programming,

we observed a large VTHshift of∼2.5 V. It is also observed that the

VTH shift increases with the increase of applied drain voltage. This

is because a large amount of “hot” electrons were generated when a larger drain voltage was applied, and thus more electrons were capable of crossing the barrier height to become trapped in the Y2O3layer.

The erase speed behaviors of the AOYOP TFT memory device were also presented in Fig.3b. We can clearly observe significant increase of programming and erasing speed for higher drain and gate voltage, respectively.

Fig. 4ashows the retention characteristics of the AOYOP TFT memory devices at room temperature and 85◦C. The retention mea-surement was performed after the CHE programming. The normalized VTHshift is defined as the ratio of VTHshift at the time of interest and at

the beginning. The retention times of the AOYOP TFT memory device can be extrapolated more than 10 years operation time for a minimal charge loss of 15% at room temperature. Such good retention behavior can be attributed to the tight embrace of the Y2O3trapping layer with

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ECS Solid State Letters, 2 (10) P83-P85 (2013) P85 100 101 102 103 104 105 2 3 4 5 6 7 (b) Program V GS=10V, VDS=10V, 1 s Erase V_GS=-10V, V_DS=10V, 1s VTH ) V( Program/Erase cycles 100 102 104 106 108 1010 0.0 0.2 0.4 0.6 0.8 1.0 25oC 85oC 10 years (a) V d e zil a mr o N TH Retention time (s)

Figure 4. (a) Retention and (b) endurance

character-istics of AOYOP TFT memory devices.

sufficiently deep trap energy level.6_{However, at elevated temperature}

of 85◦C, the retention capability of AOYOP TFT memory device de-graded significantly and a charge loss of∼35% was observed after 108_{s. We believed that the AOYOP device with a thick tunnel oxide}

can be used to improve the charge-keeping capability. Fig.4b demon-strates the endurance characteristics of the AOYOP TFT memory device. The device was programmed at VGS= 10 V and VDS= 10 V

and erased at VGS = −10 V and VDS = 10 V with the same

pro-gramming and erasing time of 1 s. No significant memory window narrowing is observed in the AOYOP TFT memory device. Though, the VTHincreases for both memory states after 103P/E cycles. We

consider three aspects to explain this behavior. First, the gradual in-crease of VTH may be due to the induced electron trapping to the

vicinity of trapping layer during P/E cycling test. Second, the stress induced electron traps generated in the tunnel oxide. The other reason is the presence of uncompensated charge due to mismatch between localized spatial distributions of the injected charges. But, we believe that the third reason is most dominant since it can successfully ex-plain the erase characteristics in Fig.2a. The Y2O3film as the charge

trapping layer exhibits the potential to be incorporated into the future LTPS-TFT nonvolatile memory fabrication.

Conclusion

In conclusion, we have fabricated the AOYOP TFT nonvolatile memory device using an Y2O3charge trapping layer. The XPS

anal-ysis indicates the formation of a thicker yttrium silicate layer. The AOYOP TFT memory device exhibited better electrical characteristics in terms of large memory window (2.5 V), long charge retention time (∼15% charge loss at ten years), and good endurance (up to 105_P/E

cycles) with no memory window narrowing. The Y2O3thin film is a

promising charge trapping layer material for the fabrication of LTPS-TFT memory devices.

Acknowledgment

This work was supported by the National Science Council (NSC) of Taiwan under contract no. NSC-98-2221-E-182-056-MY3.

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