10-Gb/s modulator drivers with local feedback networks

circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35- m SiGe BiCMOS process could generate 9V_PP differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8V_PPin 0.18- m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported Silicon-based drivers.

Index Terms—Intrinsic collector-base capacitance, intrinsic

drain-gate capacitance, laser drivers, modulator drivers, sil-icon-based, 10 Gb/s.

I. INTRODUCTION

E

XTERNAL modulators are preferably used to modulate light intensity in long-haul 10-Gb/s fiber-optic communi-cation systems. To ensure sufficient extinction ratio, modulator drivers are required to supply an output swing higher than 3 . Over the past decade, most modulator drivers have been fabri-cated in compound semiconductors owing to their high-break-down and high-speed characteristics [1]–[7]. However, most of them are quite inefficient both in the die area and power con-sumption. To achieve low cost system integration with other digital functional blocks, a driver circuit realized by high-speed transistors with lower breakdown voltage is required. 10–14 Gb/s SiGe HBT drivers with output swings over 3 and 10-Gb/s CMOS drivers with 2.5 output swings have been reported in [8] and [9], respectively. However, it is difficult for such single transistor topology to generate a voltage swing larger than 3.5 . To solve this problem, a series connected voltage balancing (SCVB) topology [4], [10] was introduced to double the breakdown voltage. Mandegaran and Hajimiri [11] modified the SCVB and implemented the driver in 0.18- m SiGe BiCMOS technology to give a differential output swing of 8 . However, there existed two drawbacks for this de-sign: first, the sophisticated analysis of large signal driver, and second, the power inefficiency.

In this paper, we demonstrate how to implement 10-Gb/s modulator drivers effectively and efficiently in Silicon-based process technology. A novel intrinsic collector-base capaci-tance feedback network (ICBCFN) was incorporated into the

Manuscript received June 27, 2005; revised December 23, 2005.

D.-U. Li is with the Industrial Technology Research Institute, 310 Taiwan, R.O.C. (e-mail: davidli@itri.org.tw).

C.-M. Tsai is with the National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

Digital Object Identifier 10.1109/JSSC.2006.872878

conventional cascode and SCVB circuit configurations at the output stage to implement drivers in 0.35- m SiGe BiCMOS technology, whereas an intrinsic drain-gate capacitance feed-back network (IDGCFN) modified from ICBCFN was used to implement drivers in 0.18- m CMOS technology. The performances, compared with previous works, are shown in Table I. To illustrate the efficiency of the ICBCFN, the driver

Fig. 1. (a) Conventional cascode driver and (b) that with proposed ICBCFN.

with SCVB only is also implemented in SiGe BiCMOS tech-nology and the results are also compared. With the advantage of ICBCFN, the power consumption is greatly reduced from 2 W to 1 W. The present work shows the smallest die area with a driving capability greater than the previously reported silicon-based drivers.

II. CIRCUITDESIGN ANDIMPLEMENTATION

A. Design Concept

In conventional driver design for large output signals, the output transistor has to sustain the whole output voltage and its size is therefore very large. This limits the achievable output swing and operation speed due to the large parasitic capacitance. One might consider a conventional cascode circuit topology shown in Fig. 1(a) to solve the problem. However, the fixed base voltage of the transistor , , confines the signal magni-tude at the collector of the transistor . As a result, the output transistor, again, sustains almost the whole output voltage and this also limits the achievable output swing with low break-down-voltage devices. Fig. 1(b) illustrates the proposed circuit diagram incorporating ICBCFN into a cascode configuration. The design concept is to designate the base voltage , so that it can bear the same phase with the output voltage rather than just being fixed. This goal can be achieved by providing a path to feedback the output voltage to give a proper . Thus, the emitter voltage of the transistor follows (characteristics of emitter followers) and its signal magnitude is larger than that of the conventional circuit topology. If the feedback network is properly designed, the two transistors, and , will evenly share the output swing. Therefore, the achievable output swing doubles without compromising the speed. A further advantage of this circuitry compared with a single transistor topology is that it is able to reduce Miller effect due to the lower signal mag-nitude at collector of . Thus, a low-power pre-driver can be achieved.

B. Circuit Implementation on SiGe BiCMOS Process

Fig. 2 shows the proposed driver, denoted as Driver 1 here-after. It comprises a differential cascode output stage, a band-width enhancing circuit composed of , , , and , and a feedback network composed of , , , and . The re-sistive feedback comprising and is used to provide the

Fig. 2. Proposed driver, driver 1, with ICBCFN.

Fig. 3. Base voltage ofQ for different values of C with R and R fixed.

low-frequency feedback control, and the capacitive feedback comprising and is used for the high-frequency part. The choice of is quite important. Fig. 3 shows how this parameter affects the waveform at the base of . The quality of the output waveform is acceptable as long as the value of does not

de-viate from its optimized window .

A better way to implement to avoid process and temperature variations is to employ a transistor with its base and emitter connected and its size a little bit larger than that of . Once is optimized, and can be determined to make both high- and low-frequency parts of an output swing shared evenly between and . and can be kept much larger for power-saving considerations. In addition, this resis-tive feedback network can also be properly designed to serve as a back termination network. Thus, the influence of the ca-pacitive feedback becomes negligible due to the resulting wide-band characteristic of the resistive feedback. Fig. 4 shows the collector-emitter voltage of and , respectively, in con-ventional cascode topology with and without ICBCFN. It is clear that in our proposed driver and share equal voltage swing, whereas in conventional cascode driver shares most of the swing. The conventional cascode topology is just like an-other single-transistor type driver and it is not reliable to imple-ment modulator drivers. The bandwidth enhancing circuit not only enhances the bandwidth but also provides appropriate bias currents to both and . Finally, is used for DC control and can be simply connected to the same supply voltage used for pre-driver for convenience. In this design, is 3.3 V. To illus-trate the efficiency of the cascode configuration with ICBCFN, we have also implemented a single-transistor topology driver,

Fig. 4. Collector-emitter voltage of transistorsQ and Q with and without ICBCFN.

Fig. 5. Single-transistor type driver, driver 2.

denoted as Driver 2 hereafter, in 0.35- m SiGe BiCMOS tech-nology as shown in Fig. 5.

C. Circuit Implementation on CMOS Process

The concept of ICBCFN is also applicable to implementing drivers in CMOS technology. Fig. 6(a) shows the proposed CMOS driver, denoted as Driver 3 hereafter. However, the breakdown-voltage of CMOS devices shrinks as the size of transistors scales down. Therefore, we have to modify the designing procedure used in SiGe BiCMOS technology by sharing the output swing between the two transistors, and , in proportion to their breakdown voltages and , respectively. To generate a higher voltage swing, the transistor should be a high-voltage device sustaining a higher voltage swing, while the transistor is a low-voltage device sus-taining a lower voltage swing for a smaller Miller effect, thus maintaining the speed. The key point of the design concept is to focus on controlling a proper . The driver circuit comprises a differential cascode output stage and a feedback network composed of , , , and . Again, the quality of the output waveform is acceptable as long as the value of does not deviate from its optimized window. Once is optimized, and can be determined to make both high- and low-fre-quency parts of an output swing shared proportionally between and . Fig. 6(b) shows the pre-driver. To have a better speed performance, an inductor is inserted between the load and the power supply for peaking.

In this design, is 1.8 V. For comparison, we also im-plement a driver, denoted as Driver 4 hereafter, in which both the transistors and are low-voltage devices. The output

Fig. 6. (a) Proposed CMOS driver, driver 3 with IDGCFN and (b) pre-driver with peaking inductors.

Fig. 7. (a) ICBCFN incorporated into SCVB and (b) driver 5.

swing is predicted to be less than that of Driver 3, but the power consumption is lower.

D. ICBCFN Incorporated Into SCVB

Fig. 7(a) illustrates the proposed design concept that incor-porates ICBCFN into the SCVB configuration. Both a feed-for-ward gain stage and an output feedback network are used to gen-erate a proper base voltage . Fig. 7(b) shows the proposed driver, denoted as Driver 5 hereafter. It comprises a differen-tial cascode output stage, a differendifferen-tial gain stage, a bandwidth enhancement circuit, and a capacitive feedback network. The differential gain stage, which comprises , and , is de-signed to provide the drive voltage with magnitude one half of

the output swing , where is the

mod-ulation current and is the current ratio. In addition, owning to the large size of and , must be kept small to ensure that the drive signal is fast enough to track the output response. Thus, it demands large devices for both and to provide a large current drive capability. As a result, the power dissipation in both of the pre-driver and the differential gain stage significantly increases. A simple approach to alleviate the problem is to uti-lize the high-frequency feedback network comprising and . With this high-frequency signal path, the differential gain stage can be treated as just a low-frequency signal generator. As a result, can be much larger and the current consumption of the gain stage can thus be greatly reduced from 90 mA to only 7.5 mA ( from 1 to 12), and that of the pre-driver can be

Fig. 8. Die photomicrograph of driver 1.

Fig. 9. Measured eye diagrams for (a) driver 1 and (b) driver 5 at 10 Gb/s. Vertical: 1 V/div; horizontal: 16 ps/div.

reduced to half of its original value. The total power consump-tion therefore is reduced from 2 W to 1 W. To avoid process and temperature variations, the capacitor is implemented by em-ploying a transistor with its base and emitter connected together and its size a little larger than that of . In this design, is 5 V.

III. CHIP-ON-BOARDTESTRESULTS

Driver 1, Driver 2, and Driver 5 were implemented in 0.35- m SiGe BiCMOS technology, whereas Driver 3 and Driver 4 were in 0.18- m CMOS technology. All drivers were tested in chip-on-board assemblies at 10-Gb/s. Each driver IC included a pre-driver with optimized performance. The output load for all drivers was 50 . A 20-dB attenuator was

Fig. 10. Die photomicrograph of driver 3.

Fig. 11. Measured eye diagram of driver 3 at 10 Gb/s.

added to avoid overloading the high-speed oscilloscope. Fig. 8 shows the die micrograph of Driver 1. The IC occupies a chip area of m and the active die area is smaller than

m . The input data stream was a mV

non-return-to-zero (NRZ) pseudorandom bit sequence (PRBS). A wideband bias-T was employed to establish a common-mode level of 6–7 V at the driver output. Fig. 9(a) and (b) show the measured electrical eye diagrams of Driver 1 and Driver 5, respectively. They both showed good characteristics at 10 Gb/s. Both driver ICs achieved a single-ended output swing of 4.5 . The rise/fall times of Driver 1 and Driver 5 were 27/29 ps and 25/27 ps, with jitters of 15 ps and 13 ps , and power consumptions of 0.8 W and 1 W, respectively. The measured BER at single-ended input amplitude larger than 100 mV is less than . Fig. 10 shows the die micrograph of Driver 3. The IC occupies a chip area of 900 750 m . The

input data stream was an mV NRZ PRBS. A

wideband bias-T was employed to establish a common-mode level of 4–5 V at the driver output. Fig. 11 shows the measured electrical eye diagram at 10 Gb/s. A single-ended (S.E.) output swing of 4 was achieved with power consumption as low as 0.6 W. The jitter was 14 ps . The measured BER at input am-plitude larger than 800 mV is less than . A comparison with some previously reported silicon-based modulator drivers is given in Table I. Driver 3 could be used as a laser driver when a 75- off-chip termination resistor was connected from the

Fig. 12. Optical measurement setup block diagram.

Fig. 13. (a) Electrical and (b) filtered optical eye diagrams for driver 3 for 10 Gb/s.

output end to common-mode level . Fig. 12 shows the block diagram of 10-Gb/s optical measurement setup. The driver directly modulates a commercial 1310-nm-wavelength MQW DFB laser diode. A golden 1310-nm O/E converter receives optical data streams emitted from the laser. Fig. 13(a) shows the electrical eye diagram for single-ended output swing of 2 at 10 Gb/s. Fig. 13(b) shows the corresponding optical eye diagram filtered with a 10-Gb/s fourth-order Bessel–Thomson filter, overlaid with the STM-64/OC-192 transmitter optical eye mask. It is clear that the optical eye stays well within the STM-64/OC-192 transmitter mask.

IV. JITTERANALYSIS

Theoretical random jitter analysis for broadband am-plifiers has been derived in [13]. However, to measure an accurate random jitter data, we need an elaborate process to exclude the oscilloscope trigger-delay jitter. From [14], the more accurate signal voltage is equal to

, where and represent the measured voltage and the slew rate of the output signal of the drivers, and , , and

Fig. 14. Measured output signal histogram of driver 1.

Fig. 15. Measured output amplitude.

represent the measured voltage, the measured voltage in average mode, and the slew rate of the reference clock used to exclude to trigger-delay jitter, respectively. Choosing the data out of the pattern generator to be a one zero pattern, and after a process described in [14], the device-under-test (DUT) signal without any trigger-delay jitter is obtained. Fig. 14 shows a measured output signal histogram of Driver 1. From this os-cilloscope reading the random jitter measurement of the DUT signal is about 0.65 ps and 4.9 ps . This measurement has trigger-delay jitter removed.

Fig. 15 shows the measured (S.E.) output amplitudes versus amplitude of input voltage. It is clearly that Driver 1 has wider input dynamic range and has better sensitivity owning to the larger of SiGe BiCMOS devieces.

Fig. 16 shows the measured rms output jitter of Driver 1 and Driver 3 versus the amplitude of input voltage with one zero pattern. The Driver 1 maintains a 4.5 S.E. output amplitude across a wide range of input signal levels (100 mV to 2 ), whereas the Driver 3 maintains 4 S.E. output amplitude in range from 800 mV to 2 . The random jitters of both drivers are less than 0.7 ps within the valid input range.

V. CONCLUSION

In this paper, 0.35- m SiGe BiCMOS and 0.18- m CMOS modulator drivers with low power and high output swings were proposed. The measured eye diagram shows good characteris-tics at 10 Gb/s. The novel ICBCFN and the advantage of cascode topology allows the power consumption to be only 0.8 W and the differential output swing to be 9 with a jitter less than 15 ps . It can also be applied to the SCVB circuit topology to

Fig. 16. Measured rms output jitter of driver 1 and driver 3 versus the amplitude of input voltage.

implement drivers with a differential output swing of 9 and a jitter less than 13 ps . The power consumption is greatly re-duced from 2 W with SCVB to only 1 W. The ICBCFN was modified as an IDGFN to implement drivers in CMOS tech-nology. The power consumption is only 0.6 W and the differ-ential output swing is 8 with a jitter less than 14 ps . The random jitters for both type of drivers are less than 0.7-ps . The drivers could be used as a laser driver when a 75- off-chip termination resistor was used. The measured BERs are less than within the valid input range. The measured optical eye diagram stays well within the 10-Gb/s Ethernet transmitter mask. To the knowledge of the authors, the proposed drivers consume the lowest power and occupy small areas with a differ-ential output swing of over 8 , and the output swing spans more widely than the previously reported silicon-based modu-lator drivers.

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Day-Uei Li was born in Chiayi, Taiwan, R.O.C.,

on May 6, 1970. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, in 1992, and the Ph.D. degree from the same university in 2000.

In 2001, he joined SoC Technology Center, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan, where he is presently working on high-speed physical layer circuits for fiber-optic communication systems and high-speed A/D con-verters for ultra-wideband communication systems. His current research interests include finite element methods, the development of numerical methods for modeling optical waveguides and waveguide devices, and mixed-signal IC design.

Chia-Ming Tsai was born in Tainan, Taiwan,

R.O.C., in 1967. He received the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1991 and 1997, respectively.

He then joined the Opto-Electronics and Systems Laboratories, Industrial Technology Research Insti-tute (ITRI), Hsinchu, Taiwan, as a designer for opto-electronic devices. In 2000, he joined the SoC Tech-nology Center, ITRI, as an analog IC designer. Since July 2005, he has been with the Department of Elec-tronics Engineering of National Chiao-Tung University as an Assistant Pro-fessor. His research interests are in the area of high-speed integrated circuits and optoelectronic devices. He is currently working on analog front-end design for fiber communication applications.