Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks

Timing Jitter and Modulation Profile Extraction

for Spread-Spectrum Clocks

Jenchien Hsu and Chauchin Su, Member, IEEE

Abstract—This paper presents a built-in jitter measurement

ap-proach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach. Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is pro-posed to correlate SSC and non-SSC jitter. A 1.2-GHz eight-phase SSC generator with the jitter measurement circuit is designed and fabricated using the 0.18-μm complementary metal–oxide– semiconductor technology. The measured results are validated by the proposed estimation method, which is the key contribution of this paper. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026 UI.

Index Terms—Analog testing, built-in self test, jitter, jitter

measurement, phase-locked loop (PLL), spread-spectrum clock (SSCs).

I. INTRODUCTION

A

CCURATE jitter measurement for high-speed serial links is extremely challenging. Such a measurement is costly, because it requires instruments with excellent timing accuracy and a long test time to ensure a low bit error rate (BER). To reduce the testing cost, a built-in self test (BIST) is considered a feasible alternative.

Conventionally, BIST circuits use time-to-digital converters (TDCs) to compare the phase difference between a generated clock and reference clock [1]–[7]. The resolution of TDCs determines the accuracy of jitter measurement results. There-fore, self-calibration techniques have been implemented to improve resolution [8], [9]. Unfortunately, a spread-spectrum clock (SSC) has a frequency deviation due to a predefined modulation profile that attenuates the peak power (see Fig. 1). The phase variation of the SSC includes jitter and phase drifting that result from the designed frequency deviation. Separating them by conventional TDC approaches or external instruments is difficult. The phase drifting that was caused by the frequency modulation is deterministic jitter, and the deterministic jitter and random jitter separation algorithm [10] can be used to separate them. However, if the phase drifting is larger than 1UI, the histogram becomes flat and meaningless. It happens for most SSCs. Furthermore, even if deterministic jitter can be separated from random jitter, the SSC phase drifting and

Manuscript received February 12, 2009; revised April 1, 2009. First published September 22, 2009; current version published March 20, 2010. The Associate Editor coordinating the review process for this paper was Dr. Jesús Ureña.

The authors are with the Department of Electrical and Control Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: dennyshu@ mail2000.com.tw).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIM.2009.2025992

Fig. 1. (a) Modulation profile. (b) PSD of the SSC.

deterministic jitter induced by other components of the phase-locked loop (PLL) cannot be separated, because they are all deterministic jitter. Notably, the SSC phase drifting is a low-frequency signal that is not crucial for receivers to recover the data, but other high-frequency deterministic jitter is important; thus, separating different types of deterministic jitter is nec-essary. The timing jitter of SSCs cannot be measured using traditional approaches; thus, spectrum analyzers are frequently used to measure the power spectrum of SSCs to roughly esti-mate signal quality. The self-trigger function of oscilloscopes is typically utilized to measure period jitter. However, the period jitter is not useful for estimating BER.

The timing jitter is more appropriate for BER estimation than the period jitter [11]; thus, Serial Advanced Technology Attachment (SATA) develops a timing jitter measurement methodology [12] (see Fig. 2). Jitter is defined as the time difference between a recovered clock and a data edge. The clock recovery circuit has a low-pass transfer function with a corner frequency of fBAU D/500 or fBAU D/1667, depending on the

application, where fBAU D is the nominal rate of data through

the channel. However, jitter includes the transmitted jitter and the jitter that was induced by the clock recovery circuit when an ideal recovery circuit is not used. Moreover, an additional clock recovery circuit is needed when using this methodology.

There are two prior arts of BIST circuits for measuring jitter of SSCs [13], [14]. In [13], the modulation profile and period jitter of SSCs were measured. However, the resolution was insufficient, and the period jitter did not comply with the SATA standard. In [14], a BIST methodology for measuring the timing jitter and the modulation profile of SSCs was proposed. How-ever, the BIST methodology was not validated using objective external instruments. In this paper, the measured results are validated by the estimation based on the measured results using external instruments. The estimation methodology is the key contribution of this paper.

The remainder of this paper is organized as follows. Section II presents the BIST methodology. Section III describes

Fig. 2. Jitter measurement methodology.

Fig. 3. Proposed BIST methodology.

the jitter estimation method that correlates non-SSC and SSC jitter based on the measurement results of external equipments. In Section IV, chip implementation and measured results are given. Finally, conclusions are drawn in Section V.

II. BIST METHODOLOGYOVERVIEW

Fig. 3 shows an SSC generator (SSCG) and the proposed BIST methodology. A triangular waveform is generated according to the modulation profile of a 5000-ppm down-spreading and a 30-kHz modulation frequency [see Fig. 1(a)]. The sigma−delta modulator (SDM) is used to control the ten-phase five-stage voltage-controlled oscillator (VCO) such that it oscillates in accordance with the modulation profile.

The BIST module is composed of hardware and software. The hardware comprises a ten-phase multiphase phase detector (MPD) (see Fig. 4). The MPD uses 10-D flip-flops (DFFs) to compare the reference clock to the ten clock phases that were generated by the VCO. The reference clock is used as a triggering signal of the DFFs, and the ten clock phases are the signals being sampled. When the clock edge of the reference clock comes, the ten clock phases are sampled, and the DFFs output a 10-b thermal meter code. The transition bit of the thermal meter code represents the detected phase. The phase-shift detector detects the phase phase-shift by comparing the detected phases at the first and the next triggering times. One example is shown in Fig. 5. Phase 5 is sampled by the first reference clock edge, and Phase 7 is sampled by the next reference clock edge. A phase shift of 0.2 UI is detected. Notably, if the frequency deviation of the SSC is very large, the phase shift may exceed 1 UI. If so, a faster reference clock is needed. When the frequency deviation is 6 MHz (5000 ppm) with a reference

Fig. 4. MPD.

Fig. 5. Timing diagram of the MPD.

Fig. 6. BIST methodology model.

clock period of 50 ns, the phase shift is 0.3 UI. The next step in phase detection is to accumulate each phase shift to recover the absolute phase. Notably, without jitter, the accumulated phase is the integration of the modulation profile [see Fig. 1(a)]. The modulation profile is the timing diagram of the SSC frequency; thus, the integration of frequency in time is the absolute phase. The software in the BIST modules comprises a digital signal processing (DSP) program that utilizes the on-chip DSP or microprocessor to extract jitter and the modulation profile after obtaining the accumulated phase using the MPD. Conceptually, the modulation profile can have a frequency that is as low as 30 kHz. Therefore, a low-pass filter (LPF) can extract the modu-lation profile from the accumulated phase. The high-frequency components of jitter are defined by the SATA standard. Therefore, jitter can be obtained using a high-pass filter (HPF). Notably, additional DSP functions are required to acquire the modulation profile and jitter after filtering. Fig. 6 shows the jitter measurement model, where φSSCis the ideal accumulated

phase. Two added noise sources are given as follows: 1) jitter φJand 2) MPD phase quantization noise φE. The methodology

has two processing paths: 1) the HPF path for jitter measure-ment and 2) the LPF path for modulation profile extraction.

For jitter measurement, the accumulated phase passes through the HPF. After that, only high-frequency components φJ H+EH remain, where JH is the high-frequency jitter and

EH is the high-frequency quantization noise. The power spectral density (PSD) function of high-frequency components

SφJ H+EH can be obtained by taking the square of the fast Fourier transform (FFT) as follows:

SφJ H+EH(f ) = F F T

2_(φ

J H+EH(t)) . (1)

Jitter variance or jitter power is the integration of SφJ H+EH in the frequency domain. We have

φ2_{J H+EH,RM S} =

f ref /2_ −fref/2

SφJ H+EH(f )df (2)

where fref is the reference clock frequency, and RMS is root

mean square value. Because fref is the sampling rate of MPD,

the frequency band of the signals within the BIST circuit does not exceed the range of half of fref based on DSP theories.

Jitter and quantization noise are independent random variables; thus, the jitter variance can be obtained by

φ2_{J H,RM S} = φ2_{J H+EH,RM S}− φ2_{EH,RM S}. (3) The quantization noise is typically regarded as white noise; thus, its PSD is SφE= Δ2 M P D 12· fref . (4)

The transfer function of the HPF is known; thus, φEH,RM S

is obtained as

φ2_{EH,RM S}=

fref /2

−fref/2

|HHP F(j2πf )|2· SφEdf. (5)

The modulation profile is extracted using the LPF. After the accumulated phase that passes through the LPF, only the low-frequency component φSSC+J L+EL remains, where

JL is the low-frequency jitter, and EL is the low-frequency quantization noise. φSSC+J L+EL approximates φSSC,

because the low-frequency jitter is relatively small. Most of the low-frequency jitter of the VCO is filtered out by the PLL, because the PLL acts like an HPF for VCO noise. Most high-frequency components of quantization noise are filtered out by the LPF. As mentioned, the accumulated phase shift is the integration of the modulation profile in time. Now, by taking the reverse operation, the derivative of φSSC+J L+EL

generates the modulation profile. We have f (t) =dφSSC+J L+EL(t)

dt . (6)

Using (1)–(6), the jitter and modulation profile can be extracted from the accumulated phase that was obtained by the MPD.

The next step is to validate the extracted result. Without dedicated SSC timing jitter measurement instruments, verifying that such a methodology can effectively measure SSC jitter is difficult. In Section III, this paper derives an equation that correlates the timing jitter in the SSC and non-SSC modes of the same PLL. In the non-SSC mode, jitter can be measured by

Fig. 7. Noise model of the SSCG.

external instruments. SSC jitter is estimated using measured results from the non-SSC mode and the derived equation. Thus, this paper can cross check and validate both the BIST methodology and the jitter estimation method.

III. SSC JITTERESTIMATION

In this section, a jitter estimation method that correlates a non-SSC timing jitter and the corresponding SSC jitter is used to validate the BIST methodology. One equation for SDM noise calculation is also presented for the specific SSCG in this paper. The SSCG is made by a fractional-N PLL with a triangular modulation profile. Some prior arts have developed the jitter estimation methods for fractional-N PLLs [15], [16]. In these studies, a PLL is modeled as an ideal filter, and a common SDM is used. However, a PLL has a peak in the transfer function, which increases the jitter magnitude. In addition, the SDM in this paper is special such that a common analysis is not applicable. A more accurate model and a dedicated analysis are presented as follows.

Fig. 7 shows the noise model of an SSCG circuit with a third-order loop filter. Based on spectral analysis, the output jitter PSD of the SSCG and noise sources are related as follows:

SΦP LL(f ) = SΦP LLΣΔ(f ) + SΦP LLV CO(f ) =|HΣΔ(j2πf )|2· SΦΣΔ(f )

+|HV CO(j2πf )|2· SΦV CO(f ) (7) where SΦP LL is the PSD of the PLL output jitter. SΦP LL is composed of SΦP LLΣΔ(f ) and SΦP LLV CO(f ), i.e., the PSDs of the PLL output jitter caused by the noise from the SDM and VCO. In addition, SΦΣΔ and SΦV COare the PSDs of the SDM and VCO noise, respectively, and HΣΔ and HV CO are the

transfer functions from noise sources φΣΔ and φV CO to the

PLL output, respectively. With this information, SΦP LLcan be derived by (7). The RMS jitter is calculated as

φ2_{J,RM S}=

∞



−∞

SΦP LL(f )df. (8)

The high-frequency RMS jitter is calculated as

φ2_{J H,RM S} =

∞



−∞

|HHP F(j2πf )|2· SφP LLdf. (9)

Next, the derivation and calibration of SΦΣΔ, HΣΔ(s),

A. Derivation ofHV CO(s) and HΣΔ(s)

Transfer functions HΣΔ(s) and HV CO(s) are defined as

HΣΔ(s) = φP LLΣΔ(s) φΣΔ(s) =− G(s) 1 + G(s) (10) HV CO(s) = φP LLV CO(s) φV CO(s) = 1 1 + G(s) (11)

where φP LLΣΔand φP LLV COare the PLL output phases that

were caused by the SDM and VCO noise, respectively. The open-loop transfer function G(s) is

G(s) = KdF (s)KV CO

sN (12)

where Kd and KV CO are the gains of the phase detector and

the VCO, respectively, and N is the division ratio. The transfer function of the loop filter F (s) is defined as

F (s) ∼= Kh(s + z1) s  s p1 + 1   s p2 + 1 . (13)

The gain, zero, and poles of the third-order loop filter are Kh= C2R2 C1+ C2 z1= 1 C2R2 p1= C1+ C2 C1C2R2 p2= 1 C3R3 . (14)

HΣΔ(s) and HV CO(s) deviate from the design target due

to the process variation. A proposed calibration flow is used to calibrate the parameters of the transfer functions. First, we assume that all capacitance and resistance values shift in the same ratio under process variation by factors k1 and k2,

respectively. The values of the poles and the zero proportionally deviate with a factor α, where α is related to k1and k2as

α = 1

k1k2

. (15)

The poles and zero can be written as

z1= αz1o p1= αp1o p2= αp2o (16)

where z1o, p1o, and p2o are the design target. By substituting

(13) and (16) into (12) and transforming (12) into the frequency domain, G can be rewritten as

G =KdF (j2πf )KV CO j2πf N = Ko· Ho(α, f ) = FG(K0, α, f ) (17) where Ko= KdKV COKh N (18)

and H is the remaining part of G. From this derivation, G is a function of Ko, α, and f . Thus, HV CO is also a function

of Ko, α, and f , i.e.,

HV CO= FHV CO(K0, α, f ). (19) One can approximately define the natural frequency fn as

the frequency at which the maximum gain of HV CO occurs.

The natural frequency fn is obtained by solving the following

equation:

∂

∂f |FHV CO(K0, α, f )| = 0. (20) Based on (19) and (20), fnis a function of K0and α, i.e.,

fn= Ffn(K0, α). (21)

Rearranging (21) shows that constant K0is a function of α

and fn, i.e.,

K0= FK0(α, fn). (22)

By substituting (22) into (19), HV COis a function of α, fn,

and f , i.e.,

HV CO= FHV CO(α, fn, f ). (23) This relation means that, when the natural frequency and process variation factor α are known, HV COand HΣΔ can be

derived. fnand α are obtained using the following method. We

assume that the output phase noise of a PLL in the non-SSC mode is dominated by VCO noise and the output phase noise of the PLL and VCO noise are related as follows:

SΦP LL,nonSSC= SΦV CO(f )· |HV CO(j2πf )|

2

(24) where SΦP LL,nonSSC(f ) is the PSD of the PLL output jitter in the non-SSC mode. The charge pump current of the phase detector determines the phase detector gain Kdand the values

of Koand fnin (17) and (21), but the value of α is not affected

by the charge pump current. When the charge pump current is changed, the phase noises with different natural frequencies fn1 and fn2 are produced. Notably, the charge pump current

is affected by process variation, and it is difficult to know its exact values. However, knowing the exact values of charge pump current is not necessary. The parameter of the charge pump current is included in the natural frequency, as shown in (21), and the natural frequency can be observed by a spectrum analyzer. It is the same reason that knowing the exact values of other parameters, e.g., the VCO gain, is not necessary. The non-SSC jitter PSD and transfer functions are related as follows: SΦP LL1,nonSSC= SΦV CO(f )· |FHV CO(α, fn1, f )| 2 (25) SΦP LL2,nonSSC= SΦV CO(f )· |FHV CO(α, fn2, f )| 2 . (26) This paper divides (26) by (25) to eliminate the VCO noise. We have SΦP LL2,nonSSC SΦP LL1,nonSSC = |FHV CO(α, fn2, f )| 2 |FHV CO(α, fn1, f )| 2. (27)

The equation is expressed in log scale as follows: ΔS = 10 log(SΦP LL2,nonSSC) − 10 log(SΦP LL1,nonSSC) = 10 log  |FHV CO(α, fn2, f )| 2 − 10log|FHV CO(α, fn1, f )| 2 = ΔH2(α, fn1, fn2, f ) (28)

where ΔH2_{is the difference between two transfer functions in}

log scale, and ΔS is the difference between PSDs in log scale measured by a spectrum analyzer. The value of α is calibrated as follows. Using the originally designed charge pump current, fn1is measured. Next, the charge pump current is increased to

obtain fn2 and ΔS. If fn1, fn2, ΔS, and f are known, α can

be calculated using (28). To increase the calibration accuracy, several fn2and ΔS are obtained by again increasing the charge

pump current and using a curve-fitting procedure to determine the value of α that best satisfies (28).

B. Derivation ofSΦΣΔ

Fig. 8 shows the SSCG under test [17]. A ten-phase clock is generated and fed into the multiplexer (MUX). The SDM and MUX select a suitable phase shift according to the frequency deviation determined by the given modulation profile. The divi-sion ratio for a 20-MHz reference clock and a 1.2-GHz output clock is 60. The phase shift is 0.1UI, which is confined with the division ratio of 60; thus, the frequency deviation is 0.167%. This value is 33% of the 5000-ppm frequency deviation. Thus, the phase-shift speed must increase by 300%, and the SDM must operate at 300% of the reference clock rate to achieve a 5000-ppm frequency deviation. The data rate of the SDM is 300% of the frequency of the reference clock and the divider output; thus, three consecutive data of SDM are summed in one reference clock period. The equivalent output of the SDM is the sum of three consecutive data of the original SDM.

The output signal of the SDM is denoted as x[n], and the sum of three consecutive data is

y[k] = x[3k− 2] + x[3k − 1] + x[3k]. (29) It can be regarded as a three-time downsampling of the moving sum x[n], i.e.,

x[n] = x[n− 2] + x[n − 1] + x[n]. (30) The PSD of the noise at the output of a MASH-111 SDM is

SQE(z) =(1− z−1)3

2

· SE (31)

where SE is the quantization noise in the SDM with the

following probability density function: SE=

Δ2

12fs

(32)

Fig. 8. The SSCG structure with multiphase selection.

where Δ is 1 least significant bit of the quantizer or 0.1 UI for a ten-phase MUX; fs is 300% of the reference clock rate.

We have

fs= 3fref. (33)

In addition, (31) is transformed into the frequency domain as SQE(f ) = Δ2 16 3fs sin6  πf fs  . (34)

The PSD of the moving sum is

SQE1(z) =|1 + z−1+ z−2|2· SQE(z). (35)

The PSD of the moving sum is transformed into the fre-quency domain as SQE1(f ) =  3 + 4 cos  2πf fs  + 2 cos  4πf fs  · SQE(f ). (36) After downsampling thrice, the PSD of y[k] is

SQE2(f ) = SQE1(f ) + SQE1

 f +fs 3  + SQE1  f +2· fs 3  . (37) The PSD of the equivalent noise at the divider input is calculated as SΦΣΔ(z) =  _{1− z}1 −1  2· SQE2(z). (38)

The PSD of the equivalent noise at the divider input is transformed into the frequency domain as

SΦΣΔ(f ) = 1 4 sin2  πf fref  · SQE2(f ). (39) C. Derivation ofSΦV CO

The next step is to estimate the VCO noise. We assume that the PSD of the VCO noise is

SΦV CO(f ) = AV CO

Fig. 9. Jitter estimation and calibration flow.

The jitter of the non-SSC and the PSD of the VCO noise are related as follows: φ2JnonSSC,RMS= ∞  −∞ |HV CO(j2πf )|2· SΦV CO(f )df = ∞  −∞ |HV CO(j2πf )|2· AV CO f2 df. (41)

After measuring the RMS jitter of the non-SSC,

φJnonSSC,RMS, AV COcan be obtained by (41).

Fig. 9 shows the jitter estimation and the calibration flow. First, the phase noise of the non-SSC is measured, and the natural frequency and peak values at the natural frequency are observed from the phase noise diagrams. Then, the charge pump current is increased, and the phase noise is again mea-sured to identify another natural frequency and the peak value. Using these measured parameters and (28), α, which represents pole/zero deviations due to process variation, is calibrated. To increase the estimation accuracy, this step can be repeated several times for the curve-fitting procedure. The SDM noise is theoretically obtained. The RMS jitter of the non-SSC is measured by an oscilloscope, and (41) is applied to obtain the PSD of the VCO noise. After all the parameters are acquired, (7) is used to calculate the jitter PSD and its RMS value.

Fig. 10 presents a chip photograph of this paper and its summary. The technology used is a 0.18-μm complementary metal–oxide–semiconductor (CMOS) with a supply voltage of 1.8 V. The BIST circuit area is 15% of the SSCG, which includes the DFFs and phase-shift detector of the MPD but does not include the accumulator or other digital circuits. The BIST is operated at 20 MHz, which is the same as the reference clock frequency. The SSCG is a fractional-N PLL with a ten-phase 1.2-GHz VCO, a third-order loop filter, and a MASH-111 SDM to meet the SATA-III specification. In total, 104 data outputs by the phase-shift detector are recorded by a logic analyzer. A personal computer is used for digital signal processing. The SSC and non-SSC are measured using a spectrum analyzer and oscilloscope.

Fig. 10. Chip photograph.

IV. EXPERIMENTAL ANDMEASUREMENTRESULTS

Fig. 11 shows the power spectrums measured using a spec-trum analyzer of a non-SSC and an SSC. Measured results indicate that the non-SSC has a frequency of 1.2 GHz and the SSC has a maximum frequency deviation of 6 MHz (5000 ppm) from a nominal frequency of 1.2 GHz.

Fig. 12 shows the phase-shift detector outputs. As expected, a 6-MHz frequency deviation in a 50-ns reference clock period causes a maximum phase shift of 0.3 UI. With noise, an additional phase shift of 0.1 UI can be generated. Fig. 13 shows the accumulated phase, which includes the ideal SSC phase drifting, phase quantization noise that was produced by the MPD, and jitter. The MPD output is passed through the digital filters and DSPs for further analysis. Fig. 14 shows the SSC modulation profile of the SSC obtained using a fifth-order infinite impulse response (IIR) LPF with a corner frequency of 500 kHz. The corner frequency is selected to filter out as much noise as possible to retrieve the SSC phase and its harmonics. The measurement results for the BIST show that the frequency deviation is 6.1 MHz, which is in agreement with the value that was measured by the oscilloscope (see Fig. 11). The modulation frequency is 29.4 kHz compared with the design target of 29.3 kHz.

The calibration process is explained as follows. First, the phase noise of the non-SSC of the PLL is measured. Second, the charge pump current is increased, and the phase noise is again measured. The natural frequencies are observed from these two phase noise diagrams. Fig. 15 shows the phase noise of the non-SSCs with natural frequencies of 0.4 MHz (fn1)

and 0.9 MHz (fn2), as defined in (28). The frequency f is

chosen to equal fn2. Comparing the phase noise at 0.9 MHz

(fn2), the difference in phase noise ΔS is 2 dB. For the

curve-fitting procedure, one should repeat this step several times with different charge pump currents. Fig. 16 shows the case with an fn2of 2.2 MHz. In this case, ΔS is 18 dB at 2.2 MHz.

Fig. 17 shows the curve-fitting procedure; the y-axis is ΔH2_,

and the x-axis is the natural frequency fn2. In addition, fn1 is

fixed at 0.4 MHz, and the f chosen is fn2. Curves with different

values of α are shown. The most appropriate value of α is 0.85 in this case. The calibration of the VCO noise is presented as follows. Fig. 18 shows the non-SSC jitter with a natural frequency of 0.4 MHz, which is measured by the oscilloscope. The measured RMS jitter is 12.59 ps; thus, AV CO in the PSD

Fig. 11. PSD of the non-SSC clock and SSC measured using a spectrum analyzer.

Fig. 12. Phase-shift detector output signal.

Fig. 13. Accumulator output signal.

SDM noise is also analyzed using (29)–(39). The SSC has ten phases; the frequency of the reference clock is 20 MHz, and the frequency of the SDM is 60 MHz. Fig. 19 shows the estimated SΦE(f ), SΦP LLV CO(f ), and SΦP LLΣΔ(f ). Each line represents the PSD of the jitter with different charge pump currents. The natural frequencies in this figure are 0.1–2.3 MHz. Notably, the optimal bandwidth of the PLL is 0.2 MHz in this paper. If the bandwidths exceed the optimal bandwidth, jitter increases as natural frequency increases.

Fig. 14. Modulation profile of the SSCG.

Fig. 15. Phase noise of non-SSC clocks with natural frequencies of 0.4 and 0.9 MHz.

Figs. 20–22 show the estimated and measured values of PSDs of the HPF output signal SΦJ H+EH(f ) in (1) for different natural frequencies. The estimated jitters (thick lines) are the sum of the PSD of the SDM noise, VCO noise, and quantization noise (thin lines). The measurement results are acquired from the HPF outputs. A fifth-order IIR HPF with a corner frequency of 500 kHz is utilized. The corner frequency of 500 kHz is chosen to filter out most of the SSC 30-kHz phase drifting and its harmonics caused by the frequency modulation. Using

Fig. 16. Phase noise of non-SSC clocks with natural frequencies of 0.4 and 2.2 MHz.

Fig. 17. Curve-fitting procedure for the calibration of transfer functions.

Fig. 18. Non-SSC jitter with a natural frequency of 400 kHz.

calculation tools, it is estimated that a 500-kHz fifth-order HPF can filter out most of the unwanted SSC phase drifting with a modulation frequency of 30 kHz. The unfiltered phase drifting is 0.003 UI (RMS), which causes a 1% error when the jitter being measured is, for example, 0.02 UI (RMS). If the corner frequency is decreased to 400 kHz, the error increases to 4%. Therefore, a corner frequency of 500 kHz is chosen if an error below 1% is required. The BIST results of the SSCs are in good agreement with the estimated results based on the phase noise of the non-SSC measured by a spectrum analyzer (see Figs. 15 and 16) and the RMS jitter measured by an oscilloscope (Fig. 18).

Fig. 23 shows the histogram of the jitter plus high-frequency phase quantization noise calculated based on the HPF output.

Fig. 19. Theoretical PSDs of the jitter and phase quantization noise.

Fig. 20. Theoretical and measured PSDs of jitters (fn= 0.4 MHz).

Fig. 21. Theoretical and measured PSDs of jitters (fn= 0.9 MHz).

The RMS jitter can statistically be obtained from the histogram. For experimental purposes, a fifth-order HPF with a corner frequency of 500 kHz and a third-order HPF with a corner frequency of 3.6 MHz are used. The latter HPF complies with the SATA standard, which requires fBAU D/1667, where

fBAU D is 6 Gbps. Fig. 24 shows the BIST and estimation

results. Table I lists the BIST and estimation result for the 3.6-MHz case, which complies with the SATA standard. The maximal error is 0.026 UI. Such errors are systematic errors, because all measured results exceed the estimated ones. This result may be due to the phase imbalance of the multiphase

Fig. 22. Theoretical and measured PSDs of jitters (fn= 2.2 MHz).

Fig. 23. Jitter histogram measured by BIST (fn= 0.4 MHz).

Fig. 24. Jitter RMS value: BIST versus estimation results.

clock. Such an imbalance generated additional phase noise at the MPD output. Notably, the estimation result is based on the non-SSC, which does not involve the multiphase clock. If phase imbalance is considered, (3) can be modified as

φ2_{J H,RM S}= φ2_{J H+EH+P IM,RM S}− φ2_{EH,RM S}− φ2_{P IM,RM S} (42) where φP IMis the phase imbalance noise, and PIM is the phase

imbalance. Comparing the estimation and BIST results and using linear regression to estimate the unknown term φP IM,

the phase imbalance noise is likely to be 0.0053 UI. However,

TABLE I

COMPARISON OFMEASUREDRMS JITTER ANDESTIMATEDVALUESTHAT

MEET THESATA STANDARD

this noise cannot individually be tested or calibrated; thus, the phase imbalance noise puts a limit to the measurement range of this BIST approach.

V. CONCLUSION

This paper has presented the feasibility of a built-in jitter measurement method for multiphase SSCGs. This method is based on a ten-phase MPD and DSP algorithms for extracting the jitter histogram and PSD, with the timing jitter definition complying with the SATA standard. The method for measuring the modulation profile, which includes modulation frequency and frequency deviation, is also presented. The jitter estimation method that correlates SSC jitter and non-SSC jitter is used to validate the jitter measurement methodology. A 1.2-GHz ten-phase SSC PLL with the proposed jitter measurement circuit was designed and implemented using the 0.18-μm CMOS technology. Measurement results show that the errors of the estimation and BIST results are less than 0.0026 UI.

REFERENCES

[1] S. Sunter and A. Roy, “BIST for phase-locked loops in digital applica-tion,” in Proc. Int. Test Conf., 1999, pp. 532–540.

[2] N. Abaskharoun and G. W. Roberts, “Circuits for on-chip subnanosec-ond signal capture and characterization,” in Proc. IEEE Custom Integr. Circuits Conf., 2001, pp. 251–254.

[3] S. Cherubal and A. Chatterjee, “A high-resolution jitter measure-ment technique using ADC sampling,” in Proc. Int. Test Conf., 2001, pp. 838–847.

[4] T. Xia and J. C. Lo, “Time-to-voltage converter for on-chip jitter mea-surement,” IEEE Trans. Instrum. Meas., vol. 52, no. 6, pp. 1738–1748, Dec. 2003.

[5] J. M. Cazeaux, M. Omana, and C. Metra, “Novel on-chip circuit for jitter testing in high-speed PLLs,” IEEE Trans. Instrum. Meas., vol. 54, no. 5, pp. 1779–1788, Oct. 2005.

[6] K. Ichiyama, M. Ishida, T. J. Yamaguchi, and M. Soma, “Data jitter measurement using a delta-time-to-voltage converter method,” in Proc. Int. Test Conf., 2007, pp. 1–7.

[7] J. Hsu and C. Su, “BIST for measuring clock jitter of charge-pump phase-locked loops,” IEEE Trans. Instrum. Meas., vol. 57, no. 2, pp. 276–285, Feb. 2008.

[8] B. Nelson and M. Soma, “On-chip calibration technique for delay-line-based BIST jitter measurement,” in Proc. Int. Symp. Circuits Syst., 2004, pp. 944–947.

[9] J. Rivoir, “Fully digital time-to-digital converter for ATE with au-tonomous calibration,” in Proc. Int. Test Conf., 2006, pp. 1–10. [10] Y. Cai, S. A. Werner, G. J. Olsen, and R. D. Brink, “Jitter testing for

multigigabit backplane SerDes,” in Proc. Int. Test Conf., 2002, pp. 1–10. [11] D. Hong, C. K. Ong, and K. T. Cheng, “Bit-error-rate estimation for

high-speed serial links,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 12, pp. 2616–2627, Dec. 2006.

[12] Serial ATA Revision 2.5, Serial ATA Int. Org., Beaverton, OR, Oct. 2005. [13] M. Chou, J. Hsu, and C. Su, “A digital BIST methodology for spread-spectrum clock generators,” in Proc. Asian Test Symp., 2006, pp. 251–254.

[14] J. Hsu, M. Chou, and C. Su, “Built-in jitter measurement methodology for spread-spectrum clock generators,” in Proc. IEEE Int. Symp. VLSI Des., Autom. Test, 2008, pp. 67–72.

[15] W. Rhee, B. S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1453–1460, Oct. 2000. [16] B. De Muer and M. S. J. Steyaert, “On the analysis of ΔΣ

fractional-N frequency synthesizers for high-spectral purity,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 50, no. 11, pp. 784–793, Nov. 2003.

[17] H. Lee, O. Kim, G. Ahn, and D. Jeong, “A low-jitter 5000-ppm spread-spectrum clock generator for multichannel SATA transceiver in 0.18/spl mu/m CMOS,” in Proc. Int. Solid State Circuits Conf., 2005, p. 162.

Jenchien Hsu received the B.S. and M.S. degrees

in electronic engineering from the National Central University, Chung-Li, Taiwan, in 2000 and 2003, respectively. He is currently working toward the Ph.D. degree, with a specialization in mixed-signal testing, in the Department of Electrical and Con-trol Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan.

Chauchin Su (M’90) received the B.S. and M.S.

degrees in electrical engineering from the National Chiao-Tung University, Hsin-Chu, Taiwan, in 1979 and 1981, respectively. He received the Ph.D. degree in electrical and computer engineering from the University of Wisconsin, Madison, in 1990.

He is currently with the Department of Electrical and Control Engineering, National Chiao-Tung University. His research interests include mixed analog and digital system testing and design for testability. He is also involved in projects on base-band and circuit design for wireless communications.