A new small-signal MOSFET model and parameter extraction method for RF IC's application

A new small-signal MOSFET model and parameter extraction

method for RF IC’s application

Kow-Ming Chang*, Han-Pang Wang

Department of Electronics Engineering, Institute of Electronics, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC Received 31 March 2004; revised 21 May 2004; accepted 1 June 2004

Available online 28 July 2004

Abstract

In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance gm; match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered.

q2004 Elsevier Ltd. All rights reserved.

Keywords: Gate resistance; RF MOSFET modeling; Substrate resistance; Nonreciprocal capacitance

1. Introduction

The majority of the radio-frequency integrated circuits (RFICs) are typically implemented by GaAs or silicon bipolar technologies [1,2]. Due to their high unity-gain cutoff frequency ðftÞ; GaAs devices and BJTs have been

generally used in high frequency applications. However, continuously scaling down of the minimum channel length and the consequent increase of ft have made CMOS

technology become an attractive one in applications for analog and RFICs [3]. With another advantage (i.e. high integration level and low cost budget, etc.) over GaAs and silicon bipolar technologies, CMOS technology is a good candidate to meet the demand of wireless telecommunica-tion system in the future.

As circuitry operates at higher frequency (GHz frequency range) and lower voltages, a major requirement for RF circuit design is the availability of RF MOS transistor model to describe the circuit behavior accu-rately. Besides, the establishment of an accurate par-ameters extraction method relevant to the RF model is essential.

In order to meet the requirement for an accurate RF model, several fundamental analyses on MOSFETs high frequency characteristics have been developed, as described in Refs. [4 – 6]. As MOSFETs operation frequency approaches VHF and beyond, the parasitic components geometry-related (e.g. inductance, capacitance and resist-ance) play important roles in their high frequency performance. Therefore, the nature of gate region—RLC distributed network and substrate parasitics should be considered in the development of RF MOS model. Some conventional models[7 – 9]replaced the gate region with a single resistance, and this would cause inaccuracy in predicting the gate related noise at high frequency [10]. Besides, in several models[10 – 12], the substrate parasitics were not taken into account, and this would hurt their accuracy in the prediction of output characteristics (i.e. output impedance [13]). In addition, several conventional models [13 – 15] excluded the nonreciprocal capacitance considering the charge conservation [16], and this would result in a significant error in predicting the imaginary parts of Y12and Y21:

Except for the development of an accurate RF model, a related parameters extraction methodology is indispensa-ble. Several methods of extracting small-signal equivalent

0026-2692/$ - see front matter q 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2004.06.001

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* Corresponding author. Tel.: þ886-3-5731887; fax: þ886-3-5731887. E-mail address: [email protected] (K.-M. Chang).

circuit parameters from the S-parameter measurement data have been reported [14,17,18]. However, most of them require complex curve fitting and optimization steps.

In this paper, we propose a high frequency analytical MOSFETs model well describing the distributed effects of the gate region and including substrate parasitics and nonreciprocal capacitance. Besides, a direct and accurate parameter extraction method for the proposed model including gate-related parameters, substrate-related par-ameters and nonreciprocal capacitor is also proposed. This study focuses on the development of a physics-based small signal MOSFETs model and an accurate parameter extrac-tion approach by Y-parameter analysis from measured S-parameters.

This paper is organized in the following manners. In Section 2, a new and accurate high frequency MOS transistor model is briefly described. This section begins with the assumptions and definitions, which are useful for the model development, and follows by describing the closed-form modeling equations. In Section 3, an accurate and direct method for the extractions of the parameters of small signal equivalent circuit is presented and explained in detail. In Section 4, the proposed model and related extraction method are verified by the experimental data. Finally, the conclusions are summar-ized in Section 5.

2. Small signal RF MOSFET model

In this section, a new and analytical small signal RF MOSFET model including distributed gate network, sub-strate parasitics and nonreciprocal capacitance is proposed. At first, the relative approaches and assumptions are briefly described and defined, respectively. Then, the derivation details of model equations will be described.

2.1. Approaches and assumptions

To accurately describe the fact that the signal travels across the gate in the form of incident and reflected EM waves[10], we use the concept of transmission line theorem to model the distributed nature of the gate region and the delay it causes in charging the gate capacitance. In addition, for the sake of simplicity and calculation efficiency, we add a lumped resistance to the bulk terminal to account for the substrate coupling effect. We also use the nonreciprocal capacitance to take into account the different effects of the gate and drain on each other in terms of charging currents

[16]. In order to describe the distributed nature of the gate region, a MOS transistor is viewed as an array of discrete transistors connected in parallel via gate resistances along the gate region, as illustrated in Fig. 1. The related small signal equivalent circuit is shown in Fig. 2which is based on the three-terminal configuration. In a three-terminal

configuration, the substrate is tied to the source, as in most high frequency applications [9,19]. This model is suitable for the case of zero source – substrate bias in circuit. Before developing expressions for the Y-parameters of the MOS transistors, the following assumptions have to be made:

Assumption 1. It is assumed that the DC bias condition remains the same along the gate width. This means that only AC small signals applied at the gate region needed to be considered. With this assumption, the discrete MOS transistors illustrated inFig. 1have the same small signal parameters (e.g. transconductance g_m; drain-bulk transcon-ductance gmb; etc.). To make the model equations clearly,

we use the prime-notation to stand for the parameters per width (i.e. X0 is used to represent the variable X per unit width) R0g¼ Rg W ð1Þ C0gd ¼ Cgd W ð2Þ C0gs¼ Cgs W ð3Þ g0m¼ gm W ð4Þ

where W is the channel width, Rgis the gate resistance, Cgd

and Cgsare the gate-to-drain capacitance and gate-to-source

capacitance, respectively, and gmb is the transconductance

of substrate.

Assumption 2.This assumption states that the electric field along the width of the device is significantly less than the fields existing along the channel length. Note that this condition is valid in most devices used for RF applications

where the gate width W is normally larger with respect to the gate length L:

Assumption 3. In order to develop an analytical model easily, the average voltage at the gate region is expressed as

v ¼ 1 W

ðW 0

vðxÞdx ð5Þ

where v is the average voltage at the gate region, and vðxÞ is the voltage at the location x along the gate region. Thus, the total current flowing in the channel can be expressed as: gmv ¼

ðW 0

g0mvðxÞdx ð6Þ

2.2. Analysis for new RF MOSFET model

In the primary step, we will decouple the feedback loops and find the loadings caused by the feedback networks at the input and output terminals. Then, the derivation of Y-parameters of MOSFETs will be expressed in the secondary step.

Step 1. The circuit configuration shown inFig. 2 is too complicated to be analyzed directly. Nevertheless, if the circuit is viewed as a dual-feedback circuit in which DCgdis

the local shunt – shunt feedback element forms the first feedback loop (i.e. loop A), where DCgd¼ C0gdDx represents

the gate – drain capacitance of the section Dx at the gate region, and Cdb; Csb; Rsub and C0gbDx are the local shunt –

shunt feedback elements form the second feedback loop (i.e. loop B), where DCgb¼ C0gbDx represents the gate – substrate

capacitance of the section Dx at the gate region, then the circuit becomes much easier to solve. The feedback loops A and B are illustrated inFig. 3, where V1and V2represent the

output voltage relative to ground (e.g. Vds) and the voltage Fig. 2. Small signal equivalent circuit of an MOSFET for RF modeling.

along the gate width shown inFig. 2, respectively. By local shunt – shunt feedback theory[20], the loading effects at the input and output terminals caused by the feedback networks shown in Fig. 3 can be expressed in the Y-parameter representation as follows Y11_;loopA¼ sCgd ð7Þ Y_12;loopA¼ Y21;loopA¼ 2sC 0 gdDx ð8Þ Y22;loopA¼ sC 0 gdDx ð9Þ Y11;loopB¼ sCdbð1 þ sRsubðCsbþ CgbÞÞ 1 þ sRsubCb ð10Þ Y12;loopB¼ Y21;loopB¼ 2 s2_R subCdbC0gbDx 1 þ sRsubCb ð11Þ Y22;loopB¼ sC0_gbDxð1 þ sRsubðCsbþ Cdbþ Cgb2 C0gbDxÞÞ 1 þ sRsubCb ð12Þ where Cdb; Csb and Cgb are the drain-to-substrate

capaci-tance, source-to-substrate capacitance and gate-to-substrate capacitance, respectively, C0gdand C0gbare the gate-to-drain

capacitance per unit width and gate-to-substrate capacitance per unit width, Rsub is the substrate resistance, and Cbis the

sum of Cgb; Cdband Csb:

Then, with the local shunt – shunt feedback theory mentioned above, the circuit inFig. 2can be transformed into the one in Fig. 4. In Fig. 4, some components (i.e. Y0_12;loopA; Y0_21;loopA; Y0_22;loopA; Y0_12;loopB; Y0_21;loopBand Y0_22;loopB) in the Blocks A and B are referred to as the per-unit width

components and expressed as

Y012;loopA¼ Y 0 21;loopA¼ 2sC 0 gd ð13Þ Y022;loopA¼ sC 0 gd ð14Þ Y012_;loopB ¼ Y021_;loopB ¼ 2 s2RsubCdbC0gb 1 þ sRsubCb ð15Þ Y022;loopB¼ sC0gbð1þsRsubðCsbþ CdbþCgb2C0gbDxÞÞ 1 þsRsubCb <sC 0 gbð1þsRsubðCsbþCdbþ CgbÞÞ 1þsRsubCb ¼ sC0gb ð16Þ

where Dx is an infinitesimal section of the gate width. Step 2. In the derivation procedure of Y-parameters, the complete small-signal equivalent circuit of Fig. 4 is analyzed as a two-port circuit with input at the gate and output at the drain and both the source and substrate terminals are grounded. Then, due to the distributed RC network along the gate region, the equivalent circuit can be analyzed by transmission line theory. Along the gate width, we have the transmission line equations in frequency domain as follows

2›vðxÞ

›x ¼ R

0

giðxÞ ð17Þ

Fig. 3. Equivalent circuits of shunt – shunt feedback loops are presented. By feedback theorem[20], feedback loops A and B can be transformed into equivalent loadings on the input and output nodes.

2›iðxÞ ›x ¼ ðsC 0 gsþ Y 0 22;loopAþ Y 0 22;loopBÞvðxÞ

þ ðY021;loopAþ Y021;loopBÞvout

¼ ðsC0gsþ sC0gdþ sC0gbÞvðxÞ þ 2sC0gd2 s2RsubCdbC0gb 1 þ sRsubCb ! vout ð18Þ

which are subject to the boundary conditions iðWÞ ¼ 0 and vð0Þ ¼ vgs: Solving these equations for vðxÞ and iðxÞ yields

vðxÞ ¼ vgs2 B A  _coshð ffiffi A p ðW 2 xÞÞ coshðpffiffiAWÞ þ B A ð19Þ iðxÞ ¼ vgs2 B A   ffiffip_A R0g sinhðpffiffiAðW 2 xÞÞ coshðpffiffiAWÞ ð20Þ where A ¼ R0gðsC 0 gsþ Y 0 22;loopAþ Y 0 22;loopBÞ ¼ R0gðsC 0 gsþ sC 0 gdþ sC 0 gbÞ ¼ sR 0 gC 0 g ð21Þ B ¼ 2R0gðY 0 21;loopAþ Y 0 21;loopBÞvout ¼ R0g sC0gdþ s2RsubCdbC0gb 1 þ sRsubCb ! vout ð22Þ

where R0_g is the gate resistance per unit width and C0_g¼ C0gsþ C0gdþ C0gb: With the assumption (3), the average

voltage at the gate region and total current in the channel

can be expressed as:

v ¼ vgs2 B A  _tanhð ffiffi A p W Þ ffiffi A p W þ B A ð23Þ gmv ¼ gmv ¼ gm vgs2 B A  _tanhð ffiffi A p WÞ ffiffi A p W þ B A " # ð24Þ

Then, according to the two-port circuit model, the Y-parameters of the equivalent small signal circuit can be solved as follows Y11¼ ig vgs " # vout¼0 ¼ W½sC0gsþ Y 0 22;loopAþ Y 0 22;loopB tanhðpffiffiAWÞ ffiffi A p W ¼ sCg tanhðpffiffiAWÞ ffiffi A p W ð25Þ

where igis expressed as the current at location x ¼ 0 and Cg

is the sum of Cgb; Cgs and Cgd: The above result clearly

indicates that three coupling paths influence the input admittance Y11: They are the ways from gate to

source, gate to drain and gate to substrate through Cgs; Cgd

and Cgb; respectively. Then, the parameter Y12 can be

expressed as: Y12¼ ig vout vgs¼0 ¼ W Y021;loopA |fflffl{zfflffl} TermM þ Y021;loopB |fflffl{zfflffl} TermN 0 B @ 1 C Atanhð ffiffi A p WÞ ffiffi A p W ¼ 2 sCgdþ s2RsubCdbCgb 1 þ sRsubCb ! tanhðpffiffiAWÞ ffiffi A p W ð26Þ

Eq. (26) provides useful insight on the coupling paths of drain voltage to gate current. Two terms (term M and term N) in Eq. (26) describe the paths. Term M: the voltage applied to the drain couples to the distributed gate region through Cgd: Term N: the drain voltage couples to the

distributed substrate region and makes current flow through Cgb into gate region. In addition, the parameter Y21 can be

expressed as Y21 ¼ id vgs " # vout¼0 ¼ ðgmþ WY 0 12;loopA2 sCmÞ |fflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflffl} TermO 2 6 4 þ gmb sRsubCgb 1þsRsubCb |fflfflfflffl{zfflfflfflffl} TermP þ W Y012;loopB |fflffl{zfflffl} TermQ 3 7 5tanhð ffiffi A p WÞ ffiffi A p W ¼ gm2 sCdgþ sgmbRsubCgb2 s2RsubCdbCgb 1 þ sRsubCb ! tanhð ffiffi A p WÞ ffiffi A p W ð27Þ

where Cmis the transcapacitance (i.e. Cm¼ Cdg2 Cgd) and

Cdg is the drain-to-gate capacitance. Similarly, the signal

coupling paths are described by three terms expressed in Eq. (27). Term O: the voltage applied to the gate makes the current flowing in the channel, but due to the existence of Cgd; the current flowing from the drain end must subtract the

current flowing through Cgd from gate region. Term P: the

gate voltage makes current flow through Cgb and voltage

drop across Rsub; vbs; which is multiplied by gmb to make

current flowing into the channel. Term Q: the gate voltage makes the current flow through Cgb and voltage drop on

Rsub; vbs; which makes current flowing through Cdb into the

drain end in the opposite direction of id: Finally, the

parameter Y22 can be expressed as

Y22¼ id vout vgs¼0 ¼ gmþ WðY 0 12;loopAþ Y 0 12;loopBÞ 2 sCm |fflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflffl} TermR 0 B @ 1 C A 1 2tanhð ffiffi A p WÞ ffiffi A p W ! ð21ÞR0

gðY021;loopAþ Y021;loopBÞ

A þ gdsþ Y11_;loopA |fflffl{zfflffl} TermS þ Y11_;loopB |fflffl{zfflffl} TermT þ gmb1þsRsRsub_subCdbC_b |fflfflfflffl{zfflfflfflffl} TermU ¼ gm2 sCdg2 s2RsubCdbCgb 1 þ sRsubCb ! 1 2tanhð ffiffi A p WÞ ffiffi A p W ! sC0_gdþs 2_R subCdbC0gb 1 þ sRsubCb sC0g 0 B B B @ 1 C C C Aþ gdsþ sCgd þsCdb½1 þ gmbRsubþ sRsubðCsbþ CgbÞ 1 þ sRsubCb ð28Þ

where gds is the conductance of drain-to-source. In

Eq. (28), four terms describe the signal coupling paths.

Term R: the voltage applied to the drain makes current flow into the distributed gate region through loops A and B, and voltage drop on the gate region, vgs;

which makes current flow out of the drain end through feedback loops A and B. Term S: the drain voltage makes current flow through loop A. Term T: the drain voltage makes current flow through Cdb and voltage drop

across Rsub; Csband Cgb; vbs; which makes current flow out

of the drain end. Term U: the voltage drop vbs due to the

coupling effect as described in Term T is multiplied by gmb to make current flow into the channel. From the

expressions of Y-parameters derived, how signal-coupling occurring through capacitive and resistive elements contained in Fig. 2 has been clearly explained.

3. Parameter-extraction method

In this section, a direct extraction method for RF equivalent circuit parameters of MOS transistors is presented. The method is based on the linear regression approach and the Y-parameters obtained from S-parameters analysis. All components in the equivalent circuit are extracted by the Y-parameters analysis and the relative analytical equations are derived from the real and imaginary parts of Y-parameter expressions mentioned in Section 2. The details of the equivalent circuit parameters extraction are described as follows.

Due to the fact that gmand gds are DC parameters, they

can be obtained from the y-intercept of Re½Y21 versus w2

and y-intercept of Re½Y22 versus w2 at low frequency,

respectively, and shown as:

gm¼ Re½Y21w2_¼0 ð29Þ

gds¼ Re½Y22w2_¼0 ð30Þ

Then, at low frequency, with the assumption that the first term in the parentheses of Eq. (26) dominates, Y12 can be

approximated as follows: Y12¼ 2 sCgdþ s2RsubCdbCgb 1 þ sRsubCb ! tanhðpffiffiAWÞ ffiffi A p W < 2sCgd tanhðpffiffiAWÞ ffiffi A p W ð31Þ

Similarly, with the assumption that the first two terms in the parentheses of Eq. (27) dominate, Y21 can be

approximated as follows: Y21¼ gm2sCdgþ sgmbRsubCgb2s2RsubCdbCgb 1þsRsubCb ! tanhðpffiffiAWÞ ffiffi A p W <ðgm2sCdgÞ tanhðpffiffiAWÞ ffiffi A p W ð32Þ

Then, due to the fact that the real part of term tanhðpffiffiAWÞ=ðpffiffiAWÞ is almost equal to 1 at low frequency,

as shown inFig. 5, Cgd can be obtained as: Cgd¼2Im½Y12= Re tanhðpffiffiAWÞ ffiffi A p W " # w ! ¼Im½Y12=w ð33Þ

In addition, Cgcan be obtained from Y11at low frequency

and shown as follows:

Cg¼Im½Y11= Re tanhðpffiffiAWÞ ffiffi A p W " # w ! ¼Im½Y11=w ð34Þ

With the extracted parameters Cg; we can obtain Rg by

optimization to fit Eq. (25) to the experimental data Y11:

Then, in order to extract the transcapacitance Cm; Cdghas to

be extracted first. At low frequency, from Eq. (32), C_dg can be obtained as: Cdg¼Im½Y21= Re tanhðpffiffiAWÞ ffiffi A p W " # w ! ¼Im½Y21=w ð35Þ

Besides, based on the assumption that the term s2RsubCdbCgb=ð1þsRsubCbÞ is extremely small for frequency

up to 10 GHz, Eq. (28) can be re-expressed as

Y22<ðgm2sCdgÞ 12 tanhðpffiffiAWÞ ffiffi A p W ! C0gd C0_g ! þgds þsCgdþ sCdb½1þgmbRsubþsRsubðCsbþCgbÞ 1þsRsubCb ¼YAþ sCdb½1þgmbRsubþsRsubðCsbþCgbÞ 1þsRsubCb ð36Þ where YA¼ðgm2sCdgÞ 12 tanhðpffiffiAWÞ ffiffi A p W ! C0gd C0g ! þgdsþsCgd

Additionally, at low frequency, with the assumption w2R2subCb2p1; Eq. (36) can be approximated as[22]:

Y22<YAþw2Rsub½CbðCdbþgmbRsubCdbÞ2CdbðCsbþCgbÞ

þjw½ðCdbþgmbRsubCdbÞþw2R2subCbCdbðCsbþCgbÞ <YAþw 2 RsubC 2 dbþjwCdb ð37Þ

In the Eq. (37), in order to obtain initial values of Cdband

R_sub; we assume that g_mbR_{subp1: This assumption may} slightly overestimate the values of Cdb and Rsub; so they

have to be corrected by optimization after substrate-related components (i.e. Cgb; Cb and gmb) extracted. At first, we

determine the initial values of Cdb and Rsub from the

imaginary and real parts of Y22in Eq. (37) at low frequency,

respectively, and shown as follows:

Cdb¼ðIm½Y222Im½YAÞ=w ð38Þ

Rsub¼ðRe½Y222Re½YAÞ=ðw 2

C2dbÞ ð39Þ

For the extraction of substrate-related components, Cgb;

Cb and gmb; Ysub is first defined as follows

Ysub¼Y222YA<jw Cdbð1þgmbRsubÞ 1þw2_R2 subC2b þw2RsubCdbðgmbRsubCbþCdbÞ 1þw2_R2 subCb2 ð40Þ

where w3_{-terms are negligible compared with the w-terms}

for operation frequency up to 10 GHz. The parameter gmb

can be obtained from the intercept of the relationship for w=Im½Ysub versus w2by Eq. (41) as follows:

w Im½Ysub ¼ 1 Cdbð1þgmbRsubÞ þw2 R 2 subCb2 Cdbð1þgmbRsubÞ ð41Þ

Then, Cb is obtained from the slope of the relationship

for w2=Re½Ysub versus w2and shown as:

w2 Re½Ysub ¼ 1 RsubCdbðRsubgmbCbþCdbÞ þw2 R 2 subC2b RsubCdbðRsubgmbCbþCdbÞ ð42Þ

The remaining parameter Cgb is determined by

optimiz-ation to fit Eq. (36) to the experimental data Y22: The

validity of the assumptions mentioned above (i.e. w2_R2

subC2bp1 at low frequency; s2RsubCdbCgb=ð1þsRsubCbÞ

is extremely small for frequency up to 10 GHz) will be checked after all parameters are extracted.

4. Verification with experiments and results discussion In this section, the proposed direct extraction approach was applied to determine the parameters of the test device, which were n-MOSFETs fabricated by 0.18-mm technology. To obtain the Y-parameters of RF MOSFETs, S-para-meters were measured in the common-source configuration using an Agilent 8510C vector network analyzer and an on-wafer RF probe station. Before starting the measuring procedure, the calibration was performed on a ceramic calibration substrate using a SOLT calibration method. Besides, the measured data had to be corrected for parasitic capacitance of input/output pads and the resistances and inductances of

Fig. 5. Real and imaginary parts of tanhpffiffiAW=ðpffiffiAWÞ as a function of frequency.

connection lines using two-step de-embedding technique

[21]. The parameter extraction approach had been performed on the n-MOSFETs with 0.18-mm length and 105-mm width.

Fig. 6shows the extraction results of transconductance gm and channel conductance gds for an n-MOSFET device

W=L ¼ 105=0:18-mm biased at Vgs¼ 1 V and

Vds¼ 1:4 V. The transconductance gm was obtained from

the y-intercept of Re½Y21 versus w2 at low frequency, as

shown in Fig. 6(a). In similarity, the channel conductance gdswas obtained from the y-intercept of Re½Y22 versus w2at

low frequency, as shown inFig. 6(b). InFig. 7(a), gmbcan be

obtained from the y-intercept of linear fit straight line of w=Im½Ysub versus w2: InFig. 7(b), Cbcan be obtained from

the slope of linear fit straight line of w2=Re½Ysub versus w2:

Figs. 8 and 9 show the extracted parameters Cgb; Cb; Csb;

Cdb; Cgd; Cdg; Cgs; Rg and Rsub as a function of frequency.

They show that the extracted resistances and capacitances are frequency-independent and this result verifies that the proposed extraction approach is accurate and reliable. Furthermore, due to the charge-conservation and nonreci-procity, Cdg is larger than Cgd; as shown in Fig. 8. The

extracted values of all parameters are summarized in

Table 1. From the extracted parameters, the value of

w2R2_subC2_b is calculated to be 0.012 at 1 GHz, and the real and imaginary parts of s2RsubCdbCgb=ð1 þ sRsubCbÞ

are calculated to be 8 £ 1025 and 2 8.6 £ 1025 at 10 GHz, respectively, which are much smaller than the ones of gm2 jwCdg and jwCgd: Besides, for the extracted

parameters listed in Table 1, the assumptions used in the approximations of Y12and Y21in the Eqs. (31) and (32) Fig. 6. The extraction results of transconductance gm and channel

conductance gds: (a) gmis obtained from the y-intercept of Re½Y21 versus

w2 at low frequency, (b) gdsis obtained from the y-intercept of Re½Y22

versus w2_{at low frequency.}

Fig. 7. (a) The extraction results of w=Im½Ysub as a function of w2; where

gmcan be determined from the y-intercept. (b) The extraction result of

w2_=Re½Y

sub as a function of w2; where the Cbcan be determined from

the slope.

Fig. 8. Frequency dependence of the extracted capacitances for an n-MOSFET with 105 mm width and 0.18 mm length biased at Vgs¼ 1 V and

Vds¼ 1:4 V. The extracted capacitances remain almost constant with

frequency and thus verify that the extraction method is reliable and accurate.

Fig. 9. Frequency dependence of the extracted resistances for an n-MOSFET with 105 mm width and 0.18 mm length biased at Vgs¼ 1 V and

are valid for frequency up to 10 GHz. These results verify the validity of the assumptions made in the extraction approach.

InFig. 10, the Y-parameters calculated with the extracted parameters are compared with measured data for two bias conditions: (1) Vgs¼ 1 V; Vds¼ 1:4 V; and (2) Vgs¼ 0:6

V; Vds¼ 1:4 V: It is shown that a good agreement was

obtained between the simulation results and measured data. From Eq. (27), it is known that nonreciprocal capacitance Cdg contributes the accuracy in Im½Y21 prediction. In

Fig. 10(c), excluding the nonreciprocal capacitance Cdg

resulting in a significant error in matching Im½Y21 is

observed, especially for larger Vgs: This is because Cdg

increases with Vgs; being discussed latter.

Fig. 11(a) shows the gate bias dependence of the

extracted capacitances for an n-MOSFET biased at Vds¼

1:4 V: As gate bias increases for constant Vds; Cgb

decreases due to the fact that the inversion status is getting stronger as Vgs increases. In other words, the

ability of the inversion layer to protect the gate from the influence of the substrate is increasing as Vgs increases. In

saturation region, Cdb is dominated by junction

capaci-tance and almost constant at fixed Vds: Cgd and Cgs are

composed of intrinsic capacitances Cgdi; Cgsi and overlap

capacitances Cgdo; Cgso: Cgd is dominated by intrinsic

capacitance Cgdi in the saturation region because the

communication from the drain to the rest of the device is cut off owing to the pinch-off region. Furthermore, Cdg

and Cm increase with Vgs due to the increase of intrinsic

capacitance.Fig. 11(b) shows the gate bias dependence of the extracted resistances for an n-MOSFET biased at Vds¼ 1:4 V: From the figure, it is shown that Rg and Rsub

remain almost constant as Vgs increases.

The drain bias dependence of the extracted capacitances for an n-MOSFET biased at Vgs¼ 1 V: is shown in

Fig. 12(a). As Vds increases, Cgb increases because the

influence of the substrate bias on the gate charge is increasing. Due to the increasing reverse bias between drain and substrate, Cdb decreases as Vds increases.

In the saturation, Cgsand Cgd are dominated by the overlap

capacitances Cgdo; Cgso and remain constant. Fig. 12(b)

shows the drain bias dependence of the extracted resistances for an n-MOSFET biased at Vgs¼ 1 V: The extracted

resistances Rgand Rsubare almost constant as Vdsincreases.

The bias dependence of transconductance gm obtained Fig. 10. Real and imaginary parts of Y-parameters: (a) Y11; (b) Y12; (c) Y21;

and (d) Y22as a function of frequency for a device with 105 mm width and

0.18 mm length biased at Vgs¼ 1 V and Vds¼ 1:4 V. The simulation

results obtained by proposed model have a good agreement to the experimental data.

Table 1

Table of the extracted small signal parameters for an n-MOSFET with 105 mm width and 0.18 mm length biased at Vds¼ 1:4 V and different Vgs

Vgs(V) 0.6 1 Cgs(fF) 102 118.9 Cgd(fF) 58.5 60.45 Rg(V) 6.5 6.4 gm(mS) 26.626 51.238 Cdg(fF) 85 140.3 Rsub(V) 59 60.7 Cgb(fF) 8.3 8 gmb(mS) 3.543 3.92 Cdb(fF) 80.1 90 Csb(fF) 185 188 gds(mS) 1.3433 3.608

from Y-parameters measurement and conventional DC measurement for an N-MOSFET is shown in Fig. 13. It can be seen that there is a good agreement between these two measurements. The results demonstrate that the DC- and AC-related parameters can be extracted by the proposed method in the HF analysis simultaneously. This extraction method avoids the possible error occurring in

the conventional DC extraction method for transconduc-tance gm: This is because that conventional DC extraction

method extracts gmby differentiation of the I – V curves and

this may cause a significant error.

5. Conclusions

In this paper, a new and accurate small signal model including distributed gate network, substrate network and nonreciprocal capacitance has been developed. Mean-while, a direct extraction method for the parameters of the new model is also proposed. This model uses transmission line theorem to describe the distributed gate region, a single substrate resistance and relative capacitances to model the distributed substrate network and accounts for the nonreciprocal capacitance. In addition, an examination has done by using the measured data to verify the model and parameter extraction method. The extracted par-ameters are physical meaning and good agreements have been obtained between the simulation results and measured data. Furthermore, the extraction method was used to extract the transconductance gm by Y-parameters

analysis and verified by DC measurement data. The results demonstrated that the proposed extraction method is accurate and reliable.

Fig. 11. Gate bias dependence of small-signal parameters for an n-MOSFET with 105 mm width and 0.18 mm length biased at Vds¼ 1:4 V:

(a) capacitances and (b) resistances.

Fig. 12. Drain bias dependence of small-signal parameters for an n-MOSFET with 105 mm width and 0.18 mm length biased at Vgs¼ 1 V: (a)

capacitances and (b) resistances.

Fig. 13. The bias dependence of transconductance gmobtained from

S-parameters measurement by the proposed extraction method and from the conventional DC measurement for an n-MOSFET with 105 mm width and 0.18 mm length: (a) gate bias dependence and (b) drain bias dependence.

Acknowledgements

The helpful suggestion and discussion from Dr J.H. Wang are gratefully acknowledged. The great support from S.Y. Huang on S-parameter measurement is also appreciated.

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