Improved memory window for Ge nanocrystals embedded in SiON layer

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Improved memory window for Ge nanocrystals embedded in SiON layer

Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Hsin-Chou Liu, Simon M. Sze, and Chun-Yen Chang

Citation: Applied Physics Letters 89, 162105 (2006); doi: 10.1063/1.2362972 View online: http://dx.doi.org/10.1063/1.2362972

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Improved memory window for Ge nanocrystals embedded in SiON layer

Chun-Hao Tu

Institute of Electronics, National Chiao Tung University, Hsin-Chu 300, Taiwan, Republic of China

Ting-Chang Changa兲

Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan, Republic of China; Institute of Electro-Optical Engineering, National Sun Yat-Sen University, Kaohsiung 80424,

Taiwan, Republic of China; and Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan, Republic of China

Po-Tsun Liu

Department of Photonics, National Chiao Tung University, Hsin-Chu 300, Taiwan, Republic of China and Display Institute, National Chiao Tung University, Hsin-Chu 300, Taiwan, Republic of China

Hsin-Chou Liu, Simon M. Sze, and Chun-Yen Chang

Institute of Electronics, National Chiao Tung University, Hsin-Chu 300, Taiwan, Republic of China

共Received 1 August 2006; accepted 29 August 2006; published online 18 October 2006兲

The formation of germanium 共Ge兲 nanocrystals embedded in silicon oxygen nitride 共SiON兲 is proposed for charge storage elements in this work. The Ge nanocrystals can be nucleated after the oxidation process of silicon germanium nitride共SiGeN兲 layer at high temperatures. Compared to the control samples of Ge nanocrystals/SiO2/ Si structure and SiON / Si stack memory, the proposed Ge nanocrystals/SiON / Si memory obtained superior memory window, even larger than the typical sum of both. It is considered that the extra interface trap states between Ge and SiON film were generated as Ge nanocrystals were embedded in SiON layer. © 2006 American Institute of Physics.

关DOI:10.1063/1.2362972兴

In the past few years, the portable electronic devices have significantly impacted the market of consumer electron-ics. Because of the low working voltage and nonvolatility, the selection of storage media for most portable electronic devices is the flash memory which almost bases on the struc-ture of the continuous floating gate 共FG兲.1,2 To date, the stacked-gate FG device structure continues to be the most prevailing nonvolatile memory implementation and is widely used in both independent and embedded memories. The in-vention of FG memory impacts more than the replacement of magnetic-core memory and creates a moment of portable electronic systems. Despite a huge achievement in commer-cialization, conventional FG devices have some drawbacks.2 Hence, the disserted stored center concept for charge trap-ping layer was proposed, such as poly-Si/oxide/nitride/ oxide/Si共SONOS兲 and nanocrystals. In such proposed non-volatile memory devices, charges are not stored in a continuous FG poly-Si layer but instead in a discrete, mutu-ally isolated layer. Also, the proposed nonvolatile device can avoid the charge leakage and lower the power consumption when tunneling oxide is thinner.3–5 The self-assembling of silicon or germanium nanocrystals embedded in SiO2layers has been widely studied, and strong memory effects in metal-oxide-semiconductor devices were reported.3,6,7 Recently, different charge storage elements have been studied to achieve the robust distributed charge storage.8–13 Whereas research on nanocrystal memory has mainly focused on Si and Ge nanocrystals, it is also of interest for its smaller band gap, inducing a theoretically better and faster writing/erasing times and reliability.14,15In this contribution, the SiGeN was investigated to be a self-assembling layer.16 The self-assembling layer of SiGeN, fabricated by the directly

depos-iting using plasma enhanced chemical vapor deposition 共PECVD兲 system. The following amorphous silicon 共a-Si兲 was also deposited in one chamber system by using PECVD. The structure with Ge embedded SiON layer exhibits obvi-ous charge trapping memory effects under electrical measurements.

First, a 5-nm-thick thermal oxide was grown as the tun-nel oxide on p-type Si substrate by dry oxidation in an at-mospheric pressure chemical vapor deposition furnace. Sub-sequently, 20 nm silicon nitride, silicon germanium, and silicon germanium nitride thin film were prepared on tunnel oxide, respectively. The sequential a-Si layer was also de-posited. The oxidation process was performed to fabricate the oxygen-incorporated SiO2 to serve as blocking oxide, and the oxidation temperature was 900 ° C. Furthermore, the SiGe-based thin film layer is also oxidized to nucleate the Ge nanocrystals during the blocking oxide formation. Afterward, a steam densification at 900 ° C was also performed for 180 s to densify the blocking oxide. The deposition of the charge trapping film was kept at 200 ° C in a low pressure of 0.6 mTorr. The low pressure of 0.6 mTorr during deposition leads the mean free path of electrons to be increased and to improve the uniformity of the thin film. Next, the high-temperature thermal oxidation was performed in the thermal furnace in oxygen ambient. The sequent steam oxidation was performed to improve the quality of oxidized a-Si layer as the blocking oxide. Finally, the Al gate was patterned and sintered to form a metal-oxide-insulator-oxide-silicon 共MOIOS兲 structure

The MOIOS memory device is utilized to capture the injected carriers from the channel, which causes a variation in the threshold voltage of the memory device. The blocking oxide is utilized to prevent the carriers of gate electrode from injecting into the charge trapping layer by Fowler-Nordheim

a兲_{Electronic mail: [email protected]}

APPLIED PHYSICS LETTERS 89, 162105共2006兲

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tunneling. Figure 1 shows the capacitance-voltage 共C-V兲 hysteresis of the MOIOS structure for SiON as charge trap-ping layer. The electrical C-V measurements were performed by bidirectional voltage sweeping. The sweeping conditions were split as follows:共I兲 operated from 7 to −7 V and vice versa and共II兲 operated from 5 to −5 V and vice versa. It is clearly shown in Fig. 1 that the threshold-voltage shift 共memory window ⌬Vth兲 of the MOIOS structure is promi-nent for 900 ° C oxidation. When the device is programed, the electrons directly tunnel from the Si substrate through the tunnel oxide and are trapped in the forbidden gap of silicon nitride layer. For the erasing process, the holes may tunnel from the valence band of the Si substrate and recombine with the electrons trapped in the SiON layer. The memory win-dow of 0.2 V is observed under an operation of 5 V. How-ever, the C-V hysteresis of the MOIOS structure for Ge nanocrystal is shown as Fig.2. The electrons共holes兲 directly tunnel from the Si substrate through the tunnel oxide and are trapped共detrapped兲 in the forbidden gap of Ge nanocrystal. The larger memory window for Ge nanocrystal embedded in

SiO2layer is obtained than the previous one. This is contrib-uted from the trap state for nanocrystals surrounding the di-electric. Under an operation of 5 V, a memory window of 0.4 V is exhibited after a cycle of programming and erasing process.

The proposed MOIOS structure via a way of oxidizing SiGeN layer as charge trapping layer is also measured under the same operation conditions. The C-V electrical character-istic is shown in Fig.3. The threshold-voltage shift after the 5 V programming operation is 1 V for the Ge nanocrystals embedded in SiON memory device with a-Si layer oxidized at 900 ° C. The large threshold-voltage shift of memory de-vice with an oxidized a-Si film as blocking oxide layer is attributed to the presence of Ge nanocrystals in the SiON film. The memory windows under 5 V operation for the three types of MOIOS structure are listed in Table I. It is clear that the memory window of Ge nanocrystals embedded in SiON memory structure is the largest than both above. Even the memory window value is larger than the sum of those of SiON and Ge nanocrystal MOIOS structures. The Ge nanocrystal embedded in SiON layer exhibits the supe-rior memory characteristics. It is considered that the extra interface trap states between Ge and SiON film were gener-ated as Ge nanocrystals were embedded in SiON layer. The initial SiON trap state density plus the trap state density of Ge nanocrystal surrounding the dielectric cause more larger memory effect. The proposed diagram is inserted in the Fig. 3. The proposed Ge nanocrystals embedded in SiON stack layer with high-temperature oxidized a-Si layer, therefore, contribute both larger memory window and the additional blocking oxide deposition for the nonvolatile memory appli-cation promisingly.

FIG. 1. Capacitance-voltage共C-V兲 hysteresis of the MOIOS structure for SiON as charge trap center. The electrical C-V measurements are performed by bidirectional voltage sweeping共1兲 from 7 to −7 V and from −7 to 7 V and共2兲 from 5 to −5 V and from −5 to 5 V. The insert is the diagram for charge trapping center for SiON layer.

FIG. 2. Capacitance-voltage共C-V兲 hysteresis of the MOIOS structure for Ge nanocrystal embedded in SiO2layer as charge trap center. The electrical C-V measurements are performed by bidirectional voltage sweeping from

5 to − 5 V and from −5 to 5 V. The insert is the diagram for charge trap-ping center for Ge nanocrystal embedded in SiO2layer.

FIG. 3. Capacitance-voltage共C-V兲 hysteresis of the MOIOS structure for Ge nanocrystal embedded in SiON layer as charge trap center. The electrical

C-V measurements are performed by bidirectional voltage sweeping from

5 to − 5 V and from −5 to 5 V. The insert is the diagram for charge trap-ping center for Ge nanocrystal embedded in SiON layer.

TABLE I. Memory windows for three types of nonvolatile memory devices. Nonvolatile memory ⌬V_thunder 5 V operation

SiON 0.2

Ge nanocrystal embedded in SiO2 0.4

Ge nanocrystal embedded in SiON 1

162105-2 Tu et al. Appl. Phys. Lett. 89, 162105共2006兲

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In conclusion, an easy nanocrystal memory technology has been demonstrated by oxidizing SiGeN film to form Ge distributed storage elements embedded in SiON layer. The memory window is obviously larger than the MOIOS struc-tures with SiON layer alone or with Ge nanocrystals embed-ded in SiO2layer and even larger than the sum of both. The exhibition of memory windows after programming is re-sulted from the formation of Ge nanocrystals embedded in SiON layer and extra interface trap states between Ge and SiON film. Therefore, the material of SiGeN served as self-assembling layer and has more potential for the application in the nanocrystal nonvolatile memory technology.

This work was performed at National Nano Device Laboratory and was supported by the National Science Council of Republic of China under Contract Nos. NSC 95-2221-E-009-283, NSC 95-2221-E-009-270, NSC 95-2120-M-110-003, and NSC 95-2221-E-009-254-MY2. Also, the authors would like to acknowledge the support of the plasma enhanced chemical vapor deposition共PECVD兲 system in Na-tional Chiao Tung University共NCTU兲 in Hsin-Chu. Further-more, this work was partially supported by MOEA Technol-ogy Development for Academia Project No. 94-EC-17-A-07-S1-046.

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