Novel duty phase control for single-phase boost-type SMR

Novel Duty Phase Control

for Single-Phase Boost-Type SMR

Hung-Chi, Chen (IEEE Member)

Department of Electrical and Control Engineering, National Chiao-Tung University, Hsin-Chu, Taiwan.

[email protected]

Abstract- In this paper, a novel duty phase control (DPC) for single-phase boost-type switching-mode-rectifier (SMR) is developed and implemented in DSP-based system. Compared to the conventional multi-loop control structure with inner current loop and outer voltage loop, noted that there is only one voltage loop tuning the phase of pre-defined duty pattern (i.e. duty phase) in the proposed DPC. Due to no current loop, inductor current sampling and tracking control are unnecessary when SMRs are operated to obtain sinusoidal current waveform and regulate the output voltage. It implies that the single-loop DPC is simple, current sensorless and loopless, and is very adaptable to the implementation with digital and analog integrated circuits. In this paper, first, the effect of the duty phase on the input current is analyzed and modeled. It shows that the sinusoidal current waveform can be naturally generated by the pre-defined duty pattern and the current amplitude is roughly proportional to the controllable duty phase. Then, a voltage controller is designed to regulate the dc output voltage by tuning this duty phase. Finally, some simulated and experimental results have been given to illustrate the performances of the proposed DPC.

I. INTRODUCTION

The AC/DC converter is an essential component for most power electronic systems to build up DC-link voltage source from the AC mains. The use of switching-mode-rectifier (SMR) [1-3] with power factor correction (PFC) function is an effective mean to perform the AC/DC conversion with high quality by shaping the input current waveform and regulating the output voltage. The boost-type SMRs are the most popular circuit topology among all the others to shape the current waveform for their continuous current in the front-end inductors [1].

In order to let the boost-type SMRs have good input and output performances, many types of voltage and current control approaches have been developed, such as feedforward current control [3-5], robust voltage and current control [3,6] and predictive current control [7-8]. The multi-loop control is the most popular structure to coordinate the individual voltage and current control to meet the input and output specifications by controlling the single power switch.

However, there are two drawbacks in the common multi-loop control for boost-type SMRs. One is that the output voltage ripple through the outer voltage loop will result in the distorted current command into the inner current loop. The other is the difficulty of deciding the current sampling instants due to the large variations in the switching duty of the

boost-type SMRs. However, it is cleared that the above two problems are relating to the inner current loop and, thus, if there is no current loop in the control structure, both the problems and the cost of current sensing can be removed in the operations of boost-type SMRs. It implies that only one voltage loop is included in the final control structure, and thus, such single-loop control structure is very competitive for its simplicity.

The proposed duty phase control (DPC) can be seen as the single-loop structure with only one voltage loop tuning the phase of the pre-defined duty pattern (i.e. duty phase). Compared to the simple single-loop voltage mode control under discontinuous current mode (DCM), the proposed single-loop DPC is working in continuous current mode (CCM). Therefore, the developed DPC is novel, easy, current sensorless and loopless.

The paper is organized as follows. Initially, the phase effect of the pre-defined duty pattern on input current is analyzed and modeled. The results show that the sinusoidal current waveform can be automatically generated by the pre-defined duty pattern and the input current amplitude is roughly proportional to the duty phase. Subsequently, based on the effect of duty phase on the input current amplitude, a voltage controller can be included to regulate the dc output voltage by means of tuning the duty phase. Finally, some simulated and experimental results have been given to illustrate the performance of the proposed DPC. The measurements also show that the drawn harmonic currents are well below the limits of the standard IEC 61000-2-3.

II. BOOST-TYPE SMRS A. Modeling

As shown in Fig. 1, the power circuit of the boost-type SMR mainly consists of a diode bridge rectifier and a boost-type DC/DC converter. In order to model the behaviors of the boost-type SMR, some assumptions are initially made:

(i) Circuit elements are ideal and thus, lossless;

(ii) Power switch SW operates at a switching frequency approaching infinity.

(iii) A bulk capacitor Cdis included in the power circuit and

the output voltage vd can be assumed to be the average

valueVd.

Therefore, the above three assumptions allows the following equation on an instantaneous basis.

) ( ) ( ) ( ) ( ) (t P t v ti t V i t P_{s d d d} | _dd (1)

where P_s(t) and P_d(t)are the instantaneous input power and output power, respectively. Furthermore, when the boost-type SMR is operating in CCM with unity power factor, the drawn input power P_s(t) can be expressed as the product of input current i_s(t) Iˆ_ssin(Zt) and input voltage v_s(t) Vˆ_ssin(Zt).

Fig. 1. Power circuit of the boost-type SMR.

Therefore, from the above two equations, we can obtain output current ) ( ) 2 cos( 2 ˆ ˆ 2 ˆ ˆ ) ( ) ( t I i t V I V V I V V t P t i load c d s s d s s d s d  Z '  (3)

where the average value of i_d is

d s s load d V I V I I 2 ˆ ˆ (4) and the current through the capacitor is

) 2 cos( ) 2 cos( 2 ˆ ˆ ) ( t I t V I V t i d d s s c  Z  Z (5)

Then, the ripple v_d,ac in v_d can be estimated from (5) as ) 2 sin( 4 ˆ ˆ ) ( 1 ) ( , _{C V} t I V t i C t v d d s s c d ac d Z Z  ³ | (6) B. Multi-Loop Control

The above derivations (1)~(6) are mainly from considering the relations between input and output waveforms and neglecting the detailed switching behavior of the boost-type SMRs. Therefore, as shown in Fig. 2, the popular multi-loop control for boost-type SMRs are not based on (1) through (6) but based on the following straightforward principles of waveform tracking and power balance.

From the balance between input and output power, the adequate input current amplitude can be certainly obtained to maintain the desired output voltage. Therefore, in the multi-loop control shown in Fig. 2, the input current amplitude ˆI* can be yielded to regulate the output voltage through the outer voltage controller. By multiplying ˆI* with the unity rectified signal s(Zt) sinZt , the inductor current command i_L* of desired load condition can be obtained. In order to shape the

current waveform, the switching signal d(t) in Fig. 2 is generated by comparing the output signal v_cont of the current controller in (+) input and an unity triangular signal v_tri possessing frequency f_tri in (-) input.

However, we can find two drawbacks in the above multi-loop control. The first one is that some significant ripple voltage on the DC bus voltage v_d(t) will result in the existence of double line-frequency component in the current command magnitude ˆI* by the voltage controller. Then, it follows that the line current waveform is regulated to follow a distorted current command waveform. The second drawback is the difficult decision to determine the current sampling instants due to the large variation of the switching instants in the boost-type SMRs. However, the above two problems are relating to current control loop and both can be removed by developing current loopless controller.

Voltage controller 6 d v * d V _ˆI* 6 * L i L i Currentcontroller cont v d(t) v H _{G (s)} Hi cv Gci(s) tri v ) ( t sZ ABS s Vˆ s v s v Peak s s V v /ˆ 0 1 Fig. 2. Conventional multi-loop control for boost-type SMRs.

III. PROPOSEDDUTY PHASE CONTROL

The configuration of the proposed DPC is plotted in Fig. 3 where only one voltage controller is used. The DPC technique can be regarded as a single-loop control. Like the conventional configuration in Fig. 2, the duty signal d(t) is also generated by comparing the carrier signal vtri and the control signal

cont

v . Noted that the carrier signal vtri is at (+) terminal in Fig.

3, but at (-) terminal in Fig. 2. Besides, the control signal

cont

v is not the current controller output as in Fig. 2 but is the pre-defined duty which is the product of the gain V /ˆs Vd and

the shifting rectified signal s(ZtT) from the signal s( tZ in ) Fig. 3. The control signal vcont and the average duty signal

) (t

d can be expressed in the following two equations: ) sin( ˆ ) ( ZtT V V t v d s cont (7) ) sin( ˆ 1 ) (  ZtT V V t d d s ₍₈₎

where the maximum duty is 100% and the minimum average duty is dependent on the input voltage amplitude Vˆs and the

average output voltage Vd. From (8), we can find that the duty

pattern is in fact pre-defined.

To simply the following analysis, the main circuit topology in Fig. 1 and the proposed DPC in Fig. 3 can be combined and redrawn in Fig. 4 where the diode rectifier is removed. Thus, the input voltage of the boost-type DC/DC converter is

represented as an ideal rectified sinusoidal voltage Vˆ_ssin(Z .t) In the following derivations, we will show that the inductor current will become rectified sinusoidal waveform by the pre-defined patterns. Therefore, the SMR’s current shaping function is achieved. Voltage controller 6 d v * d V _{T s(ZtT)} d(t) v H ) (s G_cv Phase shifter ps G s s V v t s(Z) /ˆ ABS s v 0 vtri cont v d s V Vˆ Peak s v s Vˆ 1 Average

Fig. 3. Proposed DPC for boost-type SMRs.

L SW d C L i d v ) sin( ˆ _t V_s Z d i c i ) (t d ) sin( ˆ 1 ZtT V V d s T

Fig. 4. Boost-type PFC SMR with DPC.

From Fig. 4, the KVL and KCL equations can be written as the following equations according to the conduction states pf power switch SW. ) sin( ˆ ) ( _{V t} dt t di L L _{s Z when SW is turning on (9)} d s L _{V t V} dt t di

L () ˆ sin(Z) when SW is turning off (10) Based on the time-averaging approach, the above two equations can be combined to become the following equation (11) through multiplying them by turning-on time d )(tT_s and turning-off time ( 1 d ))(t T_s, respectively.

d s L _{V t d t V} dt t i d L ( ) ˆ sin(Z)(1 ()) (11)

Therefore, by substituting the duty signal d(t) into the above equation and arranging the terms, we can obtain the following time-differential equations for inductor current.

L t V L t V dt t i d L() ˆssin(Z ) _ ˆssin(Z T) ₍₁₂₎

The right term sin(Z t T) can be extracted by applying the commonly used function sin(A B) sinAcosBsinBcosA. If the duty phase signal T in radians is small and near to zero

(T|0), we can substitute sinT |T and cos |T 1and the above equation can be rewritten as:

L t t V L t V dt t i

d L()_| ˆssin(Z ) _ ˆssin(Z)Tcos(Z) ₍₁₃₎

Since the inductor current is periodic with double line frequency, the current differential equation during the first cycle (0d tZ S) can be approximately obtained by removing the absolute operators in (13) and canceling the same terms

) sin( tZ . L t V dt t i d _L() ˆ_sTcos(Z) | , 0d tZ S (14)

Then, by integrating (14), we can obtain the first-cycle current as ) sin( ˆ ) ( t L V t i s L Z Z T | , 0d tZ S (15)

where the current magnitude is dependent on the duty phase T . Because of the periodic current in inductor, we can write the complete inductor current i_L(t) in terms of the first-cycle current in (15). ) sin( ˆ ) sin( ˆ ) ( t I t L V t i s _s L Z Z Z T | (16)

Noted that the inductor current waveform becomes the rectified sinusoidal waveform and the current amplitude Iˆ_s is nearly proportional to the duty phase T . From the original circuit topology including diode bridge rectifier as shown in Fig. 1, the relation between the input current i_s(t) and inductor current i_L(t) can be express as

0 sin ˆ 0 sin ˆ ) ( ) ( ) (  t ° ¯ ° ® ­  whenv V t t V v when t i t i t i s s s s L L s Z Z (17) However, equation (17) can be simplified to the sinusoidal waveform Iˆ_ssinZt in phase with the input voltage Vˆ_ssinZt. It implies that by using the proposed pre-defined duty pattern, the aligning sinusoidal current waveform can be obtained without current feedback.

Besides, because the input current amplitude Iˆ_s can be controlled by its dependency on the duty phase T , we are able to regulate the input and output power with unity power factor by tuning the duty phase T . That is, we can include a voltage controller in DPC to obtain suitable duty phase T to meet the requirement of current waveform shaping and output voltage regulation.

In addition, the output voltage ripple in (6) can be rewritten by replacing the term Iˆ_s with (16):

) 2 sin( 4 ˆ ) ( ₂ 2 , t V LC V t v d d s ac d Z Z T  | (18)

IV. SIMULATED RESULTS

In this section, we begin with a series of computer simulations to demonstrate the proposed DPC. Some nominal values and circuit elements are listed in Table I. It should be noted that no design optimization has been done in order to select the values in Table I. The simple plus-integral (PI) controller is used in the voltage loop of the developed DPC to adjust the duty phase.

Table I

Simulated circuit parameters Input line voltage (peak) V ˆ_s 170V(120V_rms)

Input line frequency f 50Hz

Smoothing capacitance C_d 560PF

Smoothing inductance L 4.65mH

Equivalent load resistance Rload 200:(||1600:) : :or177.78 200

Carrier frequency ftri 25kHz

The simulated waveforms for the condition * d

V =300V and

: 200

load

R are plotted in Fig. 5 where the average duty signal d(t) and the reference signal (i.e. zero duty phase T 0) are the solid line and the dashed line, respectively, in the upper plots. From the simulated data, the duty phase is about

S 014 .

0 rads to obtain the desired output voltage v_d shown in the bottom plot. It implies tuning the duty phase is able to regulate the output voltage.

Fig. 5. Simulated waveforms for ideal circuit elements. Top: average duty signal. Middle: input current and voltage.

Bottom: output voltage.

From the middle plot, we can find that input current is sinusoidal waveform in phase with the input voltage and therefore, not only the output voltage regulation but the input current shaping can be achieved by the single loop tuning the single duty phase. Furthermore, from the key derived equation

in (16) and the parameters in Table I, we can calculate and find that the input current peak is about 5.12A. From observing the input current amplitude 5.1A in the middle plot, the key equation in (16) has been demonstrated.

However, the above simulated waveforms in Fig. 5 are based on the strong assumption of ideal circuit elements. In the following simulations, all the equivalent resistors of inductor and bulk capacitor and the voltage drops of diodes and switch are included in the simulation program to evaluate the nonideal effect on the performance of the proposed DPC.

The simulated waveforms for the same condition * d

V =300V

and R_load 200: are plotted in Fig. 6. The average duty signal )

(t

d (solid line) and duty reference signal (dashed line) are plotted together in the upper plots for the sake of comparison. From the simulated data, the duty phase T now is increasing to about 0.024ʌ rads to obtain the desired output voltage found in the bottom plot. Thus, the actual circuit elements have no effect on the output voltage regulation in the proposed DPC.

Fig. 6. Simulated waveforms for ideal circuit elements. Top: average duty signal. Middle: input current and voltage.

Bottom: output voltage.

However, from the middle plot in Fig. 6, we can find that the ideal sinusoidal current waveform in Fig. 5 has been distorted and replaced with the incomplete sinusoidal waveform where the near-zero portion has been cut. Since the current waveform is far from the sinusoidal one, it is reasonable that the duty phase T increases from 0.014S rads to 0.024S rads in order to provide larger current magnitude and thus, to obtain the desired output voltage. Fortunately, from the following experimental results, the harmonic currents of such distorted current waveform are still lower than the limits of standard IEC 61000-3-2. It implies the developed DPC technique complies with IEC 61000-3-2.

Then, we increase the load condition R_load 177: with the same voltage command *

d

V =300V and illustrate the experimental waveform in Fig. 7. In order to yield suitable

current amplitude to meet the new load condition, the duty phase is automatically tuned to about T|0.028ʌ rads through the voltage loop.

From (8), all the duty patterns in Fig. 5 through Fig.7 are the same because of the same input and output voltage level. The only differences between them are their phase which is the main originality of the proposed DPC. In addition, although the current waveforms are not sinusoidal ones, the proposed DPC still possess useful input and output performances.

Fig. 7. Simulated waveforms for ideal circuit elements. Top: average duty signal. Middle: input current and voltage.

Bottom: output voltage.

IV. REALIZATION

The proposed DPC has been digitally implemented in a DSP-based system using TMS320F240 where a simple and popular PI-type voltage loop is used in order to focus on the performance of tuning duty phase. Only input voltage and output voltages are sensed where the former provides the phase information of input voltage and the latter helps to regulate the output voltage. It is noted that the digital resolution of duty phase is the main challenge in the implementation of the proposed DPC. Too smaller resolution will result in the instable operation of SMRs in shaping current waveform. In my experiment, the phase resolution is set to 12500 per ʌ rads. All the circuit parameters in the experimental system had been listed in Table. I.

V. EXPERIMENTAL RESLTS

Fig. 8 shows the measured waveforms for the condition V

V* 300 and P_s |520W . The top plot shows the output voltage waveform varying around the desired voltage level. The duty phase signal in the middle plot is almost fixed to 0.028ʌ rads in order to stably yield the input current as shown in the bottom plot. From the bottom plots of input current and

voltage, we can find that the actual current waveform is very close to the simulated one in Fig. 7 and the measured power factor now is 0.944. Obviously, input power quality has been improved and the proposed DPC has been demonstrated.

d v T s v s i

Fig. 8. Measured waveforms at Ps 520W. Top: output voltage.

Middle: duty phase. Bottom: input current and voltage.

In Fig. 9, the average duty phase signal d(t) is shown and the reference signal is also plotted for comparison. We can find that the little phase difference between the top plots contributes to draw the distorted current waveform similar to the waveform shown in Fig. 7.

Fig. 10 shows the measured waveforms at V* 300V _and input power P_s 456W . In order to draw smaller current amplitude for smaller input power, the duty phase signal in the middle plot is automatically adjusted from about 0.028ʌ rads to 0.024ʌ rads by the voltage loop. It also implies that the proposed DPC is able to vary the output voltage simply by varying the phase of the per-defined duty pattern.

s v s i ) (t d rads S T|0.028

Fig. 9. Measured waveforms at Ps 520W. Top: average duty

In addition, by using digital power meter YOGOGAWA WT210, the measured power factor, the total current harmonic distortion and the harmonic currents are listed in Table II where the limits IEC-61000-3-2 are also tabulated for the sake of comparison. The total harmonic distortion is about 23.22% and 24.57% in both cases. Fig. 11 plots the harmonic spectra of input current for the measurement in Fig. 8 and Fig. 10. From Fig. 11 and Table II, we can find that the developed control technique generates input current harmonics well below the limits of IEC-61000-3-2 and the current control loop for current tracking has been eluded. This illustrates the advantages of the developed control technique – the proposed DPC is very simple as it avoids inner current loop, and the technique is robust as it has an inherent ability to shape current waveform. d v T s v s i 300V 50V 0.026Ӹ 0.030Ӹ 0 5A 100V 4ms Fig. 10. Measured waveforms at Ps 456W. Top: output voltage.

Middle: duty phase. Bottom: input current and voltage. Table II Harmonic currents IEC-61000-2-3 W Ps 520 PF=0.944 THD=24.57% W Ps 456 PF=0.953 THD=23.2% n=3 2.30A_rms 0.9918A_rms 0.8371A_rms n=5 1.14A_rms 0.1642A_rms 0.1624A_rms n=7 0.77Arms 0.1043Arms 0.0982Arms n=9 0.40A_rms 0.0364A_rms 0.0309A_rms n=11 0.33Arms 0.1118Arms 0.1026Arms n=13 0.21A_rms 0.0930A_rms 0.0850A_rms n=15 0.15Arms 0.0140Arms 0.0194Arms n=17 0.13A_rms 0.0175A_rms 0.0166A_rms n=19 0.12A_rms 0.0094A_rms 0.0136A_rms V. CONCLUSIONS

A new DPC has been developed to the boost-type SMRs, which just adjusts the phase of pre-defined duty pattern. The control technique is single-loop and no current control loop is included. It means that the system cost could be notably decreased for the needless current sampling and/or ADC.

Therefore, the DPC is very simple for analog and digital implementations.

The new DPC technique described and considered in this paper is a generation of popular multi-loop control technique, which can be used directly in many other applications. Simulation and experimental results verify the functionality of the developed DPC technique, where the input harmonic currents compile with IEC 61000-3-2. The developed control can be advanced by considering the nonideal effect on the current waveform in order to provide an even higher power-factor and total current harmonic distortion.

2A 0A 1A Harmonic number n 5 n I 2 3 61000 IEC   10 15 20 25 30 35 W Ps|520 W Ps|456 Harmonic number n 5 10 15 20 25 30 35 2A 0A 1A n I 2 3 61000 IEC  

Fig. 11. Harmonic spectra of the input current and the IEC-61000-3-2 limits. Top: the harmonic current for the measurement in Fig. 8. Bottom: the harmonic current for the measurement in Fig. 10.

ACKNOWLEDGMENT

The author wish to thank the support from the National Science Council under Grant NSC 95-2218-E-009-205.

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