A Dual-Gate-Controlled Single-Electron Transistor
Using Self-Aligned Polysilicon Sidewall Spacer
Gates on Silicon-on-Insulator Nanowire
Shu-Fen Hu, Yung-Chun Wu, Chin-Lung Sung, Chun-Yen Chang, Member, IEEE, and Tiao-Yuan Huang, Fellow, IEEE
Abstract—A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a com-bination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typ-ical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.
Index Terms—Nanotechnology, quantum dots (QD), quantum wires, silicon-on–insulator (SOI) technology.
I. INTRODUCTION
S
ILICON single-electron devices are one of the potential key elements in achieving extremely low-power con-sumption and high-density integration for future large-scale integrated circuits (LSIs). Most silicon-based single-electron transistors (SETs) employ a naturally grown, lithographi-cally defined single quantum dot (QD) with nanosize as the transport bridge between the source and the drain. These conventional single-QD-based SETs, however, depict poor stability in the Coulomb blockade effect due to the inevitable quantum-mechanical cotunneling process. Recently, various single-electron transistors based on silicon-on-insulator (SOI) substrate have been demonstrated. Coulomb blockade oscil-lation is attributed to the formation of randomly distributed Coulomb islands separated by tunnel barriers formed by the SOI substrate [1]–[12]. Matsuoka et al. [13] have observed the Coulomb blockade at lower temperature (100 mK) by six-QD-coupling in a Si metal-oxide-semiconductor (MOS) field-effect-transistor (FET) structure with dual gate. Park etal. [14] have also reported a dual-gate-controlled SET based on
SOI structure that exhibited Coulomb blockade phenomena by three-QD-coupling. Such multi-QD-based SETs are conducive to more stable single-electron circuits because coupled dots are defined by independently controllable gates, which are
Manuscript received January 11, 2003; revised August 15, 2003. This work was supported by The National Science Council, Republic of China, under Con-tract NSC92-2215-E-492-008.
S.-F. Hu and C.-L. Sung are with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
Y.-C. Wu is with the National Nano Device Laboratories, Hsinchu 300, Taiwan, R.O.C., and is also with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
C.-Y. Chang and T.-Y. Huang are with the Institute of Electronics, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TNANO.2003.820784
designed to separately control the tunneling potential barriers to compensate for variations due to size fluctuation in QDs [13], [14]. Kim et al. [15], [16] reported an electrically induced quantum dot SET in SOI nanowire that showed Coulomb oscillation and movement of the oscillation peak in two inde-pendently controllable tunnel junctions. However, the scaling of their device, even though not limited by lithography, is limited by the controllability of chemical vapor deposition (CVD) and reactive ion etching (RIE) processes [15], [16]. Here we present our experimental work using electron-beam (e-beam) direct writing combined with oxidation to achieve thin and narrow wires on SIMOX wafers. Specifically, a dual-gate-controlled SET was successfully fabricated by self-aligned polysilicon sidewall spacer depletion gates on the SOI nanowire. The Coulomb island is determined by the thickness as well as the width of the nanowire, and its length is defined by the separation between two polysilicon sidewall spacer gates, which are formed by electron beam lithography combined with the sidewall spacer processes. The Coulomb oscillations and Coulomb staircase phenomenon by multidot coupling at low temperature are successfully demonstrated.
II. EXPERIMENTAL
The SET in this study was fabricated using SIMOX wafers fabricated on p-type Si substrates, with a thin 60-nm silicon layer on top of a 400-nm buried SiO . After depositing a 10-nm capping oxide, the top silicon layer was doped by phosphorous ion implantation at a dose of ions/cm and with an energy of 40 kV. The doping results in a significant drop in the silicon sheet resistance to around . Afterwards, the silicon device layer was thinned down by a sacrificial oxidation with subsequent oxide strip. E-beam direct writing, by a Leica Weprint 200 system with NEB22A e-beam resist, was then employed to define 80-nm-wide narrow lines. After pattern transfer, the 80-nm-wide silicon wires were further thinned and narrowed, and a 20-nm gate oxide was sub-sequently grown at 925 C for 43 min in oxygen which served to further reduce the silicon wires’ dimension. A TEOS SiO layer was then deposited, patterned using e-beam lithography, and RIE etched to form TEOS narrow bar perpendicular to the nano silicon wire. To further reduce the TEOS width from 80 to 40 nm, wafers were dipped in 5% diluted HF solution for 30 s. Next, a 10-nm-thick oxide was thermally grown in dry at 800 C for damage curing, which also formed a good quality
Fig. 1. Scanning electron microscopy (SEM) picture of the self-aligned polysilicon sidewall spacers abutting the narrow TEOS bar.
Fig. 2. Schematic diagram of the self-aligned dual-gate-controlled SET structure.
gate oxide on the exposed nano silicon wire. The thickness of the final SOI layer is around 3 nm [7]. Afterwards, an in-situ -doped 150-nm-thick polysilicon layer was deposited using LPCVD. This was followed by an RIE etching of the poly-Si layer in reactive ion plasma to form self-aligned sidewall polysilicon spacers abutting the TEOS narrow bar, as shown in Fig. 1. After depositing another 110-nm-thick TEOS oxide layer and contact patterning, aluminum metal film was deposited and patterned to form the metal control gate on top of the active de-vice area, and also to provide electrical contacts to the dede-vice. Fig. 2 shows a schematic of the fabricated dual-gate-controlled SET. The corresponding cross sectional view is shown in Fig. 3, indicating biasing electrodes and major geometric parameters. It should be noted that the two polysilicon sidewall spacers, when properly biased negatively, serve as the lower gates to induce two depletion regions in the nano silicon wire beneath the thin 10-nm gate oxide. As a result, single QD of SET operation is formed in the active channel of the nano silicon wire by nega-tively biasing the lower gates. The top metal control gate, posi-tioned over the top of the two lower spacer gates, was designed to control the tunneling potential barriers to compensate for vari-ations due to size fluctuation in QD. The thickness of the control gate oxide is 110 nm, while the thickness of the gate oxide un-derneath the polysilicon spacer gates is 10 nm. The width of the
Fig. 3. Cross-sectional drawing of the self-aligned dual-gate-controlled SET.
Fig. 4. Drain current versus control gate voltage measured atT = 300 K. The source–drain biases are 1 and 100 mV.
sidewall spacer gate is 84 nm, and the space between the two spacer gates, which is the width of the TEOS nano bar, is around 40 nm. Thus, Coulomb island with feature size smaller than that characteristic of the state-of-the-art e-beam lithography is achieved in our structure. The device characteristics were mea-sured by an HP4156B parameter at 300 and 4.2 K in liquid he-lium cryogenic probing system.
III. RESULTS ANDDISCUSSION
Drain current versus control gate voltage measured at are shown in Fig. 4 for two drain-to-source biases of 1 and 100 mV. Typical MOSFET I–V characteristics were ob-served. The dependence of drain-to-source current on the lower gate (i.e., polysilicon spacer) voltage at 300 K, with the con-trol-gate voltage as a parameter, is shown in Fig. 5. It can be seen that the drain current decreases rapidly with decreasing . This feature is indicative of the formation of an electrostatic tun-neling potential barrier below the polysilicon spacer gate, and the creation of nano-size quantum dots on the wire channel, thus cutting off the channel current. is cut off at various cutoff voltages of 0.2 V, 1.3 V and 1.6 V for different con-trol-gate voltages of 1 V, 1 V, and 3 V, respectively. The shift of the cutoff voltage to more negative value with increasing control-gate voltage implies that the cutoff is likely due to the
Fig. 5. MeasuredI 0 V characteristics at V = 1 mV and T = 300 K with various control gate voltage of00.1, 1, and 3 V.
Fig. 6. Measurements of source–drain current at a low temperature T = 4:2 K. The control metal gate voltage varies from 2.025 V to 3.228 V in steps of 60 mV.
channel current decrease by the lower gate-induced electrostatic potential barriers, rather than some charged defect fluctuation, which is uncontrolled and possibly occurs at the Si-SiO interface [17].
The drain-to-source current–voltage characteristics measured at a low temperature are plotted in Fig. 6 with the control-gate voltage from 2.025 to 3.228 V in steps of 60 mV. This is a clear indication of the Coulomb blockade effect. More-over, some of the curves depict Coulomb staircase (as indicated by arrows in Fig. 6) at different applied voltages. The origin of the Coulomb blockade effects shown in Fig. 6 observed when only the upper control gate bias is applied may be due to the roughness of the SOI nano wire, or the impurities in distributed electron islands separated by tunneling barriers could be formed by dopant fluctuations within the nanostructure [18]. Further-more, by applying negative voltage to the lower gates to induce depletion regions in the nano channel beneath the gate oxide, two electron-tunneling barriers are induced and a quantum dot is created between these two electrically induced barriers. In Fig. 7 we show the drain current–voltage characteristics of the device for a fixed lower gate voltage and a con-trolled-gate voltage , measured at 4.2 K. The corresponding Coulomb gap is found to be 50 mV. Due to the
Fig. 7. Drain current voltage characteristics of the device with a fixed lower gate voltageV = 00:5 V and control-gate voltage V = 2:341 V , measured at 4.2 K.
Fig. 8. Coulomb oscillations of the dual-capacitive coupled gate on the transport properties of nano tunneling channel at 4.2 K as a function of the top control gate voltage with resolved quantum levels for differentV ’s. V varies from 7.36 mV (bottom) to 11.79 mV (top) in steps of 1.1 mV.
limit of our measurement system, we can not support the data above 4.2 K.
The effects of the dual-capacitive coupled gate on the trans-port properties of the nano tunneling channel were also mea-sured. In Fig. 8, characteristics with respect to the control-gate are shown. The drain-to-source bias is varied be-tween 7.36 to 11.79 mV in steps of 0.9 mV, while the lower gate voltage is fixed at 0.5 V. When the lower gate voltage is biased at around 0.5 V, which is negative enough to form two small energy barriers for the quantum dot in the source-to-drain tunneling channel. In Fig. 8, characteristics show non-linear ones even at the peak . These results suggest that Coulomb diamond is not closed at peak position, which means that a multiple-island SET is formed [19], [20]. Elec-trons tunnel through the nano channel, and the quantized nature of the energy level inside the nano channel causes the observed
oscillation peaks. But it is thought that these barriers are formed mainly due to the lower gate-induced electrostatic potential. The complex periodic oscillation curve indicates the superposition of different modes. The current exhibits oscillations and the pe-riod is around 50, 100, and 150 mV, respectively. If we assume the island has a spherical shape, the dot capacitance cor-responds to the self-capacitance of a sphere with a diameter of 30 nm. This value is consistent with the device structure; in our device, the Coulomb island is determined by the thickness and width of the nanowire, the length is defined by the separation of the two spacer depletion gates which are formed by e-beam lithography combined with the spacer formation processes. The effective size of the Coulomb island should therefore be smaller than nm , due to further shrinkage by thermal ox-idation process and the electrical field effect. Assuming a dom-inant charging dot, the control gate capacitance
is estimated to be aF and the dot capaci-tance ( ) is around 6.4 aF. From these measurements, we obtain typical energy scales of the charging energy to be around 11.25 meV. However, the requirement for the charging energy is much larger than the thermal energy. According to the orthodox theory of single-electron tunneling, Coulomb oscillations and Coulomb blockade only matter, if the Coulomb energy is bigger than the thermal energy. Otherwise thermal fluctuations will dis-turb the motion of electrons and will wash out the quantization effects. The necessary condition is , where is Boltzmann’s constant and is the absolute tem-perature. This means that the capacitance has to be smaller than 1.03 aF for charging effects to appear at room tempera-ture. The patterned structure size can be estimated smaller than
nm for room temperature operation.
Park et al. [14] reported previously that they barely ob-served the Coulomb-blockade effect by enhancing the effect with increasing number of the coupled dots. In contrast, we have successfully demonstrated a SET with pronounced Coulomb-blockade effect by employing the dual-gate structure. This is probably due to the narrower width within and between the spacer depletion gates in our device, thus leading to two narrower barriers and the quantum dots, which are beneficial to the observation of the Coulomb-blockade effect.
IV. CONCLUSIONS
The electrically induced multiple quantum dots on a narrow silicon wire have been successfully demonstrated. The dual-gate-controlled device employs a narrow-channel (width 80 nm and thickness 60 nm) FET defined by e-beam lithography combined with self-aligned polysilicon sidewall spacers that serve as depletion gates. The I–V characteristics depict typical Coulomb gap characteristics of the single-elec-tron charging effect. The Coulomb oscillations by single dot coupling were observed at low temperature. The effective size of the Coulomb island is consistent with the device structure of a sphere with a diameter of 30 nm by thermal oxidation process and the electric field effect. Further reduction of the quantum dot’s size is promising with the proposed method that could lead to possible room temperature operation in the near future.
ACKNOWLEDGMENT
The authors gratefully acknowledge the technical support from members of National Nano Device Laboratories and also wish to thank Prof. S. M. Sze for a critical reading of the manuscript and C. D. Chen and W. Kuo (Academia Sinica) for their assistance in the electrical measurements.
REFERENCES
[1] R. A. Smith and H. Ahmed, “Gate controlled Coulomb blockade effects in the conduction of a silicon quantum wire,” J. Appl. Phys., vol. 81, no. 6, pp. 2699–2703, 1997.
[2] A. Tike, R. H. Blick, H. Lorenz, J. P. Kotthaus, and D. A. Wharam, “Coulomb blockade in quasimetallic silicon-on-insulator nanowires,”
Appl. Phys. Lett., vol. 75, no. 23, pp. 3704–3706, 1999.
[3] R. Augke, W. Eberhardt, C. Single, F. E. Prins, D. A. Wharam, and D. P. Kern, “Doped silicon single electron transistors with single island char-acteristics,” Appl. Phys. Lett., vol. 76, pp. 2065–2067, 2000.
[4] A. Tike, R. H. Blick, H. Lorenz, and J. P. Kotthaus, “Single-electron tun-neling in highly doped silicon nanowires in a dual-gate configuration,”
J. Appl. Phys., vol. 89, pp. 8159–8162, 2001.
[5] E. Leobandung, L. Guo, Y. Wang, and S. Y. Chou, “Observation of quantum effects and Coulomb blockade in silicon quantum-dot transis-tors at temperatures over 100 K,” Appl. Phys. Lett., vol. 67, pp. 938–940, 1995.
[6] L. Zhuang, L. Guo, and S. Y. Chou, “Silicon single-electron quantum-dot transistor switch operating at room temperature,” Appl.
Phys. Lett., vol. 72, pp. 1205–1207, 1998.
[7] S. F. Hu, W. Z. Wong, S. S. Liu, Y. C. Wu, C. L. Sung, T. Y. Huang, and T. J. Yang, “A silicon nanowire with a Coulomb blockade effect at room temperature,” Adv. Mater., vol. 14, pp. 736–739, 2002.
[8] D. Ali and H. Ahmed, “Coulomb blockade in a silicon tunnel junction device,” Appl. Phys. Lett., vol. 64, pp. 2119–2120, 1994.
[9] Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwdate, Y. Naka-jima, S. Horiguchi, K. Murase, and M. Tabe, “Fabrication technique for Si single-electron transistor operating at room temperature,” Electron.
Lett., vol. 31, pp. 136–137, 1995.
[10] H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma, “Coulomb Blockade Oscillations at room temperature in a Si quantum wire metal-oxide-semiconductor field-effect transistor fabri-cated by anisotropic etching on a silicon-on-insulator substrate,” Appl.
Phys. Lett., vol. 68, pp. 3585–3587, 1996.
[11] T. Sakamoto, H. Kawaura, and T. Baba, “Single-electron transistors fab-ricated from a doped Su-film in a silicon-on-insulator substrate,” Appl.
Phys. Lett., vol. 72, pp. 795–796, 1998.
[12] Y. Ono, Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kuri-hara, and K. Murase, “Fabrication method for IC-oriented Si single-elec-tron transistors,” IEEE Trans. Elecsingle-elec-tron Devices, vol. 47, pp. 147–153, 2000.
[13] H. Matsuoka, T. Ichiguchi, T. Yoshimura, and E. Takeda, “Coulomb blockade in the inversion layer of a Si metal-oxide-semiconductor field-effect transistor with a dual-gate structure,” Appl. Phys. Lett., vol. 64, pp. 586–864, 1994.
[14] J. W. Park, K. S. Park, B. T. Lee, C. H. Lee, S. D. Lee, J. B. Choi, K.-H. Yoo, J. Kim, S. C. Oh, S. I. Park, K. T. Kim, and J. J. Kim, “Enhance-ment of Coulomb blockade and tunability by multidot coupling in a silicon-on-insulator-based single-electron transistor,” Appl. Phys. Lett., vol. 75, pp. 566–568, 1999.
[15] D. H. Kim, J. D. Lee, and B.-G. Park, “Room temperature Coulomb os-cillation of a single electron switch with an electrically formed quantum dot and its modeling,” J. Appl. Phys., vol. 39, pp. 2329–2333, 2000. [16] D. H. Kim, S.-K. Sung, K. R. Kim, J. D. Lee, and B.-G. Park,
“Fabrica-tion of silicon-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire,” J. Vac. Sci. Technol.
B, vol. 20, pp. 1410–1417, 2002.
[17] A. Fujiwara, Y. Takahashi, K. Yamazaki, H. Hamatsu, M. Nagase, K. Kurihara, and K. Murase, “Silicon double-island single-electron device,” in Int. Electron Devices Meeting (IEDM) Tech. Dig., 1997, pp. 163–166.
[18] A. T. Tilke, F. C. Simmel, R. H. Blick, H. Lorenz, and J. P. Kotthaus, “Coulomb blockade in silicon nanostructures,” Progress Quantum
[19] Y. Ono, K. Yamazaki, and Y. Takahashi, “Si single-electron transistors with high voltage gain,” IEICE Trans. Electron., vol. E84-C, pp. 1061–1065, 2001.
[20] K. R. Kim, D. H. Kim, S.-K. Sung, J. D. Lee, B. G. Park, B. H. Choi, S. W. Hwang, and D. Ahn, “Single-electron transistors with sidewall depletion gates on a silicon-on-insulator nano-wire,” Jpn. J. Appl. Phys., vol. 41, pp. 2574–2577, 2002.
Shu-Fen Hu was born in Tainan, Taiwan, R.O.C.
She received the Bachelor degree in physics from Shoochow University, Taipei, Taiwan, in 1981, and the M.Phil. and Ph.D. degrees in physical chemistry from the University of Cambridge, Cambridge, U.K., in 1992 and 1995, respectively.
For eight years, she worked as a Process Engineer at semiconductor factories. From 1995 to 1997, she was with the National Tsing Hua University, Hsinchu, Taiwan, as a Postdoctorate. In 1997, she joined the National Nano Device Laboratories, Hsinchu, Taiwan, as an Associate Researcher. Her scientific research interests include nano structures and nanoelectronics. She is the author or coauthor of more than 30 publications in international journals.
Yung-Chun Wu received the B.S degree in physics
from the National Central University, Taoyuan, Taiwan, R.O.C., and the M.S. degree, also in physics, from the National Taiwan University, Taipei, Taiwan, in 1996 and 1998, respectively. He is currently pursuing the Ph.D. degree at the National Chiao-Tung University, Hsinchu, Taiwan.
From 1998 to 2002, he was an Assistant Researcher at the National Nano Device Lab-oratory, Hsinchu, Taiwan, engaged in research on single-electron transistors and electron-beam lithography technology. His Ph.D. research includes fabrication, simulation, and characterization of submicron LTPS TFT and novel nano-scale devices.
Chin-Lung Sung received the B.S. degree in
materials science from National Tsing-Hua Uni-versity, Hsinchu, Taiwan, R.O.C., in 1982. He is currently pursuing the Master degree at the National Chiao-Tung University, Hsinchu.
After his military service, he became a Semicon-ductor Process Engineer working in semiconSemicon-ductor factories from 1984 to 1993. In 1993, he joined the National Nano Device Laboratories, Hsinchu, as a Senior Technical Research Staff Member. He is coauthor of more than 15 publications in international journals.
Chun-Yen Chang (M’88) was born in Feng-Shan,
Taiwan, R.O.C. He received the B.S. degree in electrical engineering from National Cheng Kung University (NCKU), Taiwan, in 1960, the M.S. de-gree in tunneling in semiconductor-superconductor junctions and the Ph.D. degree in carrier transport across metal–semiconductor barrier, both from National Chiao-Tung University (NCTU) Hsinchu, Taiwan, in 1969.
In 1969, he became a Full Professor at NCKU. From 1977 to 1987, he established a strong electrical engineering and computer science program at NCKU where GaAs, Si, and poly-Si researches were established in Taiwan for the first time. Since 1987, he served consecutively as Dean of Research (1987–1990), Dean of Engineering (1990–1994), and Dean of Electrical Engineering and Computer Science (1994–1995) at NCKU. Simultaneously, he was serving as the Founding President of National Nano Device Laboratories (NDL), Hsinchu, from 1990 to 1997. From 1997 to 1998, he served as Director of the Microelectronics and Information System Research Center (MIRC), NCTU. In August 1998, he was appointed as the President of NCTU. As the National Chair Professor and President of NCTU, his vision is to lead the university for excellence in engineering, humanity, art, science, management and bio-technology.
Dr. Chang received the IEEE Third Millennium Medal in 2000. He is a Member of Academia Sinica and a Foreign Associate of the National Academy of Engineering.
Tiao-Yuan Huang (S’78–SM’87–F’95) was born
in Kaohsiung, Taiwan, R.O.C., on May 5, 1949. He received the B.S.E.E. and M.S.E.E. degrees from National Cheng Kung University, Tainan, Taiwan, in 1971 and 1973, respectively, and the Ph.D. degree in electrical engineering from the University of New Mexico, Albuquerque, in 1981.
He served two years in the Taiwan Navy and was with the Chung Shan Institute of Science and Tech-nology, Taoyuan, Taiwan, for another two years. He spent 14 years working in U.S. semiconductor indus-tries, where he held various technical and managerial positions. In 1995, he returned to Taiwan to become a Chair Professor with the National Chiao Tung University, Hsinchu, and Deputy Director in charge of Research and Develop-ment of the National Nano Device Laboratories, Hsinchu, Taiwan, in 1995.
Dr. Huang is currently on the program committee of the International Confer-ence on Solid-State Devices and Materials (SSDM). He served on the Technical Committee of the IEEE International Electron Devices Meeting (IEDM) in 1990 and 1991, respectively.
