A fully-settled linear behavior plus noise model for evaluating the digital stimuli of the design-for-digital-testability Sigma-Delta modulators

DOI 10.1007/s10836-007-5005-7

A Fully-Settled Linear Behavior Plus Noise

Model for Evaluating the Digital Stimuli

of the Design-for-Digital-Testability

- Modulators

Hao-Chiao Hong

Received: 12 September 2006 / Accepted: 8 May 2007 / Published online: 19 October 2007 © Springer Science + Business Media, LLC 2007

Abstract Evaluating the digital stimuli used in the design-for-digital-testability (DfDT)- modulator is a time-consuming task due to its oversampling and non-linear nature. Although behavioral simulations can sub-stantially improve the simulation speed, conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this partic-ular application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT

- modulator is presented to improve both the accuracy

and the speed of the behavioral simulations. The model includes the following parameters: the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the pro-posed model, the behavioral simulation results demon-strate a high correlation with the measurement data. On average, the SNR difference between the simula-tion and the measurement is –1.1 dB with a maximum of 0.05 dB and a minimum of –2.2 dB. Comparing with the circuit-level simulation using HSPICE, the behav-ioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the mixed-signal design with an embedded DfDT - modulator.

Responsible Editor: M. Lubaszewski H.-C. Hong (

_B

Department of Electrical and Control Engineering, National Chiao Tung University, Hsin-Chu, 300, Taiwan e-mail: hchong@cn.nctu.edu.tw

Keywords Design-for-digital-testability· Stimulus evaluation· Behavioral model ·

- modulator 1 Introduction

It has become a major challenge to test a system-on-chip (SoC) system-on-chip as such an integrated system typically consists of several complex components such as a digital signal processor (DSP) core, random logic, memory, and analog/mixed-signal (AMS) circuits. Each compo-nent in an SoC may require different automatic test equipment (ATE) to satisfy its unique testing charac-teristics. Among them, testing the AMS part is not only costly but also cumbersome. Conventionally, the AMS and the digital parts of a mixed-signal chip are tested sequentially to avoid interference between the analog and the digital signal paths. However, the sequential flow results in a long test time. The expensive mixed-signal ATE, the low noise test environment require-ment, and a long test time combined lead to a high test cost for the AMS circuits [1]. One example of such cir-cuits is the- modulator, a popular analog-to-digital converter (ADC) architecture for high resolution ap-plications. Testing such an ADC by traditional DSP-based functional tests requires a high-quality analog stimulus generator (ASG) and an ultra low noise testing environment.

To reduce the test cost and alleviate the debugging efforts on the test setup, unifying the testing interfaces completely in digital forms is an appealing approach. It benefits from reduced interference in the test environ-ment, using less expensive digital ATE, and an easier test setup. Due to the elimination of analog signal paths

on the loadboard, simultaneously testing the AMS and digital parts becomes possible. As a result, the test time can be reduced.

There are a variety of schemes proposed for test-ing AMS circuits with digital stimuli in Toner and Roberts [14], Haurie and Roberts [2], Roy et al. [13], and Venuto et al. [15]. In Roy et al. [13] and Venuto et al. [15], four-step exponential staircase waveforms were generated and used as their analog stimuli by feeding a pulse-width-modulated digital stimulus to an R-C low-passed filter. Then, the specific test items of the ADC are analyzed by the polynomial-fitting test algorithm. It successfully measured the gain error and the offset of the ADC under test in addition to the second and the third harmonic distortions.

In Hong [3], a design-for-digital-testability (DfDT) second-order - modulator with pure digital inter-faces in the test mode has been proposed. It is based on the- modulation based BIST scheme [4]. In the test mode, the digital stimulus DBSG is generated by a

bit-stream generator (BSG) which is a single-bit, digital

- modulator. Then, the DfDT modulator accepts the

repetitively applied digital bit-stream as its stimulus. Since it is a kind of functional test, all the specifications measured by conventional functional tests can be ob-tained by the digital stimuli as well. The measurement data show that the digital tests present a peak signal-to-noise ratio (SNR) up to 75.3 dB. In addition, the DfDT

- modulator has the advantages of a low hardware

overhead, a high fault coverage, a simple test setup, and the capability of performing at-speed tests [3].

The reconfigurable switched-capacitor input struc-ture in Hong [3] can be applied to various- mod-ulators as well. Simulations are necessary to choose the most suitable digital stimulus for the designated DfDT

- modulator’s architecture and the specified test

item. Due to the over-sampling and nonlinear nature of the- modulator, conventional circuit level simu-lation tools such as HSPICE will take prohibitively long simulation hours to evaluate numerous digital stimu-lus candidates. Besides, there are other shortcomings in HSPICE simulations. For example, thermal noise and flicker noise are hard to be incorporated with the simulations. To address the issue of long simulation hours, one alternative is to use behavioral simulations for acceleration [3, 8–10]. However, behavioral simu-lations can underestimate the DfDT modulator’s SNR performance in the test mode as shown in Hong [3]. A more accurate behavioral model is needed to improve the simulation accuracy.

In this paper, a fully-settled linear behavior plus noise (FSLB+N) model is proposed to enhance the simulation accuracy without compromising the fast

simulation feature provided by behavioral modeling. The model consists of the parameters including the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), and the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With this method, we show that the SNR results from our behavioral simulations are within 2.2 dB comparing with their corresponding measurement data.

The rest of the paper is organized as follows. Sec-tion2reviews the DfDT- modulator and explains why behavioral simulations are necessary for evaluat-ing the digital stimuli. Section3introduces the FSLB+N model for the DfDT- modulator. Simulation results of various cases are discussed and analyzed in Section4. Section5compares the measurement data with the sim-ulation results to show the accuracy and speed of our proposed FSLB+N model. Finally, Section6concludes.

2 Overview of the DfDT- Modulator

2.1 Circuit Architecture of the Modulator Under Test Figure 1 shows the schematic of a - modulation based DfDT second-order - modulator [3]. It will be used as the modulator under test (MUT) throughout this paper. The basic analog building blocks include two integrators and a comparator. The integrators are realized using the stray-insensitive switched-capacitor integrator shown in Fig.2, except that four additional DfDT switches (S1 to S4) are added to the first inte-grator. The MUT has two operation modes: the normal mode and the test mode. By setting T = 0 and DBSG=

1, the MUT operates in the normal mode. On the other hand, by setting T = 1 the MUT will operate in the test mode. In either mode, both integrators can still be represented by Fig. 2. The only difference is that the stimulus, Vs(n), in the test mode is

Vs(n) = XBSG(n) × VREF, (1)

where

XBSG(n) = 2DBSG(n) − 1, DBSG(n) ∈ {1, 0}. (2)

Here, XBSG(n) is defined as the signed digital stimulus

whose value is either 1 or –1.

Figure 3 depicts two possible test setups for the mixed-mode chips embedded with a DfDT modulator. The BSG can be implemented by software. A logic analyzer or PC-based ATE loads the generated digital stimulus and repetitively applies it to the MUT. The digital output of the MUT, Do, then feeds back to

Fig. 1 Schematic of the - modulation based DfDT second-order- modulator [3] Φ1d Φ1d Φ2&Do Φ2&Do Φ2&Do Φ2 Φ2 Φ2d Φ2d Φ2d Φ2d Φ2d Φ2d Φ2d Φ2d Φ1d Φ1d Φ1d Φ1d Φ1 Φ1 Φ1 Φ1 Φ1 Φ1 Φ1 Φ1 Φ2&DBSG Φ2&DBSG Φ2&DBSG Φ2&DBSG REF +V /2 REF +V /2 Φ2&Do Φ2&Do Φ2&Do Φ2&Do Φ1d T& Φ2&Do Vs Φ1d T& Φ1d T& Φ1d T& REF V /2 REF V /2 Cs2 Cr2 Cr2+ Cs2+ Cr1+ Cr1 Cs1+ Cs1 _C f2 Cf2+ Cf1+ Cf1 + + + + + SC S1 S3 S2 SD S4 COMP Do OPAMP1 OPAMP2 + SA SB =VCM Control logics – – – – – – – – – – – – – –

modulator can be designed to be built-in-self-testable by adding an embedded BSG and an output response analyzer [5] to further simplify the test setup.

2.2 Analysis of the MUT

Figure 4 illustrates the generic block diagram of the MUT. Traditionally, the behavior of the integrator is

REF V /2 REF +V /2 Φ1d Φ1d Φ1d Φ1d Φ2d Φ2d Φ2d Φ1 Φ1 Φ1 Φ1 Φ2d Φ2&Do Φ2&Do Φ2&Do Φ2&Do Φ2 Φ2 C_s+ C_r C_r+ C_s C_f C_pi+ C_pi C_f+ + + OPAMP + Vout + V_in – – – – – – – – –

Fig. 2 The fully differential stray-insensitive switched-capacitor summing integrator

modelled by a linear transfer function Si(z)/Ni(z), i ∈

{1, 2}. Therefore, their behavioral models can be ex-pressed by the difference equations of their input and output sequences [10,11]. Ideally, S1(z) = S2(z) =

Cs

Cfz

−1 _{and N}

1(z) = N2(z) = 1 − z−1 for the example

integrator. The actual transfer functions of the inte-grators depend on their circuit designs. On the other hand, the comparator can be easily described by if-then-else statements. Putting above equations together, the behavior of the- modulator can be simulated with a simple for-loop program.

An alternative way to estimate the performance of the - modulator is using an analytical method. Nonetheless, the- modulator is actually a nonlinear system owing to the comparator, even though all com-ponents were ideal. The non-linear nature makes an

Logic Analyzer /PC–based ATE D_BSG D_o Embedded BSG Embedded ORA DfDT Σ−Δ modulator

Mixed–mode chip under test

Pass/Fail Decision BSG

Software

+ Σ +Σ Y (z) o MUT E (z) 1 S (z) S (z)2 1 N (z) N (z)2 s X (z) ++ A/D D/A Σ – –

Fig. 4 The generic block diagram and pseudo-linear analytical model of the second-order MUT

accurate analysis of the- modulator very difficult. Yet the analytical results can still provide some prelim-inary information.

To simplify the analysis, the analytical model shown in Fig. 4 is widely accepted. The comparator (1-bit ADC) and the feedback 1-bit DAC are modelled by adding an additive and white quantization noise

EMU T(z). According to the analytical model, the

in-put/output (I/O) relationship of the second-order- modulator can be derived to be

Yo(z) = ST FMU T(z)Xs(z) + NT FMU T(z)EMU T(z), (3) where Xs(z) ≡ Vs(z) VREF, ST FMU T(z) = S1(z)S2(z) S1(z)S2(z) + N1(z)S2(z) + N1(z)N2(z), NT FMU T(z) = N1(z)N2(z) S1(z)S2(z) + N1(z)S2(z) + N1(z)N2(z), (4) and Yo(z) ≡ 2Do(z) − 1. (5)

Xs(z), EMU T(z), and Yo(z) represent the normalized

test stimulus, the normalized quantization noise, and the signed digital output of the MUT, respectively.

Yo(n) has a value of either 1 or –1.

Equation3indicates that Vs(z) is filtered by the

sig-nal transfer function (STF), ST FMU T(z), and EMU T(z)

is shaped by the noise transfer function (NTF),

NT FMU T(z), to appear at the digital output of the

- modulator. Since ST FMU T(z) has a low-pass and

NT FMU T(z) has a high-pass characteristic, the in-band

Vs(z) will be passed to the output while the in-band

EMU T(z) is attenuated by NT FMU T(z). As a result, the

remaining shaped quantization noise in the passband determines the SNR performance of the MUT.

Equation 3 is also a generic formula of a gen-eral single-bit - modulator’s I/O relationship [10]. Since the signed digital stimulus XBSG(z) comes from

a single-bit, digital - modulator, it can be ex-pressed by

XBSG(z) = ST FBSG(z)Xs(z)

+NT FBSG(z)EBSG(z). (6)

ST FBSG(z), NT FBSG(z), and EBSG(z) represent the

STF, the NTF, and the normalized quantization noise of the BSG respectively.

Recall that the stimulus Vs(z) is equal to XBSG(z) ×

VREFin the test mode. Substituting (6) into (3), the I/O

relationship of the MUT in the test mode will be

Yo(z) = ST FMU T(z)ST FBSG(z)Xs(z)

+ST FMU T(z)NT FBSG(z)EBSG(z)

+NT FMU T(z)EMU T(z). (7)

Equation7indicates that there are two shaped quan-tization noise sources in the output of the test mode enabled MUT. One comes from the BSG, the other is generated by the MUT itself. If the two shaped noises were uncorrelated and a suitable BSG is chosen such that

|ST FMU T(z)NT FBSG(z)EBSG(z)|

 |NT FMU T(z)EMU T(z)| (8)

in the passband, then Eq.7could be approximated by

Yo(z) = ST FMU T(z)ST FBSG(z)Xs(z)

+NT FMU T(z)EMU T(z) (9)

in the passband. Equation 9 is similar to Eq. 3, thus both modes should have similar measurement results. An intuitive approach to satisfy Eq.8is to select a BSG whose order is higher than that of the MUT. A question raises here: Are ST FMU T(z)NT FBSG(z)EBSG(z) and

NT FMU T(z)EMU T(z) actually uncorrelated when an

arbitrary BSG is applied? The shaped noise correlation mechanism is very complicated. It depends not only on the stimulus and the structure of the MUT, but also on the circuits of the MUT. Only the measurement data or the simulation results with a suitable model can provide the answer.

3 Fully-Settled Linear Behavioral Plus Noise Model Circuit designers usually rely on circuit-level simulators to obtain accurate simulation results. Unfortunately, it can take a long time before the simulations are

completed. The simulation time will get even worse for the over-sampling - converters since a large number of output samples have to be collected in order to analyze their performance. A general solution is to conduct simulations with a simplified behavioral model [8–10]. With such models, the simulation results could be acceptably accurate while the simulation time is greatly reduced.

Such a behavioral model for switched-capacitor

- modulators has been proposed in Malcovati [9]. The finite gain, the slew-rate, the unit-gain bandwidth, and a limited output swing of the OPAMP in the first stage are included in the simulations in addition to the KT/C noise of the switched-capacitors of the same stage and the sampling jitter. This model has been shown to be effective in making accurate predictions for the SNR performance of the- modulators; however, it is not appropriate for evaluating the digital stimulus as will be discussed later.

Because the goal of the behavioral simulations is to evaluate the test stimuli rather than the circuits, non-linear behavioral factors such as the finite slew-rates and the finite unit-gain bandwidths of the OPAMPs are excluded to make the behavioral model as simple as possible. In other words, the output responses of the integrators are assumed to be fully-settled in every clock cycle. With this assumption, the behavior of the integrator can be expressed by a simple linear differ-ence equation to reduce the simulation time. On the other hand, the comparator is also assumed to be ideal and noise free. The reason is that any error and noise induced by the comparator will be effectively attenu-ated by NT FMU T(z) [6,10]. Consequently, the errors

and noise caused by the comparator can be ignored. 3.1 Stray-Insensitive Integrator

Practical transfer function of an integrator depends on its circuit design. To simplify the behavioral model thus speeding up the simulations, only the signal indepen-dent circuit impairments are considered.

3.1.1 Operational Amplifier

Four basic static characteristics of the OPAMP are included in the model: the finite open-loop gain A, the offset voltage VOS, the parasitic input capacitance Cpi,

and a limited output swing. They are all assumed to be constants. Practical integrators always have some offsets. The offset may come from the mismatched devices in the OPAMP and the mismatched differential capacitors. Clock feed-through and charge injection mechanisms of unbalanced switches can induce some

offsets as well. To simplify the model, VOS is used to

lump all the offset factors together.

According to the charge conservation principle, the difference equation of the stray-insensitive integrator in the presence of these linear impairments of the OPAMP can be derived as

Vout(n) = Cf +Cf+C_A pi Cf +Cf+Cr+C_A s+Cpi Vout(n − 1) + Cs Cf +Cf+Cr+C_A s+Cpi Vin(n − 1) − Cr Cf +Cf+Cr+C_A s+Cpi VREFYo(n − 1) + Cr+ Cs Cf +Cf+Cr+C_A s+Cpi (VOS− VCM), (10)

where VCM = 0. Since Eq.10is a singled-ended

behav-ioral description, each of the capacitance in Eq.10is the result of the respective differential capacitors in series, i.e., CS= CS+/2 = CS−/2 and so forth. The capacitive

values will affect the calculation of the thermal noise power later. Additional if-then-else statements are used to clip the output signals of the integrator once they exceed the output swing limits. It has been shown that a small output swing may lead to considerable SNR degradation when the stimulus amplitude is close to the full-scale [9].

The behavioral model described above only simu-lates the quantization noise. The output of a practical

- modulator, however, contains shaped quantization

noise, thermal noise, as well as flicker noise. Due to the high SNR performance of the - modulator, these noises can not be ignored.

3.1.2 Thermal Noise

Each switched capacitor, the OPAMPs, and the refer-ence supplies induces some thermal noise. A uniformly distributed random sequence is suitable for represent-ing this type of noise. Let Ri(n), i ∈ {1, · · · , 7} be

uni-formly distributed random sequences with an output range in-between −1 to 1. In theory, such a sequence has a power of one third. Consequently, a thermal noise source whose power is PN can be represented by a

noise sequence√3PNRi(n).

The noise sequences are added to the model accord-ing to the circuit operations. For instance, a switched-capacitor induces a total thermal noise power of KT/C to its sampled data where C represents the sampling ca-pacitance [12]. During the period when1is active, Cs

two noise sequences,3KT_C

s R1(n) and



3KT

Cr R2(n), are

added to the respective signals. When2 is active, Cs

and Crwill sample VCMin parallel. The noise sequence,



3KT

Cs+CrR3(n), is added accordingly. The transfer

coeffi-cient of each noise sequence is the same as that of the corresponding sampled signal.

The thermal noise of the reference supplies is in-cluded by replacing their fixed values in Eq.10with the following noise sequences

Vcm(n) =  3PT NVCMR4(n) (11) and Vre f(n) =  3PT NV REFR5(n) + VREF. (12)

Finally, the noise sequence

Vnop(n) = VOS+



3PT N OPR6(n) (13)

takes over the role of VOS in Eq. 10 because both

PT N OP and VOS of the OPAMP are input-referred

results. In the above equations, PT N OP represents the

input-referred thermal noise power of the OPAMP, while PT NVCMand PT NV REFdenote the thermal noise

powers of the reference supplies VCMand VREF

respec-tively. These noise powers can be estimated by proper simulations such as the ac noise analysis of HSPICE.

The resulting difference equation of the integrator incorporated with the thermal noises is formulated by

Vout(n) = Cf +Cf+C_A pi Cf +Cf+Cr+C_A s+Cpi Vout(n − 1) + Cs  Vin(n − 1) +  3KT Cs R1(n − 1)  Cf + Cf+Cr+Cs+Cpi A − Cr  Vre f(n − 1)Yo(n − 1)+  3KT Cr R2(n − 1)  Cf + Cf+Cr+Cs+Cpi A + [Cr+ Cs]  3KT Cs+CrR3(n) + Vcm(n)  Cf + Cf+Cr+Cs+Cpi A + Cr+ Cs Cf + Cf+Cr+Cs+Cpi A Vnop(n). (14)

It is important to note that since each switched capacitor is switched independently, the random se-quences should be independently generated.

A question is that is it necessary to take all thermal noise sources into account? For a normal- modula-tor, the thermal noise of the first stage will dominate due to the modulator’s noise shaping property [10]. That is why the model in Malcovati [9] only takes

the KT/C of the first stage into account while still providing satisfactory predictions.

For the DfDT modulator operating in the test mode, the scenario is different. In fact, the thermal noise leads to two contradictory effects on the MUT operating in the test mode. First, it increases the in-band noise power, which is not desirable. On the other hand, it is also a nature source that dithers the internal signals of the MUT. Note that dithering is beneficial for the test mode enabled MUT as it effectively reduces the correlation between signals [10]. Such a technique is widely applied to enhance the performance of - modulators [10]. Because the shaped noise correlation is a major concern in the test mode, excluding any noise source may lead to incorrect results of the shaped noise correlation and reduce the SNR prediction accuracy. Consequently, we suggest to include all thermal noise sources in the simulations.

3.1.3 Flicker Noise

In addition to thermal noise, the OPAMPs also induce flicker noise whose power spectral magnitude is in-versely proportional to the frequency. The flicker noise plays the same role as that of the thermal noise and thereby is necessary to be included in the model.

Circuit-level simulators such as HSPICE usually do not provide any embedded command to involve the flicker noise in transient analysis simulations. However, a time-domain flicker noise representation is compul-sory for the simulation.

Here, the flicker noise is generated by filtering a uniformly distributed random sequence, R7(n), through

the digital integrator whose transfer function is _1−z1−1.

A constant, Kf, is used to scale the computed sequence

such that the sequence has a similar power to that ob-tained from the ac input-referred flicker noise analysis. Finally, it is added to the model by modifying Eq.13 to be Vnop(n) = VOS+  3PT N OPR6(n) +Kf m=n  m=1 R7(m). (15) 4 Simulation Results

A large number of behavioral simulations are con-ducted to check the significance of every parameter in the FSLB+N model. The design and test setup parame-ters in Hong [3] were used for the experiments. VREFis

set to±2.8 V. The stimulus amplitude and frequency are set to –6 dBFS and 21/128K times the sampling frequency respectively unless otherwise noticed. The oversampling ratio (OSR) is set to 128 and the output samples taken for the spectral analysis are 128K points. Five different types of stimuli are simulated includ-ing the analog one in the normal mode and four digital ones in the test mode. The digital stimuli are generated by the second-, the third-, the fourth-, and the fifth-order BSGs adopted from Kuo et al. [7].

Similar to the practical measurement results, the random nature of the added noises will vary the sim-ulation results of the same test from time to time. To alleviate the randomness, each simulated SNR result is an average of the eight simulation results.

4.1 Ideal Case

Figure 5 depicts the relationship between SNR and stimulus amplitude with ideal OPAMPs and an ideal comparator. Additionally, no noise is applied. The re-sults show that the analog stimuli present lower SNR results than their digital counterparts. The higher order the BSG is, the higher SNR the MUT has. Obviously, these results are incorrect. In fact, the output bit-streams of the test mode enabled MUT are identical to its input ones separated by a two-clock delay. In other words, the ideal MUT does not generate any quantization noise (EMU T(z) = 0) in the test mode.

Figure5also reveals the possible limitation of using high-order BSGs. The fourth- and fifth-order BSGs are not suitable for the test in which the stimulus amplitude is higher than−5 dBFS. Such a high stimulus amplitude will overload the MUT and/or the BSGs and severely deteriorate the test results.

–60 –50 –40 –30 –20 –10 0 20 30 40 50 60 70 80 90 100 110 120 Stimulus Amplitude (dBFS) SNR (dB) Analog stimuli The 2nd order digital stimuli The 3rd order digital stimuli The 4th order digital stimuli The 5th order digital stimuli

– – – –

Fig. 5 SNR vs. stimulus amplitude with ideal circuits

4.2 Finite OPAMP Gain

Figure6shows how finite OPAMP gains affect the SNR results. The simulation results contradict with those of the ideal case. The analog stimuli now present higher SNR results than their digital counterparts. The finite OPAMP gains dramatically degrade the tested SNR results of the digital stimuli even if the gains are as high as 120 dB. It is because the finite OPAMP gains make the transfer functions of the integrators no longer having a pole at dc. Thus the integrators leak some of their input signals to the output. The smaller the OPAMP gain is, the more the leakage will be. The leaked signals excite the MUT and result in nonzero

EMU T(z).

Recall that EBSG(z) is a part of the digital stimulus.

The finite OPAMP gains leak it through the two inte-grators to the comparator where EMU T(z) is generated.

Consequently, EMU T(z) has a strong correlation to

EBSG(z). The correlation makes the approximation of

Eq.9invalid and the in-band quantization noise power increases.

Figure7shows the simulated SNR vs. the stimulus amplitude in which only the 75 dB OPAMP gains are considered. In general, the digital stimuli generate poor SNR results than their analog counterparts. Their dif-ferences can be more than 16 dB. The only exception is the scenario when the stimulus amplitude is−60 dBFS. To provide more insights with respect to the shaped noise correlation, Fig. 8 illustrates the simulated out-put spectrum of the MUT with the −40 dBFS, third-order modulated digital stimulus. There are many spurs that deteriorate the tested result. Similar spurs can be found in the output spectrum of a single-bit first-order - modulator that also suffers from

40 60 80 100 120 140 70 75 80 85 90 95 OPAMP Gain (dB) SNR (dB)

The analog stimulus The 2ndorder digital stimulus The 3rd order digital stimulus The 4th order digital stimulus The 5th order digital stimulus–

– – –

60 50 40 30 20 10 0 20 30 40 50 60 70 80 Stimulus Amplitude (dBFS) SNR (dB) Analog stimuli The 2nd order digital stimuli The 3th order digital stimuli The 4th order digital stimuli The 5th order digital stimuli

– – – – – –

– – – –

Fig. 7 SNR vs. stimulus amplitude with OPAMP gains of 75 dB

the correlation between its input and the quantization noise [4].

4.3 Offset Voltage and Finite Output Swing

The offset was never considered as an important factor in previous behavioral models [8–10]. However, the test accuracy of the digital stimulus is actually much improved due to the unavoidable offsets of the inte-grators. Excluding the offset will introduce significant simulation errors. Figure9plots the stimulated SNRs with different stimulus amplitudes. Both OPAMPs are assumed to have a 75 dB gain and a 410μV offset.

Comparing Fig.9with Fig.7, the digital stimuli now show much higher SNR results. The reason can be better understood by examining Fig. 10. This illustra-tion plots the output spectrum of the MUT with the

103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Frequency (Hz) Normalized PSD (dBFS/bin) 103 104 105 106 107 160 140 120 100 80 60 40 20 0 Cumulative THD+N Power (dBFS) Cumulative THD+N – – – – – – – –

Fig. 8 Output spectrum of the MUT with the third-order, −40 dBFS digital stimulus. Only the 75 dB OPAMP gains are considered –60 –50 –40 –30 –20 –10 0 20 30 40 50 60 70 80 Stimulus Amplitude (dBFS) SNR (dB) Analog stimuli The 2nd order digital stimuli The 3rd order digital stimuli The 4th order digital stimuli The 5th order digital stimuli

– – – –

Fig. 9 Stimulated SNR vs. stimulus amplitude. The OPAMPs have the same 75 dB gain and 410μV offset voltage

same −40 dBFS, third-order digital stimulus applied to Fig. 8. The in-band spurs become much less signif-icant implying that the offsets help de-correlating the shaped noises. Recall that - modulators generate pulse-density-modulated output bit-streams. Since the generated signed digital stimulus, XBSG(z), contains no

dc term while the signed digital output of the MUT (Yo(z)) does, these two bit-streams are not likely to

be highly correlated. As a result, the shaped noise correlation is mitigated.

Figure11shows the SNR differences between with and without offset voltages when the OPAMP gains are all 75 dB and the stimulus amplitude is−40 dBFS. Although the offsets do not affect the test results of the conventional analog stimulus, they do have profound effects on the digital ones. Without any

103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Frequency (Hz) Normalized PSD (dBFS/bin) 103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Cumulative THD+N Power (dBFS) Cumulative THD+N

Fig. 10 Output spectrum of the MUT with the third-order, −40 dBFS digital stimulus. The gains and offsets of the OPAMPs are 75 dB and 410μV respectively

105 10 4 10 3 10 2 0 5 10 15 20 25 Offset Voltage (V) SNR difference (dB)

The analog stimulus The 2nd order digital stimulus The 3rd order digital stimulus The 4th order digital stimulus The 5th order digital stimulus

– – – – – – – –

Fig. 11 SNR difference between with and without offset volt-ages. The OPAMP gains are 75 dB

offset, all digital stimuli only deliver SNR results around 35 dB. However, an offset voltage as small as 10μV instantly improves these values over 11 dB. Prac-tical offset of a properly designed OPAMP is around several millivolt, the digital stimuli thereby do not suf-fer from severe SNR degradation.

4.4 Thermal Noise and Flicker Noise

To predict the MUT’s SNR more accurately, the final parameters added to the FSLB+N model are the ther-mal noise and the flicker noise. Figure 12 shows the simulation results of the complete FSLB+N model.

According to the requirement of Eq.8, the intuition suggests using the BSG with the highest possible order. Indeed, the second-order BSG does provide a smaller SNR result than the other BSGs do in most of the tests.

60 50 40 30 20 10 0 20 30 40 50 60 70 80 Stimulus Amplitude (dBFS) SNR (dB)

Conventional analog stimuli The 2nd order digital stimuli The 3rd order digital stimuli The 4th order digital stimuli The 5th order digital stimuli

– – – – – – – – – –

Fig. 12 SNR vs. stimulus amplitude of the MUT with the com-plete FSLB+N model 103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Frequency (Hz) Normalized PSD (dBFS/bin) 103 104 105 106 107 –160 –140 –120 –100 –80 –60 40 20 0 Cumulative THD+N Power (dBFS) Cumulative THD+N power – –

Fig. 13 Output spectrum of the MUT with the third-order, −40 dBFS digital stimulus using the complete FSLB+N model

However, the simulation results indicate the fourth-order BSG is inferior to the third-fourth-order one for testing the peak SNR, even though the fourth-order stimulus does contain much less in-band noise than the third-order one as shown in Fig.5.

The simulation results also indicate that the fifth- and the fourth-order BSG candidates are not suitable for the test that requires a stimulus amplitude larger than −5 dBFS. The third-order BSG is found to be the most appropriate for general tests of the MUT.

Different MUTs may have different choices. With the proposed FSLB+N model, design engineers can design their own BSG structures and check their per-formance within a short turnaround time.

Figure13shows the output spectrum of MUT with the complete FSLB+N model. The same −40 dBFS, third-order digital stimulus was applied. Comparing it with Fig. 10, a noise floor appears. To demonstrate that the FSLB+N model can be used for projecting and evaluating the performance of the digital stimuli, Fig.14 illustrates the measured output spectrum of the MUT with the same digital stimulus as a reference. As can be seen, Figs.13and 14show a great resemblance.

5 Performance of the FSLB+N Model 5.1 Model Accuracy

To check the accuracy of the proposed FSLB+N model, the simulation results are compared with the measure-ment data of the DfDT second-order - modula-tor manufactured by a 0.35 μm CMOS mixed-signal process. The measurements were done at a sampling rate of 32 MHz, which is the measured maximum speed of the test chip operating in the normal mode without

103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Frequency (Hz) Normalized PSD (dBFS/bin) 103 104 105 106 107 –160 –140 –120 –100 –80 –60 –40 –20 0 Cumulative THD+N Power (dBFS) Cumulative THD+N power

Fig. 14 Measured output spectrum of the MUT with the third-order,−40 dBFS digital stimulus

significant SNR degradation. At this extremely high sampling rate, the effects of a finite bandwidth and slew rate of the OPAMPs will be the most significant. The rest of the test setups such as the stimulus frequency, the reference voltages, and so on are the same as those applied to the behavioral simulations mentioned above. The third-order BSG is used to conduct the experi-ments in the test mode.

Figure15compares the simulation results of Figs.7, 9, and12with the measurement data of the MUT in the normal mode. Essentially, the behavioral simulation results with the complete FSLB+N model are consis-tent with the measurement data. The SNR differences between the measurement data and simulation results

60 50 40 30 20 10 0 –10 –5 0 5 10 Stimulus Amplitude (dBFS) SNR differences (dB)

Considering OPAMP gains only Consiering OPAMP gains and offsets With complete FSLB+N model

– – – – – –

Fig. 15 SNR differences between the measurement data and corresponding simulation results of the MUT in the normal mode

60 50 40 30 20 10 0 –10 –5 0 5 10 Stimulus Amplitude (dBFS) SNR differences (dB)

Considering OPAMP gains only Considering OPAMP gains and offsets With complete FSLB+N model

– – – – – –

Fig. 16 SNR differences between the measurement data and corresponding simulation results of the MUT in the test mode

show an average value of 0.2 dB with a maximum value of 1.1 dB and a minimum value of−0.8 dB. As shown, the finite gains and nonzero offsets of the OPAMPs are less critical for simulating the MUT operating in the normal mode. The noise sources dominate the simula-tion accuracy.

The comparison results of the test mode enabled MUT are different as shown by Fig.16. The simplest model considering only the finite OPAMP gains gives the worst SNR prediction. The SNR differences be-tween corresponding measurements and simulations range from −11.3 to 10.1 dB. Including the offsets ef-fectively improves the SNR differences to be no worse than −5 dB. As such, including the offsets to the be-havioral model is essential to achieve a more precise simulation for the MUT operating in the test mode. Aside from these, another concern is that what will happen if the modelled offset values are different from what the MUT actually has? As Fig. 11indicated, the accuracy of the offsets are insensitive in most cases as long as they are nonzero.

The noise sources further improve the simulation accuracy. The SNR differences between the measured data and the corresponding simulation results using the complete FSLB+N model range from 0.05 to−2.2 dB with an average of−1.1 dB. This average value is 1.3 dB lower than that of the normal mode case. In other words, the MUT exhibits an extra 1.3 dB noise power when the test mode is enabled.

Figure 17 illustrates the output spectra of the peak SNR test for further analyze the differences between the measured data and simulation results. The same third-order,−6 dBFS digital stimulus were

103 104 105 106 107 –120 –100 –80 –60 –40 –20 0 Frequency (Hz) Normalized PSD (dBFS/bin)

Measured output spectrum Simulated output spectrum

Fig. 17 Measured and simulated output spectra of the MUT with the same third-order,−6 dBFS digital stimulus

applied. Both measurement and simulation show al-most the same high frequency noise components, but their in-band noise floors look different. The measured spectrum of the digital stimulus shows some spurs that are less significant in the simulated one. They are absent in the measured output spectrum of the corresponding analog stimulus as well. It implies that some signal coupling mechanisms of the fabricated MUT inter-modulate the test stimulus tone to the high frequen-cies. Since the digital stimuli contain significant high frequency shaped noises, these noises will be inter-modulated into the passband as well. Consequently, the in-band noise power increases. The simulation re-sults can be improved by adding more comprehensive parameters to the model such as those for capacitive crosstalk, the nonlinearity of the OPAMP gains, and other inter-modulation mechanisms at the cost of in-creased modeling complexity and a longer simulation time.

5.2 Simulation Time

Table1compares the simulation times and results of two tools on the same computer. The first one used MATLAB with the proposed FSLB+N model. The other exerted HSPICE. The measurement result was

also listed as a reference. Due to the extremely long simulation time, the sample points taken from the HSPICE simulation are limited to 8,292. As shown, even the sample points of the MATLAB simulation are 17 times more, the behavioral simulation is still 694,500 times faster and provides an SNR result within 2.2 dB of the measured data. The SNR obtained by HSPICE is lower because neither any noise nor any offset was taken into account. The limited sample number for analysis also reduces the prediction accuracy.

6 Conclusion

In this paper, an FSLB+N model for the DfDT - modulator is presented. Our goal is to improve the simulation time and accuracy in the test mode. The model considers the finite open-loop gains, the off-sets, the limited output swings, the flicker noises of the OPAMPs, and the thermal noises induced by the switched capacitors, the OPAMPs, and the reference supplies. The SNR differences between the measured data and the simulation results of the second-order MUT have a mean value of −1.1 dB, a maximum of 0.05 dB, and a minimum value of −2.2 dB. Com-paring with the conventional circuit-level simulation, the behavioral simulation with the FSLB+N model is 1,190,000 times faster while it achieves compatible accuracy. The simulation results can be improved by adding more comprehensive parameters such as those for capacitive crosstalk, nonlinearity of the OPAMP gains, and other inter-modulation mechanisms at the expense of increased modeling complexity and simula-tion time. The proposed model not only can be used to evaluate the digital stimulus candidates, but also can be used in system-level simulations of the mixed-signal design with an embedded DfDT- modulator.

Acknowledgments This work is supported by National Science Council, Taiwan R.O.C. under Grant NSC93-2215-E009-050. The author would also like to thank Dr. Hsien-Hsin S. Lee of Georgia Tech for his comments on this work.

Table 1 Performance of the test mode simulations with the same−6 dBFS digital stimulus

Tool Simulated samples Simulation time (s) Peak SNR result (dB)

MATLAB with FSLB+N 142,000 4.188 77.3

HSPICE 8,292 2.91 × 105 _72.0

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Hao-Chiao Hong received his B.S., M.S., and Ph.D. degrees in electrical engineering in 1990, 1992, and 2003 respectively, all from National Tsing-Hua University, Hsin-Chu, Taiwan.

He joined TSMC, Hsin-Chu, Taiwan in 1997 where he devel-oped DACs and PLLs for various customers. He also designed specialized IPs of the mixed-signal test vehicles for monitor-ing the processes. From 2001 to 2004, he was a senior man-ager of Intellectual Property Library Company, Hsin-Chu, Tai-wan where he led Mixed-Signal IP Department developing cus-tomized mixed-signal IPs.

Dr. Hong is currently an assistant professor of Electrical and Control Engineering Dept., National Chiao Tung University, Hsin-Chu, Taiwan.

His research interests include design-for-testability and built-in-self-test techniques for mixed-signal circuits, as well as high performance mixed-signal circuit design.