SerDes Applications
Wei-Zen Chen, Member, IEEE, and Guan-Sheng Huang
Abstract—This paper presents the design of a low-power
programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of27 1, 210 1, 215 1, 223 1, and231 1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power opera-tions of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 psrms, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18- m CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.
Index Terms—Clock multiplier unit (CMU), parallel feedback
shift register (PFSR), psuedorandom word generator (PRWG), SerDes.
I. INTRODUCTION
T
HE rapid development of high-speed serial link technolo-gies, such as HDMI, PCI Express, Serial ATA, SONET, and GbE, have driven the data rate beyond the multi-GHz range. They create strong demands for low-cost, reliable, and auto-matic testing methodologies of these high-speed transceivers. Pseudorandom bit sequences (PRBS) provide a convenient way of testing these devices and have been widely used for eye di-agram, bit error rate (BER), and jitter measurements. To facil-itate built-in self test (BIST) of these components, a low-cost PRBS generator and a BER tester (BERT) can be integrated with the transceiver as substitutes for expensive, external testers and equipments.Fig. 1 depicts the architecture of a serial link transceiver with BIST circuit. During the loop-back self-test mode, the test pattern is generated from a PRBS generator in the BIST circuit, traveling through the serializer, driver, an emulated channel (such as a jitter injection filter to stress the received eye dia-gram), and then received by the receiver for BER measurement. Manuscript received February 10, 2006; revised May 30, 2007. First pub-lished February 2, 2008; last pubpub-lished July 10, 2008 (projected). This work was supported in part by the National Science Council of Taiwan under Con-tract NSC-93-2220-E009-004 and ConCon-tract 93-EC-17-A-07-S1-001 and by Me-diatek Inc. This paper was recommended by Associate Editor R. Puri.
The authors are with the Department of Electronics Engineering, National Chiao-Tung Univeristy, Hsin-Chu, 300 Taiwan, R.O.C. (e-mail: wzchen@ alab.ee.nctu.edu.tw).
Digital Object Identifier 10.1109/TCSI.2008.916507
Fig. 1. Serial-link transceiver with BIST for loop-back test.
The response of the device under test (DUT) for different length of PRBS patterns can reveal essential hints about the de-vice’s performance, such as driving capability, bandwidth, and jitter generation. For example, a clock and data recovery unit in general generates higher jitter when a longer length test pattern is fed in. Thus, it is more flexible to build in a pattern generator with selectable sequence length [1]–[5]. Moreover, to facilitate the BER measurement of a high-speed serializer and deserial-izer (SerDes), i.e., to take the impacts of the MUX and DEMUX (DUT) on the jitter performance into accounts, a pseudorandom word generator (PRWG) complying with the word length of the MUX and DEMUX is desirable for loop-back test [5].
This paper presents a generic architecture of a parallel-feed-back multipattern PRWG with selectable mark densities [5]. A low-cost, low-power, 16-bit-wide PRWG for high-speed SerDes applications is demonstrated by the proposed technique. In addi-tion, an 8-phase, 1.25-GHz clock multiplier unit (CMU) is also integrated on the chip as a clock source for the 10-Gb/s trans-ceiver.
This paper is organized as follows. Section II describes the proposed parallel feedback shift-register-based PRWG. Con-ventional PRBS generators are based on a linear feedback shift-register (LFSR) architecture, which are operated at a full rate [1], [6], a half rate [2]–[4], [7], [8], [11], [12], or a quarter rate [9], [10] incorporating with multiplexers and demultiplexers. In contrast to the prior state-of-the-art, the proposed architec-ture, which can generate parallel random words at a relatively lower symbol rate, is more feasible to comply with the SerDes BIST, is capable of high-speed operation, occupies a smaller chip area, and consumes much less power. In addition, the mark density and the sequence length are also selectable. Section III describes a multiphase CMU for the SerDes applications. Low-noise, low-power, and high-speed operations are achieved by 1549-8328/$25.00 © 2008 IEEE
sults of both the PFSR-based PRW generator and CMU are pre-sented in Section IV. Finally, a conclusion is drawn in Section V.
II. PSEUDORANDOMWORDGENERATOR
To facilitate the characterization of a high-speed SerDes (including MUX and DEMUX on the transceiving path), a programmable, multi-pattern, PRWG generator complying with the word length of the MUX and DEMUX is desirable for BIST. According to CCITT recommendations [14], the following polynomials are implemented to generate pseu-dorandom words with sequence lengths of ,
, , , and , where (1) (2) (3) (4) (5) Fig. 2 shows a conventional programmable PRBS generator architecture [1], which is composed of an LFSR chain. To gen-erate the above polynomials, the outputs of five XORs of var-ious operations are fed back to the input of the finite state ma-chine through a 5:1 MUX. The pattern length is chosen by a 3-b pattern length select signal. Once the loop is configured with a designated feedback, the pattern length of “Dout” can be deter-mined accordingly.
Along with the increasing of the data rate, the clock frequency should be increased as well to trigger out the random bit streams. This imposes severe speed requirements of the LFSR digital logic circuits and consumes drastic power. Therefore, conven-tional BERT and PRBS generators are designed with silicon bipolar, SiGe BiCMOS, [1]–[4], [7]–[10], InP [11], or GaAs [12] technology, and the power dissipation is approximately sev-eral watts. Besides, standard PRB sequences have a mark den-sity ratio, which is defined as the average ratio of number of zeros to ones in a sequence, of about 1/2 [2]–[4], [6]–[12]. To simulate the test vehicle of a dc unbalanced code, mark densi-ties other than half, such as 1/4 or 1/8 are preferable [1], [5].
In order to facilitate parallel BER measurement and reduce the speed requirements of the logic circuitries, a PFSR-based PRWG with selectable mark densities of (1/2, 1/4, and 1/8) is proposed [5]. As a 16-bit-wide PRWG example, it is mainly comprised of 18 parallel feedback shift registers along with combinational logic. The extra two path (bits) extensions are utilized to incorporate with mark density control for up to 1/8, which will be explained later. To investigate the operating
Fig. 3. PFSR-based PRW generator (forn < 16).
principles of the PFSR-based PRWG in detail, the architectures for generating sequence length of , where and
, are discussed separately.
A. Case I : 16-bit-Wide PRW Generator (for ) Fig. 3 shows the circuit schematic of a PRWG with
, and the random word is 16-bit wide. The circuits shaded in gray are utilized for mark density control.
Let , , and represent the succeeding
random word ( ) that corresponds to different sequence lengths. According to CCITT recommendations, the following holds:
if (6)
if (7)
if (8)
In the three cases, the succeeding random words can be de-rived from its previous word ( ) and part of itself (
) through theXORoperations described in (6)–(8), which are implemented inXORoperators (XOR1-XOR3). For example, to generate a pseudorandom word of sequence length of , part of the next word can be derived from its
pre-vious word , while the other part is
derived from , where are also
gen-erated in the current word. On the other hand, to generate a pseudorandom word with sequence length of , part of the next word can be derived from its previous
word , and the other part is derived
from , where are also generated in
the current word. The succeeding words ( , , or ) are then fed back to the input of PFSR through 3:1 multiplexers, and the sequence length is selected by the multi-plexers.
B. Case II: 16-bit-Wide PRW Generator (for )
Also, let and represent the succeeding
random word ( ) that corresponds to different sequence length. According to CCITT recommendations, the following holds:
if (9)
if (10)
In this case, the succeeding pseudorandom word comes out with theXORoperations of data in the previous two words. For
Fig. 4. PFSR-based PRW generator (for32 > n > 16).
example, to generate a pseudorandom word with a sequence length of , the next two succeeding random words, , are derived from . On the other hand, to generate a pseudorandom word with sequence length of , the next two succeeding random words, , are derived from . Thus, this requires two register arrays (36 flip-flops) to store the previous two words. Fig. 4 shows the detailed circuit schematic. Here, and that correspond to different pattern lengths are fed back to the input of the PFSR through 2:1 multiplexers, and theXORoperators (XOR4 andXOR5) are utilized to implement (9) and (10). The sequence length of or is then selected by the 2:1 multiplexers .
C. Case III: A 16-bit-Wide Multipattern-Length PRW Generator (for )
In combination with cases I and II, a ( ), 5-pat-tern, 16-bit-wide programmable PRWG is illustrated in Fig. 5. The PRWG is mainly composed of an 18 2 register array, 18 4:1 multiplexers, 18 2:1 multiplexers, and five XORoperators to implement the pattern generation polynomials. Here, DFF (1–1) to DFF (1–18) store the previous word of the PRWG out-puts, and DFF (2–1) to DFF (2–18) store the current word. The two register arrays are connected in parallel feedback configu-ration. For ( , 31), the PRWG is configured as a two-stage PFSR, and the top multiplexers select one of the pat-tern lengths. Thus, the successive random words can be stored in the FIFO to derive the next pseudorandom word. As ( , 10, 15), the generator is reduced to a single-row PFSR, where the output sequence is selected by the bottom 4:1 multi-plexers.
The critical path of theXORoperators is encountered for the generation of pseudorandom word. As is described in Case I, since the random word at the output is 16-bit wide while the feedback path is 7-bit deep, the derivation of the succeeding random word relies on part of itself. Thus, it takes more oper-ations to fulfill the generation of a random word whose word length is longer than its feedback depth. Fig. 6(a) illustrates the detailed circuit schematic of the XORoperator for (XOR1). It takes about three gate delays in the critical path. To shorten the delay time, the Boolean variables of the pattern-gen-eration polynomials are substituted in a recursive form, which is described as follows.
Fig. 5. Programmable 16-bit-wide, 5-pattern PRW generator (n < 32).
To generate a PRW with a sequence length of , the th bit of a random word can be derived as
(11) where corresponds to different word lengths ( ).
We have
(12)
Thus, can be derived from and
in-stead of and . Fig. 6(b) illustrates the circuit schematic of the modified XOR operator after recursive sub-stitution according to (12), where the critical path in theXOR operator is reduced to a two-gate delay.
To sum up, the critical path delay time ( ) of a PRWG can be described as
(13) Here, and represent the setup time and the CK-to-Q delay of the flip-flop, and and denote the propagation delay of theXORgate and the multiplexer. The is a critical term ( ps) in . By means of the proposed recursive Boolean variable substitution, the symbol rate for random words generation can be increased by about 30%.
The 16-bit-wide random word is fed into a mark density con-troller to alter its mark density. When two adjacent bits of the PRB sequence are “and”ed together, a “1” appears at the output only when both of the bits are 1 and the probability of appearing “1” becomes 1/4. It stands to reason that a PRBS with a mark density of 1/8 can be achieved by “and”ing the adjacent 3 bits. Thus, for a mark-density control up to , extra bits (paths) extension are needed to store the adjacent bits. The ar-chitecture of the mark density controller (MDC) is shown in Fig. 7(a), which is composed of 16 subcells (MDC1–16). The subcell of the MDC is illustrated in Fig. 7(b), which consists of anANDgate and twoORgates. The mark density of 1/2, 1/4, or 1/8 is then determined by the two-bits select signal (S1, S2).
Fig. 6. (a)XORoperator. (b) ModifiedXORoperator (forn = 7).
Fig. 7. MDC. (a) Schematic of the MDC. (b) MDC cell.
TABLE I TRUTHTABLE OF THEMDC
The corresponding truth table for the MDC is summarized in Table I.
In summary, the proposed architecture can be extended to a generic PFSR-based PRW generator with selectable mark den-sity. For a -bit-wide PRWG with sequence length up to , patterns, and mark density up to , the PRWG can be con-figured as an register array, where
Fig. 8. GenericM-bit-wide, 2 0 1 PRWG with mark density up to 1=2 .
The detailed architecture is depicted in Fig. 8 [5]. In the ini-tial state, one of the flip-flops is preset to 1 to avoid the gener-ator being stuck at all zero. In contrast to conventional -rate PRBS generators that are composed of identical LFSR chains and at least registers, the proposed architecture is much more area-efficient and low power in generating pseu-dorandom words.
As an experimental prototype, a 16-bit-wide PRWG targeted for 16:1 10-Gb/s SerDes is realized. This corresponds to an ef-fective symbol rate of 625 MS/s for 10-Gb/s random bit gener-ation. The PFSR scheme is a breakthrough for generating high-speed pseudorandom words in a relatively low-cost CMOS tech-nology. Most important of all, it relaxes the operating speed of the digital logic circuits to save power.
III. CLOCKMULTIPLIERUNIT
The CMU is designed to provide a global clock for the PFSR PRWG and a 16:1 10-Gb/s data serializer. The serializer is com-posed of two-stage tree-like multiplexers. As the parallel to se-rial data conversion is achieved by means of time-division mul-tiplexing, to alleviate jitter accumulation and relax the loading effect at the buffer stage, the CMU is operated at 1.25 GHz and provides eight phases for 10-Gb/s operations. The archi-tecture of the CMU is depicted as shown in Fig. 9(a). Here, the 1.25-GHz output frequency is derived from a 625-MHz refer-ence clock. A conventional tri-state PFD based on true single phase clocking (TSPC) dynamic logic circuit is utilized in this design, as is shown in Fig. 9(b).
Fig. 10(a) shows the VCO architecture, which is basically a four-stage ring oscillator. Each delay stage has four input ter-minals. To accelerate the operating speed of the oscillator while consuming less power, negative skew delay compensation tech-nique is adopted [13]. In addition, the feedforward paths for the negative skew delay compensation (gray line) can keep the rising and falling times of the output waveform more balanced under various operating frequencies, which will be explained
Fig. 9. (a) CMU architecture. (b) Phase frequency detector.
below. The detailed circuit schematic of the proposed delay cell is illustrated in Fig. 10(b), which is composed of a complemen-tary differential pair (M1-M4) with tunable resistive loads. To balance the switching speed of the nMOS (M1-M2) and pMOS differential pair (M3-M4), the signal path of the pMOS pair is configured in a feedforward loop. Thus, a lower phase noise per-formance can be achieved thanks to a more symmetric output waveform. The resistive loads are comprised of a negative resis-tance (M5-M6) and a positive resisresis-tance (M9-M10) in parallel.
To reduce the sensitivity of the VCO core, its output fre-quency is adjusted by a dual-loop frefre-quency-tuning scheme. The coarse frequency tuning is accomplished by adjusting , while the fine tuning is achieved by changing the current ratio between the positive and negative resistance. The control voltage is converted to a differential control current though the frequency control unit (M13-M17) before being fed into the VCO. Also, since the control voltage is fully differential, the VCO has a higher immunity to common mode noise. As is increased, the loading of the delay stage is reduced for high-speed operation. On the other hand, as is reduced, the effective impedance loading is increased to slow down the VCO. In addition, two bleeding current sources M7 and M11 are injected at the tail nodes of the resistive load to avoid the VCO being driven into latched mode and solve the start-up problem.
Since the reference frequency of the CMU is as high as 625 MHz, for a low-noise operation, the response speed of the charge pump becomes critical. Fig. 11 illustrates the detailed circuit schematic of the charge pump circuitry, which is based on fully differential current-mode logic for both high-sensitivity and high-speed operations. The pumping currents are steered by the differential pairs (M1-M2) and (M3 -M4). When either
Fig. 10. (a) VCO architecture. (b) Delay cell.
Fig. 11. Charge pump circuit.
the UP or DOWN signal is asserted, the pumping up or down current is equal to . On the other hand, when both UP and DOWN are at high or low logic levels, the charge pump circuit is kept in the hold state. A second-order loop filter composed of , and is adopted in this design. The output voltages at and are utilized for VCO frequency control. In order to preset the output common-mode voltage of the pumping circuit to comply with the tuning circuit of the VCO, a continuous-time common-mode feedback loop (M9-M14) is utilized.
IV. EXPERIMENTALRESULT
The proposed PRWG and CMU have been integrated in a 10-Gb/s SerDes for loop-back BIST. Fig. 12 shows the chip micrograph of the 16:1 serializer. Implemented in an 0.18- m CMOS process, the chip size is about 1160 m 1040 m. The core size for the 16-bit-wide PRWG is about 500 m 250 m, and the CMU occupies a chip area of about 1000 m 250 m. Operating under a single 1.8-V supply, the power dissipation
Fig. 12. Chip photograph.
Fig. 13. Measured CMU. (a) Phase noise. (b) Clock jitter at 1.25 GHz.
for the PRWG is only 10.8 mW, and the CMU consumes about 8.7 mW.
The measured phase noise and the timing jitter of the CMU at 1.25 GHz are shown in Fig. 13(a) and (b). The loop bandwidth of the phase-locked loop is about 10 MHz. The phase noise at 10-kHz offset is about dBc/Hz, and is about dBc/Hz at 100-kHz offset. The timing jitter is only 3.56 ps . By the novelties of the VCO and the charge pump circuit, the proposed CMU utilizing a ring oscillator manifests a performance that is comparable to that of the LC-VCO-based CMU.
Fig. 14. Power spectra density of (a)2 0 1 PRBS @ 508 MS/s, (b) 2 0 1 PRBS @ 511:5 MS/s, (c) 2 0 1 PRBS @ 524:272 MS/s, and (d)2 0 1 PRBS @ 503:31642 MS/s.
The performance of the programmable PRW generator is characterized by the spectrum analyzer. For a nonreturn-to-zero pseudorandom bit sequence with pattern length of , its power spectra density can be described as [15]
(14) where is the bit time, and is the pattern length. In other words, consists of discrete spectral lines separated
by Hz.
In this experimental prototype, the measured maximum op-erating speed is around 500 MS/s due to layout parasitic, which can be applied for up to 8-Gb/s SerDes applications . The mea-sured power spectra density of PRW with pattern lengths of , , , and are shown in Fig. 14(a)–(d), respectively. The spacing of the spectral line agrees well with that described in (14), which means that the PFSR-based PRWG works properly for the various pattern generations. The spectral line spacing of a PRW sequence is less than 0.3 Hz in the 625-MS/s frequency range, which is beyond the resolution of the spectrum analyzer and is not shown here.
V. CONCLUSION
In summary, a generic PFSR based, programmable PRWG ar-chitecture and a low noise, multiphase CMU are proposed for high speed SerDes applications. The 16 bits wide PRWG ex-perimental prototype performs as a linear feedback shift reg-ister (LFSR) based counterpart with a 1 to 16 demultiplexer. It reduces the clock rate by 16 times, and is more feasible for parallel bit error rate measurement complying with multiplexer and demultiplexer. Most important of all, it consumes much less
power and is more area efficient compared to conventional ar-chitectures. Besides, a 1.25 GHz, 8 phase clock multiplier unit is realized. By the novelties of the VCO and charge pump cir-cuits, the CMU manifests comparable jitter performance to that of LC-VCO based PLL.
The benchmark of the proposed PRW generator performance is summarized in Table II. The proposed PFSR-based PRW gen-erator consumes much less power compared with those of con-ventional LFSR-based architecture [1]–[3], [6] and is more fea-sible as a test vehicle for a loop-back test combined with a mul-tiplexer and demulmul-tiplexer.
ACKNOWLEDGMENT
The authors wish to thank CIC for chip fabrication. REFERENCES
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Wei-Zen Chen (M’99) received the B.S., M.S.,
and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C., in 1992, 1994, and 1999, respectively.
He was with the Industrial Technology Research Institute (ITRI), Hsin-Chu, where he was involved with RF integrated circuit design in 1999. From 1999 to 2002, he was with the Department of Electrical Engineering, National Central University, Chung-Li, Tawian. In 2002, he joined the Department of Electronics Engineering, National Chiao-Tung University, where he is currently an Associate Professor. His research interests are integrated circuits and systems for high-speed networks and wireless communications.
Dr. Chen is a member of Phi Tau Phi.
Guan-Sheng Huang was born in Kaohsiung,
Taiwan, R.O.C., in 1980. He received the B.S. and M.S. degrees in electrical engineering from National Central University, Jhong-Li, Taiwan, R.O.C., in 2002 and 2005, respectively.
After graduation, he was with Himax Technolo-gies, Inc, Tainan, Taiwan, where he was involved with LCD source driver circuit design. In 2006, he joined FARADAY Technologies, Inc, Hsin-Chu, Taiwan, where he is currently an Engineer in the R&D Division. His research interest is CMOS high-speed circuit design for data communication.
