DDR SDRAM Controller

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www.latticesemi.com

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ip1010_02

DDR SDRAM Controller

October 2002 IP Data Sheet

Features

■ Performance of Greater than 200MHz in DDR Mode

■ Interfaces to JEDEC Standard DDR SDRAMs

■ Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits

■ Supports up to 8 External Memory Banks

■ Programmable Burst Lengths of 2, 4, or 8

■ Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0

■ Byte-level Writing Supported

■ Increased Performance Using Command Pipelining and Bank Management

■ Supports Power-down and Self Refresh Modes

■ Automatic Initialization

■ Automatic Refresh During Nomal and Power-down Modes

■ Timing and Settings Parameters

Implemented as Programmable Registers

■ Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available

■ Complete Synchronous Implementation

General Description

DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to the regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle on both edges of the clock signal, implementing burst mode data transfer.

The DDR SDRAM Controller is a parameterized core giving user the flexibility for modifying the data widths, burst transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank management, which is done by maintaining a database of “all banks activated” and the “rows acti- vated” in each bank. With this information, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write commands issued to the DDR SDRAM.

Block Diagram

Figure 1. DDR SDRAM Controller Block Diagram

Generic I/F Block

Command Execution Engine

Address

Chip Select

Initialization Control Logic

Data Bus Interface Block User

Interface Bus

DDR SDRAM Interface

Bus

Data in/out Data Mask Data Strobe Data_out

Data_in Cmd Address

Busy

Data_in Valid

Data_out Valid Cmd Address

On-chip

System Clk PLL clk

clk2x

Control

PCI, PowerPC,

AHB or Generic

Bus

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Lattice Semiconductor DDR SDRAM Controller

Since the DDR SDRAM Controller takes care of activating/pre-charging the banks, user only needs to issue simple read/write commands.

Functional Description

The DDR SDRAM Controller block diagram, illustrated in Figure 1, consists of four functional modules: the Generic Interface block, Command Execution Engine, Data Bus Interface block and the Initialization Control Logic.

Generic Interface Block

The Generic interface block contains the configuration registers: CFG0, CFG1, CFG2, and CFG3. These registers are updated when a LOAD_CFG command is received from the user. These registers contain the programmable DDR SDRAM timing parameters and can be changed by the user to suit the DDR SDRAM memory timings being used thus giving the flexibility to use any DDR SDRAM memory.

Command Execution Engine

The command execution engine is the main component of the DDR SDRAM controller. This block accepts com- mands from the “User Interface Bus” and keeps a record of bank open/close status. It accepts up to two commands at any time. Once a command is received, it decides whether to open the bank, close the bank or directly execute the READ/WRITE commands and apply the appropriate DDR SDRAM commands to the DDR SDRAM Memory.

Table 1 shows the different user interface commands supported.

To maintain throughput of data this block uses two state machines to process READ/WRITE commands received from the user interface. When the commands are continuously received, one state machine works in master mode and the other state machine works in slave mode. The state machine that receives the command first becomes the master and the other becomes the slave on receiving the second command. Once the master state machine com- pletes the command execution, the slave state machine execution is enabled.

This block also maintains an auto refresh counter, which refreshes the DDR SDRAM memory at the predetermined programmed intervals even during power down.

Table 1. DDR SDRAM Controller Generic I/F Commands

Data Bus Interface

The Data Bus Interface block controls the data flow between the User Interface bus and DDR SDRAM Memory interface bus. The data received from the Memory during a read operation is converted from a double data rate to single data rate; similarly the data to be written into the memory is converted from a single data rate to a double data rate.

During a write operation, depending on the data mask signals, the data is written or masked by the DDR SDRAM memory.

Command Name Cmd[2:0] Description

NOP 000 No operation.

READ 001 Initiate a burst read.

WRITE 010 Initiate a burst write.

LOAD CONFIG REG (Load_CFG)

011 Load controller configuration values. The controller use this command to load the CFG0/CFG1/CFG2/CFG3 registers.

LOAD MODE REG (Load_MR)

100 Load the Mode and Extended Mode register.

POWER DOWN 101 Put the DDR SDRAM into power-down or wake up from POWER DOWN.

SELF REFRESH 110 To enter into self refresh mode or get out of self refresh mode

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Lattice Semiconductor DDR SDRAM Controller

3 Initialization Control Logic

When the User sets the initialization bit (Bit 7 in the configuration register CFG0) using the LOAD_CFG command, this block starts initialization as specified in the DDR SDRAM specification document. The DDR controller initializa- tion can only be performed after the system power is applied and the clock is running for at least 200 µs. An initial- ization is required before any read/write command is issued to the DDR SDRAM memory.

User Interface Bus

In order to connect this controller to different bus standards Lattice provides the following “Bus Interface blocks”:

1. PCI Target Interface 2. Power PC Interface 3. AMBA-AHB Interface 4. Generic Bus Interface

The main function of these “Bus Interface blocks” is to trap all transactions on the respective bus addressed to the DDR SDRAM and translate them into Generic Interface commands.

Since all the buses have burst addressing which is greater than the burst supported by the DDR SDRAM memory, all the interfaces have an address generator block which generates the appropriate address depending on the requested burst.

In all the interfaces the data going in and out of the bus is stored in a sync FIFO block, which is used as a storage

buffer for read/write commands. During a read from the DDR SDRAM the data is sent to FIFO and is read by Bus

Interface block. During a write the data is first written into the FIFO before actually writing this data into the DDR

SDRAM.

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Lattice Semiconductor DDR SDRAM Controller

PCI Master Target Interface Block

The PCI Target Interface Block is used to Interface the Lattice DDR Controller IP core with a Lattice PCI Mas- ter/Target core. This interface allows easy usage of the Lattice DDR SDRAM Controller and a Lattice PCI Mas- ter/Target IP core in a PCI Bus environment. Figure 2 shows the system with a PCI Master/Target core

The following are the features of the PCI Target interface block:

• Parameterized data path widths of 32, 64 on the PCI Local Bus and the User interface bus of DDR control- ler.

• Read/Write of configurable registers through PCI memory space.

• Read/Write to DDR through PCI memory space.

• Supports Power down and self refresh commands for low power applications.

• Programmable burst length.

• Programmable FIFO Depth

• Automatic wake up from power down/self refresh by a Read/Write command.

Figure 2. Typical PCI System with Lattice DDR SDRAM Controller

PCI BUS MASTER1

PCI I/F Block

PCI BUS MASTER2

Lattice DDR SDRAM

Controller

SDRAM External Bank 0 (e.g. DIMM)

Data/2 Address/2

Control

PCI Bus

Command

Address

Dataout

Datain

Chip Sel 0 BusArbiter

Lattice PCI Master/

Target IP Core

Local Target Bus

DDR SDRAM Memory 0

4Mx8bit

DDR SDRAM Memory 1

4Mx8bit

DDR SDRAM Memory 2

4Mx8bit

DDR SDRAM Memory 3

4Mx8bit

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Lattice Semiconductor DDR SDRAM Controller

5 PowerPC BUS Interface Block

The Power PC Bus Interface block is used to interface with the Lattice DDR SDRAM Controller IP Core with the Power PC 60x Bus. This interface allows easy usage of the Lattice DDR SDRAM Controller in a Power PC Bus environment. Figure 3 shows the system with a Power PC Bus interface block.

The following are the features of the Power PC Bus interface block

• Supports PowerPC 601,603, 604 and processors supporting 60x bus.

• Parameterized data path widths of 32 or 64 bits.

• Supports both burst and single-beat data transfers (DDR Burst Length is 4).

• Programmable FIFO Depth

• Supports pipeline of two requests (write).

• Supports Address retry

• Supports separate address and data bus tenure.

Figure 3. Typical PowerPC system with Lattice DDR Controller

Power PC CPU

PowerPC I/F Block

BUS MASTER (DMA Controller)

DDR SDRAM

Controller Data/2 Address/2

Control

Power PC Bus Command

Address

Dataout

Datain

Chip Sel0 BusArbiter

DDR SDRAM Memory 0

4Mx8bit

DDR SDRAM Memory 1

4Mx8bit

DDR SDRAM Memory 2

4Mx8bit

DDR SDRAM Memory 3

4Mx8bit

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Lattice Semiconductor DDR SDRAM Controller

AHB Bus Interface Block

The AHB Bus Interface Block interfaces between AMBA Bus and Lattice DDR SDRAM Controller IP Core. This interface allows easy usage of the Lattice DDR SDRAM Controller on an ARM AHB bus environment. Figure 4 shows the system with an AHB Bus interface block.

The following are the features of the AHB Bus interface block

• Parameterized data path widths of 32, 64 and 128 bits on the AMBA Bus and the User Interface Bus.

• Supports INCR4/INCR8/INCR16/WRAP4/WRAP8/WRAP16/INCR Bursts (DDR side Burst Length is 4)

• Supports Byte/Half word/Word/Double Word transfers (with 64bit AHB-Bus)

• Programmable FIFO Depth

Figure 4. Typical AHB System with Lattice DDR Controller IP Cores

Parameter Description

The static parameters are set before the design is synthesized to a gate-level netlist. The dynamic parameters can also be set in this way, or they can be changed after the core is programmed onto a device by writing the values into the Configuration Registers. The user should consult the DDR SDRAM specifications before choosing the dynamic parameters, which are dependent on the DDR SDRAM device being used.

Table 2. Static DDR Core Parameters

Parameter Description Default Value

DSIZE Defines the bus width for the data in/out port. 64 bits

RSIZE Defines row address width 12 bits

CSIZE Defines column width 10 bits

BSIZE Defines bank width for internal chip banks. This version of the DDR SDRAM Controller is designed to work with memory chips containing 4 internal banks (sometimes called a quad memory array). The default value for BSIZE cannot be changed in this version of the core.

2 bits

ARM Processor

AMBA I/F Block

AHB Decoder

Lattice DDR SDRAM

Controller

Data/2 Address/2

Control

AHB Bus

Command

Address

Dataout

Datain

Chip Sel0 DMA Controller

(Master)

DDR SDRAM Memory 0

4Mx8bit

DDR SDRAM Memory 1

4Mx8bit

DDR SDRAM Memory 2

4Mx8bit

DDR SDRAM Memory 3

4Mx8bit

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Lattice Semiconductor DDR SDRAM Controller

7 Table 3. Dynamic DDR Core Parameters

RANK_SIZE Defines the number of external Banks (RANKS). NOTE: an external bank is a memory chip or group of chips (such as on a DIMM) that can be accessed using the same chip select signal.

RANK_SIZE = 0 (External Banks = 1) RANK_SIZE = 1 (External Banks = 2) RANK_SIZE = 2 (External Banks = 4) RANK_SIZE = 3 (External Banks = 8)

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Interface Type The following Bus Interface Blocks are available for connecting this controller to different bus standards: PCI Target Interface, PowerPC Interface, AMBA-AHB Interface, Generic Bus Interface.

Generic

ASIZE_BIM BIM Address Size is used in the PPC, PCI and AHB interfaces. ASIZE_BIM is the addrss width for these interfaces.

32

INIT Initialize DDR. Initializes the DDR SDRAM when bit is set. Set by command in register. 0 TRCD Delay RAS to CAS Delay. This is the delay from /RAS to /CAS in number of clock cycles and is

calculated using this formula INT(tRCD(MIN) /tCK)*.

2

TRRD Delay Row ACTIVE to Row ACTIVE Delay, this delay is in clock cycles and is calculated using this formula INT(tRRD(MIN)/tCK)*.

2

TRFC Delay AUTO REFRESH command period, this delay is in clock cycles and is calculated using this formula INT(tRFC(MIN) /tCK)*.

10

TRP Delay PRECHARGE command period. This is calculated by the formula INT(tRP(MIN)/tCK)*. 3 TMRD Delay LOAD MODE REGISTER command cycle time. This is calculated by the formula

INT(tMRD(MIN) /tCK)*.

2

TWR Delay Write recovery time. This is calculated by the formula INT(tWR(MIN) /tCK)*. 2 TRAS Delay ACTIVE to PRECHARGE delay. Defines the delay between ACTIVE and PRECHARGE

commands. (Maximum value: 15 clock cycles)

6

TWTR Delay WRITE to READ command delay. Defines internal write to read command delay. (Maxi- mum value: 7 clock cycles)

1

TRC Delay ACTIVE to ACTIVE /AUTOREFRESH command delay. Defines ACTIVE to ACTIVE /auto refresh command period delay. (Maximum value: 15 clock cycles)

8

CAS Latency CAS Latency is a delay in clock cycles between the registration of a READ command and the first bit of output data. Valid values are 1.5, 2.0, 2.5 and 3.0.

2 (2.0 clock cycles) Burst Length Burst Length, this number determines the maximum no of columns that can be accessed

for a given READ/WRITE and is equal to Burst Length programmed in the Mode register.

Valid values are 2, 4 and 8.

4

Burst Type Burst type. Defines if an interleaved or Sequential burst is required. 0 represents sequential and 1 represents interleaved burst type.

0

DSTRENGTH Drive strength. Defines the bit 1 in Extended mode register. 0 represents normal drive strength 1 represents a reduced drive strength (Required by some memory devices).

0

QFCFUNC Defines bit 2 of the extended mode register, which enables or disables the QFC Function (Required by some memory devices).

0

Table 2. Static DDR Core Parameters (Continued)

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Lattice Semiconductor DDR SDRAM Controller

Refresh Period Refresh period. Defines maximum time period between AUTOREFRESH commands. And is calculated as follows. INT(tREF/tCK)*.

2228

*Notes:

t_CK = Clock cycle time

tRCD(MIN) = ACTIVE to READ or WRITE delay

tRRD(MIN) = ACTIVE (bank A) to ACTIVE (bank B) command period t_RFC(MIN) = AUTOREFRESH command period (min.)

tRP(MIN) = PRECHARGE command period t_MRD(MIN) = LOAD_MR command cycle time tWR(MIN) = Write recovery time

tREF = AUTOREFRESH command interval (max.)

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Lattice Semiconductor DDR SDRAM Controller

9 Signal Descriptions

The following tables show the different interface signals for the DDR SDRAM controller. The DDR SDRAM Interface signals are the same for all core configurations.

Table 4. DDR SDRAM Interface Bus Signals

Table 5. Generic Bus Interface Signals

Signal Name Direction Active State Description

ddr_clk Output N/A DDR SDRAM Clock derived from the system clock

ddr_clk_n Output N/A Inverted DDR SDRAM Clock derived from the system clock.

ddr_cke Output High Clock enable

ddr_cs_n [(2^RANK_SIZE) - 1:0] Output NA Active low chip select, which selects and deselects the DDR SDRAM external bank.

ddr_we_n Output Low Write enable, defines the part of the command being entered ddr_cas_n Output Low Column Select, defines the part of the command being entered ddr_ras_n Output Low Row select, defines the part of the command being entered ddr_ad[RSIZE-1:0] Output N/A Row or column address lines depending whether the /RAS or

/CAS is active.

ddr_ba[BSIZE-1:0] Output N/A Bank address select.

ddr_dq[DSIZE/2-1:0] In/Out N/A Bi-directional data bus.

ddr_dqm[DSIZE/16-1:0] Output N/A Data mask signals used to mask the byte lanes for byte level write control.

ddr_dqs[DSIZE/16-1:0] In/Out N/A Data strobe signals used by memory to latch the write data.

clk Input N/A System clock.

reset_n Input Low System reset.

cmd[2:0] Input N/A Command for controller.

datain[DSIZE-1:0] Input N/A Data input. DSIZE is a programmable parameter of 32, 64 or 128.

addr[ASIZE-1:0] Input N/A Address for read/write. ASIZE is a programmable parameter set based on size of memory, which is derived by the following formula ASIZE = RANK_SIZE+ RSIZE + BSIZE+ CSIZE

dmsel[DSIZE/8-1:0] Input N/A Data Mask select

busy Output High Busy signal indicates the controller will not accept any more commands.

dataout[DSIZE-1:0] Output N/A Data out.

dataout_valid Output High This signal indicates when the dataout bus from the controller has valid data during a read.

datain_valid Output High This signal indicates when the user can start sending in data through “datain” bus during a write.

clk2x Input N/A This is the doubled clock signal coming from the on-chip PLL.

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Lattice Semiconductor DDR SDRAM Controller

Table 6. Power PC Bus Interface Signals

clk In NA System Clock.

reset_n In LOW System reset

ppc_aack_n Out LOW Address Acknowledge. When asserted this signal indicates that the address phase of the transaction is complete.

ppc_addr[0:ASIZE_BIM] In NA Address bus. Address received from a bus master after receiving a bus grant.

ppc_data_l[0:31] I/O NA Low Data Bus.

ppc_data_h[0:31] I/O NA High Data Bus.

ppc_artry_n In LOW Address retry. This signal indicates that the current cycle is aborted and the bus master will issue a request in a later time.

ppc_dbb_n In LOW Data Bus busy. The bus master that has received a data bus grant issues this signal, this signal indicates the length the data bus will be used for a memory access.

ppc_ta_n Out LOW Transfer Acknowledge. This signal indicates the data transfer on the PowerPC bus has been completed.

ppc_tbst_n In LOW Transfer burst. This signal indicates that a burst transfer is in progress.

ppc_tea_n Out LOW Transfer error acknowledge. This signal indicates that an error has occurred during a data transfer.

ppc_ts_n In LOW Transfer Start. This signal indicates that the master has begun a memory bus transaction and the address and transfer attributes are valid.

ppc_tsiz[0:2] In LOW Transfer Size.

ppc_tt[0:4] In LOW Transfer Type.

Table 7. PCI Local Bus Interface Signals

Signal Name Direction Active Description

clk In NA PCI System Clock.

reset_n In LOW Async PCI reset

l_data_in[DSIZE-1:0] Out NA Local address/burst length/data input. The address/burst length input is used in master transactions, and the data input is used for a master write or for a target read

l_data_out[DSIZE-1:0] In NA Local data output for a master read or a target write lt_address_out[ASIZE_BIM-

1:0]

In NA Local starting address output for target reads and writes

lt_ben_out[DSIZE/8-1:0] In NA Local target byte enables

lt_command_out[3:0] In NA Local command for target read and writes

lt_abortn Out LOW Local target abort request

lt_disconnectn Out LOW Local target disconnect or retry

l_interruptn Out LOW Local side interrupt request (multi-function device may need additional IRQ signals)

lt_rdyn Out LOW Local target ready to receive data (write) or send data (read) lt_r_nw In HIGH Read/Write# (read / not write) to signal whether the current

transaction is a read or write

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lt_hdata_xfern In LOW Memory or I/O high DWORD read or write data phase complete.

The address counter can be incremented in combination with the Lt_LowDataXferN

lt_ldata_xfern In LOW Memory or I/O low DWORD read or write data phase complete.

The address counter can be incremented in combination with the Lt_HighDataXferN.

exprom_hit In HIGH Expansion ROM register hit.

bar_hit[5:0] In NA Signal current address is within one of the base address register ranges and access is requested until cycle is done (multi- function device will need additional set of registers for each function)

lt_64bit_transn In LOW Signal to the local target that a 64-bit read or write transaction is underway

Table 8. AMBA Bus Interface Signals

clk In NA Bus clock. This clock times all bus transfers. All signal timings

are related to the rising edge of clk.

reset_n In LOW The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW signal.

HADDR[HASIZE:0] In NA The 32-bit system address bus.

HTRANS[1:0] In NA Transfer type.Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HWRITE In HIGH Transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer.

HSIZE[2:0] In NA Transfer size. Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit) or double word (64-bit) for 64bit AHB Bus.

HBURST[2:0] In NA Burst type. Indicates if the transfer forms part of a burst. Four, eight and sixteen beat bursts are supported and the burst may be either incrementing or wrapping.

HWDATA[HDSIZE-1:0] In HIGH Write data bus. The write data bus is used to transfer data from the master to the bus slaves during write operations.

HSELx In HIGH Slave select. This signal indicates that the current transfer is intended for this Slave. This signal is simply a combinatorial decode of the address bus.

HSELregx In HIGH This signal indicates the current transfer is meant for Internal Registers of the Bus Interface Block. This is valid only when HSELx is asserted.

HSELmemx In HIGH This signal indicates the current transfer is meant for DDR Memory Data. This is valid only when HSELx is asserted.

HREADY In HIGH Transfer done. When HIGH the HREADY signal indicates that a

transfer has finished on the bus.

HRDATA[HDSIZE-1:0] Out NA Read data bus. The read data bus is used to transfer data from bus slaves to the bus master during read operations.

HREADY_out Out HIGH Transfer done. When HIGH the HREADY_out signal indicates that a transfer has finished on the bus. This signal may be driven LOW to extend a transfer.

Table 7. PCI Local Bus Interface Signals (Continued)

Signal Name Direction Active Description

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Lattice Semiconductor DDR SDRAM Controller

Custom Core Configurations

For DDR SDRAM core configurations that are not available in the Evaluation Package, please contact your Lattice sales representative to request a custom configuration.

Related Information

For more information regarding core usage and design verification, refer to the

DDR SDRAM Controller IP Core User’s Guide,

available on the Lattice web site at www.latticesemi.com.

HRESP[1:0] Out NA Transfer response. The transfer response provides additional information on the status of a transfer. Four different responses are possible OKAY, ERROR, RETRY and SPLIT. RETRY &

SPLIT are not supported.

Table 8. AMBA Bus Interface Signals (Continued)

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Lattice Semiconductor DDR SDRAM Controller

13 Appendix for Series 4 ORCA

^®

FPGAs and FPSCs

Table 9. DDR Performance and Utilization

¹

Supplied Netlist Configurations

The Ordering Part Numbers (OPN) for this core is DDRCT-GEN-O4-N1, DDRCT-PPC-O4-N1, DDRCT-PCI-O4-N1 and DDRCT-AHB-O4-N1 depending on which bus interface is selected. Table 10 lists the Lattice-specific netlists that are available in the Evaluation Package, which can be downloaded from the Lattice web site at www.lattices- emi.com.

Table 10. Parameter Files

To load the preset parameters for this core, click on the “Load Parameters” button inside the IP Manager tool. Make sure that you are looking for a file inside of this core’s directory location. The Lattice Parameter Configuration files (.lpc) are located within the .lpc folder inside this directory.

Config # Parameter

I/O Utilization External PFU²

SysMEM

EBRs f_MAX (MHz)

DDRCT_GEN_O4_1_001.lpc See configuration table below. 141 255 NA 100

(200 MHz for clk2x)

DDRCT_PPC_04_1_001.lpc See configuration table below. 129 425 NA 100

(200 MHz for clk2x)

DDRCT_AHB_04_1_001.lpc See configuration table below. 242 565 NA 100

(200 MHz for clk2x) 1. Performance and utilization characteristics are generated using an OR4E02PBGAM680-DB in Lattice’s ispLEVER™ v.2.0 software. When

using this IP core in a different density, package, speed, or grade within in the ORCA 4 family, performance may vary slightly.

2. PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.

Name of Parameter File Data Size Rank Size BSIZE CSIZE

DDRCT_GEN_O4_1_001.lpc 32 0 2 10

DDRCT_PPC_O4_1_001.lpc 32 3 2 10

DDRCT_PCI_O4_1_001.lpc 32 3 2 10

DDRCT_AHB_O4_1_001.lpc 32 3 2 10

Note: All other parameters are set to their default value as shown in the preceding Parameter Table