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Northwest Logic Proprietary Copyright 2005 Northwest LogicDDR SDRAM Controller Core
Northwest Logic’s Double Data Rate (DDR) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates them to the command sequences required by DDR SDRAM devices. The core also performs all initialization and refresh functions.
The core uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to eight banks can be managed at one time. A command queuing interface is used enabling multiple, random address requests to be queued up, each with lengths as short as 2 DDR data cycles. This ar- chitecture provides optimal bandwidth utilization both for cases of short transfers to highly random address locations as well as cases of longer transfers to contiguous address space.
The core is provided with run-time programmable inputs for all timing parameters (tCL, tRC, tRCD, tRP, tMRD, tRRD, tRFC, tRAS) as well as memory configuration and refresh period set- tings. This ensures compatibility with all DDR SDRAM configu-
rations.
Three optional add-on modules are available:
• Error Correction Coding (ECC) Module - Provides single bit correction and double bit detection
• Read-Modify-Write Module - Enables partial word writes when using ECC
• Multi-Burst Module - Enables long burst length requests and handles address alignment for requests not aligned to the boundaries of the programmed burst length
Northwest Logic also provides customization and integration services to produce complete logic designs.
Product Deliverables:
• Core (Netlist or Source Code)
• Comprehensive Verification Suite (Source Code)
• Complete Documentation
• Expert Technical Support & Maintenance Updates
Block Diagram Product Highlights
• Command queuing and bank man- agement enable up to 100% mem- ory throughput
• Supports auto-precharge com- mands for optimum random ac- cess performance
• Achieves high clock rates with minimal routing constraints
• Supports all standard DDR SDRAM chips and DIMMs
• Run-time configurable timing pa- rameters and memory settings
• A variety of read capture options are supported
• Automatic generation of initializa- tion and refresh sequences
• ECC, RMW and Multi-Burst add-on modules available
• Supports self-refresh and power- down modes
• Source code available
• Customization and Integration services available
Product Overview
Bank Management Bank
Management Refresh Control
cke
ras_n
cas_n
we_n
Initialization Control
Address Generation
sa[13:0]
ba[1:0]
cs_n[7:0]
reset_n
Configuration Ports
raddr b_size[3:0]
r_req w_req busy d_req r_valid w_valid
sdram_ddr_lb
DDR SDRAM Device(s)
DDR Data Control datain[2n-1:0]
dataout[2n-1:0]
dm_in[2n/8-1:0]
dm[n/8-1:0]
dqs[n/8-1:0]
dq[n-1:0]
Control and Timing Queue
Control
Clock Module
clk_in
clk_90 clk
ext_clk ext_clk_n
