FPGA based a realization of BCH step-by-step decoding 周文政、胡大湘
E-mail: [email protected]
ABSTRACT
In general, an algebraic decoder is with high hardware complexity or a conventional step-by-step decoder is with long decoding delay, and both of them are not efficient for a cyclic code in terms of decoding complexity. In order to overcome this difficulty, a modified step-by-step decoding is proposed in this thesis, which increases the decoding speed of conventional step-by-step decoding.
Comparing to algebraic decoding, it reduces hardware complexity. Especially, as the error correcting capability is no more than 3, modified step-by-step decoding needs less decoding delay than algebraic decoding and conventional step-by-step decoding do. In this thesis, a design of remainder circuits, syndromes, the syndrome-matrix determinant is implemented to detect and correct errors. In verification of the designed implementation, the VHDL code of the proposed decoding algorithm for a BCH code are first
downloaded to a FPGA board, and data are transmitted from a computer via an RS232 interface. After a solution is ready on the FPGA board, and then transmitted back to the computer and check whether it is correct. In the results, the modified step-by-step algorithm holds better decoding speed and little more hardware complexity in comparison with the conventional step-by-step algorithm and can improve the drawbacks of the algebraic algorithm for BCH codes.
Keywords : cyclic code, BCH code, error control coding.
Table of Contents
第一章 緒論 1.1資料傳輸與儲存系統．．．．．．．．．．．．．．1 1.2 錯誤更正．．．．．．．．．．．．．．．．．
．2 1.3 研究動機．．．．．．．．．．．．．．．．．．3 1.4 論文組織．．．．．．．．．．．．．．．．．．4 第二章 線性區塊碼 2.1線性區塊碼．．．．．．．．．．．．．．．．．．5 2.1.1生成矩陣．．．．．．．．．．．．．．．．6 2.1.2 線性系統區塊碼．．．．．．．．．．．．．7 2.1.3 同位檢測矩陣．．．．．．．．．．．．．．9 2.2 徵狀與錯誤 檢測．．．．．．．．．．．．．．11 2.2.1 徵狀．．．．．．．．．．．．．．．．．．12 2.2.2 錯誤檢測．．．．．．
．．．．．．．．．．13 2.3 漢明碼．．．．．．．．．．．．．．．．．．．14 2.4 循環碼．．．．．．．．．．．．
．．．．．．．14 2.4.1 循環碼之編碼．．．．．．．．．．．．．．16 2.4.2 徵狀值計算．．．．．．．．．．．．．
．18 第三章 二位元BCH碼之編解碼 3.1 BCH碼簡介．．．．．．．．．．．．．．．．20 3.2 BCH碼解碼．．．．．．
．．．．．．．．．．22 3.2.1 徵狀值計算．．．．．．．．．．．．．．．22 3.2.2 錯誤樣本的定義．．．．．．．．．
．．．．23 3.2.3 錯誤位置多項式．．．．．．．．．．．．．25 3.3 BCH碼之解碼方式．．．．．．．．．．．．．26 3.3.1 Peterson-Gorenstein-Zierler Algorithm．．．．27 3.3.2 Berlekamp-Massey Algorithm．．．．．．．．32 3.3.3 Euclidean Algorithm．．．．．．．．．．．．37 3.4 Galois Field的硬體實現．．．．．．．．．．44 第四章 改良式步階解碼法 4.1 步階式解碼法．．．．．．．．．．．．．．．．51 4.2 改良式步階解碼法．．．．．．．．．．．．．．52 4.2.1 餘式電 路．．．．．．．．．．．．．．．．55 4.2.2 徵狀值計算．．．．．．．．．．．．．．．58 4.2.3 徵狀矩陣計算與比較
．．．．．．．．．．．60 4.2.4 步階式解碼法演算流程．．．．．．．．．．65 4.3 權重檢測．．．．．．．．．．．．
．．．．．．66 4.4 演算法比較．．．．．．．．．．．．．．．．．69 第五章 硬體電路之模擬結果與硬體驗證 5.1設計 流程．．．．．．．．．．．．．．．．．．78 5.2模擬測試．．．．．．．．．．．．．．．．．．80 5.3硬體驗證．．
．．．．．．．．．．．．．．．．86 第六章 結論與討論．．．．．．．．．．．．．．．．．．．91 參考文獻．．．
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