Implementation of Burst-Error-Decoding Algorithm of Reed-Solomon Codes Based on Embedded System
陳宗佑、胡大湘
E-mail: [email protected]
ABSTRACT
A Reed-Solomon codes was already verified to be a kind of powerful error control code. It has quite high detecting and correcting of the multiple errors. Correcting of burst errors and random errors simultaneously is its advantage, which has been implemented in many systems. Because an RS code structured in Galois field, when the number elements in Galois field increases, its decoding complexity grows. In this thesis, the implementation of a burst error decoding algorithm for Reed-Solomon codes is presented.
Trap-decoding based, detecting and correcting of burst errors in this algorithm are implemented in a FPGA embedded system. In the implementation process, both C and VHDL programming languages and a soft ware called System Generator are employed to realize this decoding algorithm, which is then downloaded into a FPGA embedded system. In the verification process, burst errors are corrected in this embedded system and then corrected data sent back to a computer via RS-232 transmission line. From the results of synthesized circuits, the decoding speed and hardware resources of VHDL implementation are faster and less than those of System Generator, respectively. As a code length increases, more hardware resources are utilized, and the corresponding decoding speed is slow down.
Keywords : Reed-Solomon codes ; burst error correcting algorithm ; embedded system ; error control code Table of Contents
封面內頁 簽名頁 授權書．．．．．．．．．．．．．．．．．．．．．iii 中文摘要．．．．．．．．．．．．．．．．
．．．．iv 英文摘要．．．．．．．．．．．．．．．．．．．．v 誌謝．．．．．．．．．．．．．．．．．．．．．
．vi 目錄．．．．．．．．．．．．．．．．．．．．．．vii 圖目錄．．．．．．．．．．．．．．．．．．．．．ix 表 目錄．．．．．．．．．．．．．．．．．．．．．xi 第一章 緒論 1.1 研究動機．．．．．．．．．．．．．．．．．
． 1 1.2 數位通訊系統．．．．．．．．．．．．．．．． 1 1.3 錯誤更正碼發展史．．．．．．．．．．．．．． 3 1.4 論文架構．．．．．．．．．．．．．．．．．． 5 第二章 里德索羅門碼之基本架構 2.1 里德索羅門碼簡介．．．．．
．．．．．．．．． 6 2.2 里德索羅門碼之編碼．．．．．．．．．．．．． 7 2.3 里德索羅門碼的解碼．．．．．．．．
．．．．．11 2.3.1 徵狀值計算．．．．．．．．．．．．．．． 11 2.3.2 尋找錯誤樣本．．．．．．．．．．．．．．
14 2.3.3 錯誤檢測與更正．．．．．．．．．．．．． 16 2.4 解碼範例．．．．．．．．．．．．．．．．．．24 第三章 捕捉解碼 3.1 捕捉解碼簡介．．．．．．．．．．．．．．．．32 3.2 捕捉解碼之解碼過程．．．．．．．．．．．．
．32 3.3 硬體實現 Galois Field 計算．．．．．．．．．39 第四章 硬體模擬與驗證 4.1 設計流程．．．．．．．．．．．
．．．．．．．46 4.2 模擬過程．．．．．．．．．．．．．．．．．．48 4.3 電路合成與硬體驗證．．．．．．．．．
．．．．53 第五章 結論與改進．．．．．．．．．．．．．．． 66 參考文獻．．．．．．．．．．．．．．．．．．．
．68
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