Pixel Circuit with External Current Source to Achieve Fast
Compensation for Variations of LTPS TFTs for AMOLED Displays
Chih-Cheng Hsu, Chun-Ming Lu, Po-Chun Lai, Po-Syun Chen, and Chih-Lung Lin*
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Pixel Circuit Schematic Abstract
This work proposes a new pixel circuit of low- temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) for active-matrix organic light-emitting diode (AMOLED). The proposed pixel circuit is used to compensate for the threshold voltage variations of driving TFT, and the current-resistance voltage drop in power line (I-R drop).
Moreover, the proposed pixel circuit can avoid flicker and extend compensation time. The simulation results demonstrate that the relative current error rates are less than 5% and 1% as the variations of threshold voltage and I-R drop are ±0.5 V and -0.5 V, respectively.
(a) (b)
Fig. 1. (a) schematic diagram of pixel circuit and (b) timing diagram.
Pixel Circuit Operation
Simulated Results
Fig. 2. (a) Simulated transient waveforms of VA and VC of proposed pixel array. (b) OLED currents versus data voltages of proposed pixel circuit.
Conclusion
This work proposes a new LTPS-TFTs pixel circuit that combines parallel addressing scheme, current- programmed and voltage-programmed to compensate for VTH variations of TFTs, and I-R drops of power line.
The simulation results demonstrate the relative current error rates are below 5% when VTH variations are ±0.5 V and below 1% when I-R drop is -0.5 V, which verify that the proposed pixel circuit has high immunity to VTH variations of TFTs, and I-R drops. The proposed pixel circuit achieves fast compensation and generates high uniformity OLED currents. Therefore, the proposed pixel circuit is suitable for AMOLED display.
TFT aspect ratio W/L
(W/L)T1, T2,T3,T4 (μm) 3/3 (W/L)T5 (μm) 4/15 Capacitance
C1 (pF) 0.3 C2 (pF) 0.2
Voltage
SCAN1 (V) -7 ~ 7 VDD (V) 4.5
SCAN2 (V) -7 ~ 7 VSS (V) -4.5
VREF -3 V Vdata (V) 0.5~3.5
IREF 3 μA
Compensation Stage Data Input Stage
Emission Stage
2 2
1 1
2 5
)]
( [(
) (
REF DATA
REF
TH_T SG
OLED
V C V
C C K
K I
V V
K I
+ −
−
=
−
= K
V I V
VA = DD − TH_T5 − REF
V SC N
VSS SC N
SCAN1
(1)
VDATA
(3) (2)
SCAN2
VDATA
) V
C (V C
C
K V I
V V
REF DATA
REF TH_T
DD A
+ − +
−
−
=
2 1
1
5
(a) (b)
(a) (b)
Fig. 3. (a) Relative current error rates with ±0.5 V variations of TFT VTH for proposed pixel circuit. (b) Relative current error rates with 0.5V VDD drop for proposed pixel circuit.
