Due-date performance improvement using TOC’s aggregated
time buffer method at a wafer fabrication factory
Tsai-Chi Kuo
a, Sheng-Hung Chang
a,*, Shang-Nan Huang
baDepartment of Industrial Engineering and Management, Minghsin University of Science and Technology, 1 Hsin-Hsing Road, Hsin-Feng,
Hsin-Chu County 304, Taiwan, ROC
b
Department of Industrial Engineering and Management, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan, ROC
Abstract
Due-date performance is one of the most important production indexes for success utilized by wafer fabrication factories. Tradition-ally, the industry sets a specific due-date tightness level and a dispatching rule based on the total processing time, the production capacity, pre-defined order release criteria and historical data, to ensure deliveries are made on-time. However, such policies typically do not solve the due-date performance problem at wafer fabrication factories, since the processes are highly complex. This investigation explores the due-date performance problem using the concept of the aggregated time buffer in critical chain project management (CCPM), which was developed by Dr. Goldratt. A simulation model was constructed and the performance of the proposed method is evaluated based on four dispatching rules at a wafer fabrication factory. The findings reveal that applying aggregated time buffer control system improved the overall due-date control, in terms of on-time delivery rate, average tardiness, and variances in average tardiness and lateness. Ó 2008 Elsevier Ltd. All rights reserved.
Keywords: Aggregated time buffer; Due-date control; On-time delivery; Wafer fabrication; Theory of constraints
1. Introduction
The due-date control performance, finishing the prod-ucts without tardiness, is one of the most important production indexes used by wafer fabrication factories. Due-date performance is controlled by determining the high work in process (WIP) level, a long manufacturing lead time, because a high WIP level on the shop-floor increases the manufacturing lead time. Also, unsuitable WIP controlling levels and machine failures lead to a high variation in lead time. Setting an exact order due-date and delivering the goods in a timely manner to the customer
improves customer service (Chung, Yang, & Cheng,
1997). However, an accurate due-date cannot be assigned
unless the manufacturing lead time can be accurately estimated.
Traditionally, a firm sets a particular due-date tightness level and a dispatching rule according the total processing time of a plan or historical data. However, most evaluations of such manufacturing management policies are too conser-vative to determine a due-date tardiness level. Many research projects and programs have been developed to overcome these inherent limitations, and to help solve
pro-duction planning and scheduling problems (Ahmadi,
Ahmadi, Dasu, & Tang, 1992; Fowler, Phillips, & Hogg,
1992), integrated shop-floor scheduling systems based on
a variety of methods (Fargher, Kilgore, Kline, & Smith, 1994; Ovacik & Uzsoy, 1994), and using combinations of dispatching rules and order release policies (Chang, Pai, Yuan, Wang, & Li, 2003; Lu & Kumar, 1994; Wein, 1988). However, few such projects and programs have dem-onstrated the effective and efficient solving of the due-date control problems in wafer fabrication factories. Several problems are included as follows. First, most due-date con-trol rules use the decentralized time buffer method to spread to each manufacturing process to control the flow-time and 0957-4174/$ - see front matterÓ 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.eswa.2007.12.038
*
Corresponding author. Tel.: +886 3 559 3142x3224; fax: +886 3 559 5142.
E-mail address:shchang@must.edu.tw(S.-H. Chang).
www.elsevier.com/locate/eswa Expert Systems with Applications 36 (2009) 1783–1792
Expert Systems with Applications
the due-date. Second, only a few have examined those rules, with reference to shop status information. Third, the shop status in a job shop arrangement is extremely dynamic and the due-date tightness in the regulations is very difficult to set. Finally, the most important and difficult to control due-date in a wafer fabrication system is associated with a complex production process that includes: (1) many process steps; (2) machines with very different processing capacities; (3) unpredictable machine downtime and process yields, which combine to make the task of managing material flow through the facilities particularly challenging; (4) re-entrance of the product flows, as numerous products must be returned to the stations several times before completion; and (5) the visiting of bottlenecks several times before final completion. Consequently, the throughput of the system is highly unstable, the lead time is long, and the WIP level is excessive (Chung et al., 1997). Therefore, in solving due-date performance problems, it is important to simulta-neously calculate the due-date tightness level and determine the appropriate dispatching rules.
Recently, a number of researchers have implemented shop-floor control procedures to efficiently control the due-date based on the Theory of Constraints (TOC), which was developed byGoldratt (1990). The TOC states, ‘‘Any system must have a constraint that limits its output.” Hence, the system’s constraint is likely to be the weakest link in a chain. Regardless of how other links in the chain are improved, the chain itself does not become stronger unless the strength of the weakest link is improved (Leach, 2000). Therefore,Goldratt (1997)proposed that when pro-ject managers estimate due-date control, three uncertainties in project planning and scheduling must be considered. These are task time, path time and resource uncertainties. Most project planners add a safety allowance or time buffer in the total estimated time required to reduce the
uncertain-ties of a task (Goldratt, 1997). The question is how much safety allowance or time buffer should be added in the activity time? Fortunately, in CCPM, the above problems can be solved by applying aggregated time buffer (ATB) theory, which brings together all time buffers in a single time buffer (Steyn, 2000; Yeo & Ning, 2002).
In this study, the due-date performance problem of wafer fabrication factories is converted into a project prob-lem by the TOC aggregated time buffer method, because the concept of a project is similar to the concept of a cus-tomer order. A project involves several activities/tasks and an order includes several processes. Therefore, the due-date control component of an customer order problem is converted into a project dilemma. The objective of this research is to develop and discover a combinational dis-patch rule of job shop flow scheduling to improve the due-date performance by using the TOC’s time buffer approach. In addition, the safety allowance is aggregated and calculated using an aggregated time buffer based on the due-date estimation according to the concept of TOC. By constructing and monitoring the aggregated time buffer with different dispatching rules, it is expected that the aggregated time buffer control model could reduce the mean tardiness and tardiness jobs. A simulation model is also constructed and the performance of the presented aggregated time buffer method is examined based on sev-eral dispatching rules for a wafer fabrication factory.
The rest of the article is organized as follows. Section 2
reviews the literature on the TOC and due-date assignment
problems. Section 3 describes the aggregated time buffer
control model and explains how to determine flow time
controlling parameters? Section 4 simulates and applies
the aggregated time buffer control model using actual data. Finally, conclusions are drawn and avenues for further research are provided.
List of notations
i ith lot
j jth workstation
k kth monitor workstation
e the last work station to proceed lot i
ai the releasing date of lot i
ABi aggregated time buffer when lot i enter the
system
ABik aggregated time buffer for the lot i in the kth
monitor workstation
di the due-date of the lot i
d0i time at which probability that the ith lot has
been completed is 50%
etik expected time of completion of lot i on monitor
workstation k b
Fi an unbiased estimate of the flow-time of lot i
K1, K2 the parameters of the state of the system based
on the historical data
LT0i lead time of lot i, according to JIQ method
ni the throughput of the bottleneck workstation
per day
pi the processing time of ith lot
Pij processing time for the lot i in workstation j
Qi the number of jobs in the work center queues on
the job’s routing when lot i arrives
SBik remaining of the aggregated time buffer when lot
i arrives at monitor workstation k
tik time at which lot i arrives at monitor
worksta-tion k
Wi the waiting time to be processed of the lot i,
g an unbiased evaluated constant obtained from
historical data in the factory
h the safety allowance
^
2. Literature review
Since the duration of each project activity is
unpredict-able,Goldratt (1997)developed a CCPM method to solve
problems that are inherent in the traditional project plan-ning and scheduling methods. The critical chain method, applied in the TOC, offers an improved process to manage the risk and uncertainty associated with a project and
enhances the project time management (Yeo & Ning,
2002). This method solves the problem of project planning and scheduling and also overcomes the risk and uncer-tainty associated with the on-time completion of the projects.
2.1. Project activity performance
Most studies in this field use a beta (b) distribution to describe and estimate project activity time (Fig. 1), because the b distribution effectively describes the inherent variabil-ity in time estimates (Stevenson, 1999), and has a left skewed probability distribution and a long tail to the right,
above the average activity time. Time wastage is associated with student syndrome, Parkinson’s law, multi-tasking, and merging events (Yeo & Ning, 2002).
2.2. Buffer control
A project planner must add a time buffer to enable pro-ject activities to be controlled effectively.Tu and Li (1998)
defined the time buffer as ‘‘the processing time plus the setup time plus an estimated aggregated protective time required ensuring that the released product will arrive at the constrained machine when needed”. In CCPM, two buffers are defined – feeding and project buffers. Feeding buffers (FBs) are incorporated whenever a non-critical chain activity joins the critical chain, both to protect the critical chain from disruptions in the activities that feed it, and to allow critical chain activities to start early to ensure that the project proceeds effectively. The project buffer (PB) protects the project due-date promised to the customer from variations in the critical chain tasks. Dr. Goldratt further suggested that a buffer associated with the critical chain tasks should be shifted to the end of the critical chain in the form of a project buffer, as shown in
Fig. 2.
For a 90% level of confidence estimation, all original time buffer estimates should be by halved by 50% to yield the average time estimates (tm) in the TOC. The time buffer
is aggregated to against uncertainties in estimates and the
activity performance and due-date. Fig. 3 displays the
aggregated time buffer, B, which equals the sum of bi,
where i = 1, 2, . . ., n
B¼X
n
i¼1
bi; bi is the buffer between processes Fig. 1. b distribution for probabilistic time estimates.
Fig. 2. Buffers in CCPM.
As described above, the calculated buffer increases line-arly with the length of the critical chain with which it is associated.Fig. 4displays the size of the buffer as follows: A: Aggressive but possible time estimate (ABP), within which probability of completing the project is 50% if it is pushed aggressively.
C: High-probability time estimate (HP), within which probability of completing the project is 90% if the pro-ject is performed conservatively.
B: It equals to C minus A. Generally, it is defined as the buffer size.
The time buffer size of each activity is assigned by the manager, according to his or her experience and business policies.Figs. 5a and b display the different ways in which managers establish project buffers to ensure on-time deliv-ery. Dr. Goldratt stated that, regardless of the project, the
ratio B/C, where B¼ C A, should be approximately 50%.
2.3. Issues associated with setting due-dates
Due-dates could be external or internal (Chen & Gupta, 1989). The external due-dates are set by the sales depart-ment, usually neglecting job shop conditions. They tend to be later than actual delivery dates. Internal due-dates consider shop conditions, and are set by a scheduler. They are closer to the actual delivery dates. Approaches for set-ting due-dates fall into four categories.
1. Direct procedures. This approach sets a due-date based on data such as job characteristics, shop conditions and dynamic shop conditions. Although, this approach is convenient and easily implemented, some parameters must be pre-specified (Smith & Seidman, 1983). 2. Simulation method. The advantage of this approach is
that the effects of the polices can be easily evaluated without actual execution. Numerous researchers have used simulation (Vig & Dooley, 1991; Weeks, 1979).
Kaplan and Urnal (1993) determined flow-time data from the results of a simulation. They evaluated the rela-tionships among several variables and flow-time by per-forming a correlation analysis.
3. Analytical method. This approach is based on queuing theory, and estimates the mean and standard deviation flow-times of orders.
4. Statistical analysis. This approach uses regression or
relational analysis to determine the relationships
between the flow-times of orders and other variables (Kaplan & Urnal, 1993; Smith, Minor, & Wen, 1995).
3. Aggregated time buffer control model
The aggregated time buffer control model concerns the macro and dynamic factors to meet the due-date. The aggregated time buffer control model is described below. It involves: (1) calculating the total aggregated time buffer; (2) selecting the monitoring point; and (3) constructing the model.
3.1. Calculating the total aggregated time buffer
For any lot i, the total aggregated time buffer is defined as in Eq.(1).Fig. 6displays the aggregated time buffer
ABi¼ di d0i: ð1Þ
Fig. 4. Uncertainty in activity time.
Fig. 5. (a,b) The difference lengths for A, B, and C.
where di: due-date of the lot i; d0i: it is a 50% opportunity to
finish the lot i.
The due-date is set herein, using both simulation and queuing theory to estimate the flow-time and identify its control parameters (Enns, 1993; Kaplan & Urnal, 1993). The analytical method is used to the estimate time, di¼
aiþ bFiþ h^re, where ai is the releasing date of lot i; bFi is
an unbiased estimate of the flow-time of lot i; h is the safety allowance, and ^reis the standard deviation of the estimated
error. The allowance includes the processing time, the wait-ing time, and other uncertainties associated with tardiness. The setting of the due-date is further simplified as di= a-i+ pi g, where piis an unbiased estimate of the processing
time for lot i, and g is an unbiased evaluated constant obtained from historical data in the factory. Generally, the ratio of real production cycle time to theoretical produc-tion cycle time is between 2.5 and 10 (Lu & Kumar, 1994). The real number is dependent on the actual situation of pro-duction loading. In this research, the g is determined by pre-simulation according to the achievement of the due-date.
The next step is to determine the time point (d0i) at which the lot i has a 50% of being completed. It is calculated as d0i¼ aiþ LT0i. The estimate of LT
0
i is based on the jobs in
queue due-date rule (JIQ), where JIQ assign flow-times allowance on the basis of the total number of jobs in the sys-tem waiting to be processed on machines encountered on the job’s path (Tsai, Chang, & Li, 1997). The reason for using the JIQ method is that it can reflect the manufacturing pro-cesses of a wafer fabrication factory. In the JIQ method, each job receives a random due-date, usually following a probability distribution (Gordon, Proth, & Chu, 2002). By using this method, it can consider the different total process-ing times for various product types and the WIP levels for the lead time effects. As generally known, the release func-tion controls the level of WIP inventory, and the level of WIP determines the flow-time of the orders. Also, the parameters used in this method can consider the production
queue. For details of the JIQ method, refer to Chang’s
(1996), Ramasesh (1990), Vig and Dooley (1991), Gee and Smith (1993)papers
LT0i¼ K1Piþ K2Qi ð2Þ
where Pi: the total processing of the lot i; Qi: the number of
jobs in the work center queues on the job’s routing when lot i arrives; K1, K2: the parameters of the state of the
sys-tem based on the historical data.
JIQ considers the shop congestion status. Their flow-time allowance estimate is static. This method accounts for the effects of lead times on the products total processing times and the total amount of WIP. Also, the selection of K1and K2is based on the actual situation on the loading
in a production line.
3.2. Selecting the monitoring point
Aggregated time buffer control can be regarded as inven-tory control. For some orders, the time buffer is used up
quickly, while for others, it is not. Therefore, the buffer size must be determined and the rules set to protect and monitor the use of a time buffer. As lot i continues to be processed, the uncertainty that lot i will be finished increases, because
the aggregated time buffer decreases. Fig. 7 displays the
dynamic aggregated time buffer as the job shop process continues.
Based on the above, the best method is to set each con-trol point in each workstation to concon-trol the use of the time buffer. However, this method overloads the entire control system. Therefore, in this work, the control point will be a bottleneck workstation that generally has a large WIP. This idea is based on the TOC: a workstation with a high utilization will have a long queue, and therefore, consti-tutes a high-probability of using the time buffer.
3.3. Constructing the model
Three aggregated time buffers are considered, according
to the TOC. Goldratt (1997) recommended a simple
‘‘green–yellow–red” warning system. If overruns on activi-ties that lead to a buffer cause less than one third of the buf-fer to be used, then no action is taken; if between 1/3 and 2/ 3 of the buffer is used, a warning is issued; if more than 2/3 of the buffer is used, a serious corrective action must be taken. This concept is also adopted to apply to buffer con-trol in this study. To concon-trol the buffer effectively, first, if it is within the first third of the aggregated time buffer, then no action is taken. Second, if it enters the middle third of the aggregated time buffer, then the problem is addressed and a plan of action implemented. Third, if it penetrates the final third of the buffer, then the buffer manager must increase the priority of the order to ensure that it is com-pleted on time. The buffer manager must set emergency policies for the order. Also, the status of aggregated time buffer must be updated as required. The algorithms for determining the total aggregated time buffer are summa-rized as follows (Fig. 8):
Step 1. When lot i arrives at the bottleneck workstations, the monitoring process begins. IF the arrival date of lot i is before the due-date, then go to step 2; otherwise, go to step 8.
Step 2. Determine the total aggregated time buffer from the activity time. As the order is processed, the time buffer linearly declines, as shown in Fig. 7. Therefore, the aggregated time buffer for lot i at the kth monitor workstation is as follows:
ABik¼ ABi P j¼e j¼k Pij P j¼e j¼1 Pij ð3Þ
where i: ith lot; j: jth workstation; k: the kth mon-itor workstation; e: the last work station to pro-ceed lot i; Pij: processing time for the lot i in
workstation j; ABi: aggregated time buffer when
lot i enter the system; ABik: aggregated time buffer
for the lot i in the kth monitor workstation. Step 3. Calculate the remaining of the aggregated time
buffer
The aggregated time buffer is affected by the lead time, which is determined by the order and manu-facturing processes. Determining the lead time while considering all the job status information simultaneously is important.
(1) Calculate the time at which the probability that the ith lot has been completed is 50%
d0i¼ aiþ LT0i ð4Þ
where d0i: time at which probability that the ith lot has been completed is 50%; ai: the releasing date of
the lot i; LT0i: lead time of lot i, according to JIQ method.
(2) Determine the expected time for completing the
order according to the due-date d0i
etik ¼ aiþ d0i ai P j¼e j¼k Pij P j¼e j¼1 Pij ð5Þ
where etik: expected time of completion of lot i on
monitor workstation k.
(3) Determine the remaining of the aggregated time
buffer
SBik¼ ABik ðtik etikÞ ð6Þ
where tik: time at which lot i arrives at monitor
workstation k; SBik: remaining of the aggregated
time buffer when lot i arrives at monitor worksta-tion k.
Step 4. Examine the feedback on the consumption of the aggregated time buffer. The buffer control rules are as follows:
(1) If the first third of the aggregated time buffer
ðABik SBik613ABikÞ is penetrated, go to step 5;
take no action.
(2) If the middle third of the buffer 1
3ABik6
ABik SBik623ABikÞ is penetrated, go to step 6;
address the problem and plan for action.
(3) If the final third of the buffer ABð ik SBik P23ABikÞ
is penetrated, go to step 7; initiate action.
Step 5. Lot i can be finished before the due-date; set the manufacturing priority to ‘‘normal lot”, then go to step 8.
Step 6. Henceforth, the lot must be closely monitored because it could be late. If ABik SBikP23ABik,
then go to step 7, otherwise, go to step 8.
Step 7: The usage of the time buffer shows that the order will not be completed on time. Therefore, the pri-ority is set to ‘‘hot lot”, which is the highest priority.
Step 8: Wait for the subsequent process. 3.4. Illustration
The above procedure is illustrated using the following example. Lot 1 is assumed to arrive on Day 0. It is pro-cessed at three workstations, w1, w2 and w3, at which the
processing times are 2 (p11), 6 (p12) and 1 (p13) day,
respec-tively. Also, the w2 is the bottleneck workstation of the
three machines based on utilization. Estimated lead times Fig. 8. Aggregated time buffer control model.
for the workstations, based on the queue, are three, ten and
two days. Parameters K1and K2are fixed and dependent
on the actual loading of a production line. In this example, they are assumed both to be one.
Therefore, d0¼ a þ ðLT01þ LT 0 2þ LT 0 3Þ ¼ 0 þ ½ð2 þ 3Þ þ ð6 þ 10Þ þ ð1 þ 2Þ ¼ 24 day
Based on historical data from the factory on the completion of lot 1, ⁄ = 3.8 is assumed. Therefore, d¼P3i¼1p1i¼ ð2 þ 6 þ 1Þ 3:8 ¼ 34:2. The aggregated time buffer can be determined to be AB1= d d0= 34.2 24 = 10.2. The
manager can monitor the aggregated time buffer at the w2
and she/he can make a decision in real time, as presented inFig. 9.
4. Simulation experiment
In this study, the dispatching rules and the aggregated time buffer rules were developed and applied to simulate a process in a wafer fabrication factory using the simula-tion software, Simple++. During the simulasimula-tion, four dis-patching rules were grouped and evaluated by adding an aggregated time buffer based on the due-date control, as presented in Fig. 10. The first group comprises first-in-first-out (FIFO) and smallest remaining processing time (SRPT) rules, which are not related to the due-date in the consideration of the priorities of the process sequences. In contrast, the other two dispatching rules, early due-date
(EDD) and slack per operation (SLACK/OPN) are related to the due-date. For all of those dispatching rules, two experiments – I (without aggregated time buffer control) and II (with aggregated time buffer control) – are simulated and assessed. All data were collected after the simulation had reached a steady state.
4.1. Simulation input data and assumptions
Four different equal product-mixed products in a wafer fab factory (A, B, C, and D) are selected and simulated. The manufacture of each product involves at most 270 manufacturing processes on 24 workstations. In these workstations, two types of machines are used – one for batch processing (wi, where i = 1–4) and the other for serial
processing (wi, where i = 5, 6, . . ., 24). The machine down
time, MTBF (mean time between failure) and MTTR (mean time to repair) are simulated as being exponentially distributed. Table 1summarizes all data.
Fig. 9. Calculation of ATB.
Fig. 10. Experiments on buffer control with dispatching rules.
Table 1
Related data for each workstation Work station No. of machine MTBF (h) MTTR (h) MTBPM (h) MTPM (h) Process type w1 4 42.18 2.22 716 4 B w2 4 101.11 10.00 600 1 B w3 4 113.25 5.21 180 7 B w4 2 103.74 12.56 150 6 B w5 2 100.55 6.99 336 12 S w6 2 113.25 5.21 96 8 S w7 2 16.13 4.38 166 2 S w8 2 13.22 3.43 716 4 S w9 2 10.59 3.74 150 6 S w10 2 47.53 12.71 163 5 S w11 2 52.67 19.78 600 6 S w12 2 72.57 9.43 166 2 S w13 8 22.37 1.15 480 24 S w14 6 21.76 4.81 60 3 S w15 2 387.20 12.80 480 24 S w16 4 – – – – S w17 2 119.20 1.57 130 2 S w18 2 – – – – S w19 4 46.38 17.42 120 6 S w20 2 36.58 9.49 168 8 S w21 4 36.58 9.49 163 5 S w22 4 118.92 1.08 162 4 S w23 4 – – – – S w24 4 55.18 12.86 96 8 S
Remarks: B, batch process, each time can process 6 lots; S, single process, each time can only process 1 lot.
The other input data used in this simulated model are as follows:
1. The machine setup time is included in the machine pro-cessing time.
2. The lot might visit the workstation i few times.
3. The order arrival distribution is assumed to be exponen-tially distributed.
4. The order release dates are assumed to be exponentially distributed.
5. Only w7and w14(both utilization level are greater than
90%) are used as the bottleneck workstations, to sim-plify the monitor system.
6. All due-dates are simulated and collected when the sys-tem reaches a steady state, based on historical informa-tion. During the simulation, the on-time delivery rates obtained using the four dispatching rules without mon-itoring the aggregated time buffer, are 76%, 76%, 88% and 90% (Table 4), respectively, where ⁄ = 3.8.
di¼ aiþ pi 3:8
where di: the due-date of ith lot; ai: the releasing date of
ith lot; pi: the processing time of ith lot.
4.2. Due-date estimation based on JIQ method
As indicated above, the lead time is determined to be 50% using a regression method (Kaplan & Urnal, 1993). Different dispatching rules yield different sequences, so the lead times under various dispatching rules are simu-lated using a regression method when the system runs for 100 days and enters a steady state (1700 lots/day), as
pre-sented in Table 2. (The number in the Table 2 is based
on historical data and the simulation.) 4.3. Determining the control point
As stated in Section 3.2, only bottleneck workstations need to be monitored, so the utility of each workstation is calculated from the CCPM. The simulation results indi-cate that w7(deposition) and w14(photolithography) have
the highest utility, 99% and 94%. Also, the WIP at these two workstations is higher than in the others. In this work, only w7 and w14 (both utilization level are greater than
90%) are used as the bottleneck workstations and applied in the aggregated time buffer system, to simplify the mon-itor system.Table 3presents the utilization of all worksta-tions. However, a production manager should monitor workstations with utilization levels of P80% to prevent bottleneck shifting in the fabrication of wafers.
4.4. Results and analysis
The result of the experiments indicate that the dispatch-ing rule with an aggregated time buffer control, in terms of mean value and standard deviation, average lateness (AL), average tardiness (AT), variance in the average tardiness (VAT), cycle time (CT) and on-time delivery rate (OTD%) (Tables 4 and 5). The on-time delivery rates obtained using the aggregated time buffer (76%, 76%, 88%, and 90%) exceed Table 2
Due-date estimation for different dispatching rules
Dispatching rules Due-date estimation
FIFO d0i¼ aiþ ð668768Þ þ 9351:61qiþ 3:20pi
SRPT d0i¼ aiþ ð2645955Þ þ 5647:23qiþ 6:05pi
EDD d0i¼ aiþ ð1999098Þ þ 13870:38qiþ 3:98pi
SLACK d0i¼ aiþ ð1639576Þ þ 15596:58qiþ 3:29pi
d0i: time at which probability that the ith lot has been completed is 50%. pi: the total processing of the lot i.
qi: the number of jobs in the work center queues on the job’s routing when
lot i arrives.
Table 3
Utilization of the workstations
w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 U% 11 9 16 15 80 52 94 58 86 69 58 62 WIP 13.24 11.89 13.59 11.77 3.74 1.4 12.44 1.95 5.16 3.45 3.79 3.05 w13 w14 w15 w16 w17 w18 w19 w20 w21 w22 w23 w24 U% 22 99 22 3 8 3 36 84 86 60 87 47 WIP 0.32 19.58 0.51 0.04 0.11 0.04 1.83 13.10 7.18 1.60 3.20 2.73 Table 4
The mean value of the cycle time in experimental I and II (unit: h)
Rule AL AT VAT CT OTD%
Experiment I II I II I II I II I II
FIFO 20.95 11.68 64.25 73.27 84.99 79.29 781.46 769.81 0.76 0.81
SRPT 22.28 17.89 67.96 72.50 105.57 100.12 774.52 770.94 0.76 0.79
EDD 4.65 4.02 75.07 79.66 54.03 56.15 769.22 764.43 0.88 0.90
SLACK 3.40 2.29 75.30 82.91 51.26 56.79 769.40 761.01 0.90 0.93
those obtained without an aggregated time buffer (81%, 79%, 90%, and 93%), indicating that the due-date is set effec-tively when the aggregated time buffer control is used.
The experimental results were further studied by perform-ing a t test at confidence levels of 99% and 90%. Table 6
shows that FIFO and SRPT dispatching rules significantly improve the control of order due-dates when the aggregated time buffer control system is integrated, at a confidence level of 99%, because these two dispatching rules do not consider the due-date in determining the production sequences. Therefore, implementing the aggregated time buffer control system greatly improves the order due-date control. 5. Conclusions
The data herein indicate that due-date control was improved, in terms of on-time delivery rate, average tardi-ness, variance of average tardiness and average lateness. The aggregated time buffer control system based on TOC theory is used to ensure that the order due-date is met. In this study, various dispatching rules with aggregated time buffer control in a wafer fabrication factory are simulated and analyzed. The results are summarized as follows: 1. The aggregated time buffer control system yields a
sig-nificant improvement in meeting the due-date for vari-ous dispatching rules.
2. Experiment II yielded the results that were better than those in experiment I, regardless of the dispatching method used. Because the aggregated time buffer improves the accuracy of due-date performance.
3. In terms of average tardiness index, the aggregated time buffer control system is better when the due-date unre-lated dispatching rules, FIFO and SRPT, are applied, indicating that the aggregated time buffer control system improves the accuracy of the due-date performance. In
contrast, the aggregated time buffer control does not sig-nificantly affect the accuracy of the due-date when the dispatching rules related to the due-date are used. 4. The aggregated time buffer control system yields better
average lateness than obtained without such a buffer control system reducing the cost.
This study demonstrates that the aggregated time buffer control system with dispatching rules outperforms a system without aggregated time buffer control.
Acknowledgement
The authors would like to thank the National Science Council of Taiwan, Republic of China, for financially sup-porting this research under Contract No. NSC 89-2213-E-159-009.
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Table 5
The standard deviation of the cycle time in experimental I and II (unit: h)
Rule AL AT VAT CT OTD%
Experiment I II I II I II I II I II
FIFO 8.99 7.23 35.83 28.36 9.16 7.92 35.29 28.47 0.1183 0.0997
SRPT 11.68 10.78 31.97 27.25 13.12 21.30 31.97 28.65 0.1008 0.0917
EDD 4.40 4.27 32.91 29.25 8.62 15.35 32.96 29.33 0.1088 0.0984
SLACK 3.15 2.54 22.83 22.92 8.79 20.57 22.15 21.38 0.0866 0.0592
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Table 6
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**: Significant with aggregated time buffer control at a = 0.01 *: Significant with aggregated time buffer control at a = 0.1.
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