N-type Schottky barrier source/drain MOSFET using ytterbium silicide

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IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 8, AUGUST 2004 565

N-Type Schottky Barrier Source/Drain MOSFET

Using Ytterbium Silicide

Shiyang Zhu, Member, IEEE, Jingde Chen, M.-F. Li, Senior Member, IEEE, S. J. Lee, Member, IEEE, Jagar Singh,

C. X. Zhu, Member, IEEE, Anyan Du, C. H. Tung, Senior Member, IEEE, Albert Chin, Senior Member, IEEE,

and D. L. Kwong, Senior Member, IEEE

Abstract—Ytterbium silicide, for the first time, was used to form

the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, wich is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO₂gate dielectric, and HaN/TaN metal gate. The YbSi₂ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high _on _oratio of 107and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi₂ /Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dys-prosium) silicided Schottky junctions.

Index Terms—MOSFET, rare earth (RE) metal, Schottky,

sili-cide.

I. INTRODUCTION

T

HE SCHOTTKY barrier source/drain transistor (SSDT) architecture [1] has been proposed to overcome the series resistance problem of ultrashallow S/D junction of sub50–nm MOSFETs [2]–[4], due to the abrupt silicide/Si interface and low resistance of silicide. The barrier height of the Schottky junction should be low enough to obtain a high-driving current [5] and to prevent two different slopes in the subthreshold re-gion of the MOSFETs [4], [6]. P-channel SSDT (P-SSDT) with PtSi as Schottky S/D (hole barrier – eV) has been fabricated with quite acceptable electrical performance with ratio of [6], [7] and one subthreshold slope of 66 mV/dec [6]. However, the electrical performance of N-channel SSDT (N-SSDT) is still inferior mainly due to lack of suitable silicide material [4]–[6]. Erbium silicide has been widely adopted for N-SSDT, but its relatively high electron

Manuscript received April 14, 2004; revised May 11, 2004. The review of this letter was arranged by Editor C.-P. Chang.

S. Zhu is with the Silicon Nano Device Laboratory, Department of Elec-trical and Computer Engineering, National University of Singapore, Singapore 119260 (e-mail: [email protected]). He is also with the Department of Micro-electronics, Fudan University, Shanghai 200433, China.

J. Chen, S. J. Lee, and C. X. Zhu are with the Silicon Nano Device Labora-tory, Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260.

M.-F. Li is with the Silicon Nano Device Laboratory, Department of Elec-trical and Computer Engineering, National University of Singapore, Singapore 119260 and also with the Institute of Microelectronics, Singapore 117685.

J. Singh, A. Du, and C. H. Tung are with the Institute of Microelectronics, Singapore 117685.

A. Chin is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu 300 Taiwan.

D. L. Kwong is with the Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712 USA.

Digital Object Identifier 10.1109/LED.2004.831582

barrier height and poor film morphology formed by solid-state reaction of deposited Er and substrate Si do not meet the device performance criteria. The ratio of the recently reported N-SSDT with ErSi is about [8]. On the other hand, the log versus curve shows two slopes at the subthreshold region for long-channel devices [4], [6]. DySi was reported recently [6]. However, it has the similar problems as that of Erbium silicide.

It is well known that the low work function metals usually have low Schottky electron barrier height [9]. Yb has lower pho-toelectric work function (2.59 eV) than Er (3.12 eV) and Dy (3.09 eV)1_{, therefore, Yb silicide is expected to have a lower}

Schottky electron barrier height. This is the motivation for Yb silicide to be used for N-SSDT and eventually can lead to an excellent electrical device performance.

II. MOS DEVICEFABRICATION

A simplified low-temperature process, which has been de-scribed in our previous paper [6], [10] was used to fabricate N-SSDT with HfO gate oxide and HfN/TaN metal gate. Starting substrates were p-type Si(100) wafers with resistivity of 4–8 cm. HfO (4–6 nm) was deposited at 400 C using Hf[OC(CH ) ] and O in a metal–organic CVD(MOCVD) system, followed by an in situ annealing in N ambient at 700 C. Then HfN ( nm) and TaN ( nm) were de-posited sequentially in a sputtering system with a base pressure of torr. Wafers were patterned and subsequently etched using the standard photolithograph and dry etch pro-cesses. Immediately after the diluted hydrogen fluoride (DHF) solution dipping, the patterned wafer was loaded into the sput-tering system again. Yb (or other RE metal: Er, Dy, Tb) ( nm) and HfN ( nm) were deposited in sequence. HfN was used as a capping layer to prevent RE metal oxidization during

ex situ annealing. Silicidation was performed by rapid thermal

anneal (RTA) at 600 C for 1 min in N ambient, followed by forming-gas anneal (FGA) at 420 C for 1 h. The silicidation can be performed by only a FGA step, while the YbSi film morphology is improved by the RTA step. The HfN capping layer and unreacted RE metal were selectively removed by wet etch in DHF (HF H O and sulphuric-acid hydrogen peroxide mixed (SPM) solution (H SO H O at 120 C) sequentially. The square sheet resistance of YbSi is /sq. and the thickness is nm [measured by

1_{The photoelectric work function data of various elements are from the}

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566 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 8, AUGUST 2004

Fig. 1. Room-temperature I–V curves of various RE silicide/p-Si(100) diodes and the linear fitting based on the thermal emission model. The deduced barrier heights and ideality factors are summarized in Table I.

Fig. 2. (Top) XTEM image of the final N-SSDT fabricated by the simplified one-mask process and a “hole” between the S/D and the gate acts as a sidewall spacer [10], and (bottom) a high resolution XTEM image of the polycrystalline YbSi /Si(100) contact. Even though the quite rough YbSi surface, which is probably affected by the SPM solution during the selectively etching step, the polycrystalline YbSi /Si interface is quite smooth and flat.

cross-sectional transmission electron microscopy (XTEM)], the resistivity of YbSi is calculated to be cm.

III. RESULTS ANDDISCUSSION

Fig. 1 shows current–voltage (I–V) curves of various RE silicide/p-Si(100) Schottky diodes. The Schottky hole barrier height and the ideality factor were deduced by linear fitting based on the thermal emission model [9]. The values are summarized in Table I. The hole barrier heights

deduced from capacitance–voltage (C–V) curves are also given. The YbSi /p-Si contact has the highest hole barrier height of 0.85 eV, lowest reverse bias leakage current, and the best recti-fying property with near unity ideality factor. Other diodes have significantly higher leakage current at reverse bias, larger than unity ideality factors and larger difference between and , implying the unnegligible barrier height inhomogeneity [11]. Observing in the microscope, the surfaces of ErSi and DySi contain many square pits with micrometer size. While there are no such pits on the surface of YbSi and TbSi even though their surface roughness is still quite large

Fig. 3. I –V and I -V curves of N-SSDT with YbSi S/D. The channel width and length are 400 and 4m respectively. Equivalent oxide thickness of HfO is 2.5 nm as deduced from C–V andV = 0:40 V.

TABLE I

ELECTRICALCHARACTERISTICS OFVARIOUSRE SILICIDE/p-Si(100) CONTACTSFORMED BYSOLID-STATEREACTION AND THECORRESPONDING

NSSDT PROPERTIES. BARRIERHEIGHTSDEDUCEDFROMC–V HAVE RELATIVELYLARGEDEVIATION. DATA OFPtSi/n-SiANDP-SSDT [6]

AREALSOINCLUDED FORCOMPARISON

as measured by atomic force microscopy. Fig. 2 (top) shows the cross-sectional XTEM image of the final N-SSDT fabricated by our simplified one-mask process.

Fig. 3 shows the – and – curves of N-SSDT with YbSi . The ratio reaches with one sub-threshold slope of mV/dec, and its drivability is slightly larger than the corresponding P-SSDT with PtSi with the same device structure (Table I). To our knowledge, this is the best electrical performance for N-SSDT reported so far. For com-parison, Fig. 4 shows the transfer characteristics of N-SSDT with the same device structure and technology, however using

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ZHU et al.: N-TYPE SCHOTTKY BARRIER S/D MOSFET USING YTTERBIUM SILICIDE 567

Fig. 4. Transfer characteristics of N-SSDTs with various RE silicides. All devices have the same size ofW=L = 400 m/4 m, and were fabricated by the same process.

ErSi , TbSi and DySi , respectively. The electrical results of these devices are summarized in Table I.

Besides the low electron barrier height, YbSi has better film quality than other RE silicides. The growth of ErSi or DySi during solid-state reaction of deposited RE metal and substrate Si (100) is strongly nucleation preferred, resulting in a nonuniform, columnar growth of the layer with rough surface and interface [12], [13]. The formed silicide has been reported to be ErSi or DySi due to the Si vacancy in the silicide film [4]. In the case of YbSi , the formed silicide has been reported to be YbSi [14]. Our x-ray diffraction and energy dispersive X-ray analysis (not shown here) also confirm that the formed film is YbSi . Less Si vacancy may cause the silicide more uniformly. From Fig. 2, the grain size of the polycrys-talline YbSi is about 5–10 nm and the grain growths approx-imately along Si[110] axis. Columnar growth, as in the cases of ErSi and DySi , was not found.

The RE silicide property is sensitive to the oxygen contam-ination. For ErSi silicide, eV when grown in ultrahigh-vacuum (UHV) condition [15], however becomes higher when grown in normal vacuum level as reported in this work and other paper [16], [17]. Our result shows that YbSi grown in normal vacuum condition has better rectifying charac-teristics than ErSi grown in UHV condition. It implies that YbSi is not so sensitive to oxygen as ErSi , or even better rectifying property of YbSi /Si contact may be obtained if it is grown in UHV condition. Very low barrier height (0.08 eV) of metal/n-Si contacts has been reported recently by surface passivation of a thin Se layer [18]. However, such method is infeasible for N-SSDT fabrication due to the requirement of self-aligned S/D formation.

IV. CONCLUSION

Several rare earth metals are investigated for silicide S/D. The YbSi has been found to be a very promising candidate for N-SSDT as it provides a high drive current with a very low leakage current. It is probably due to the low electron barrier height of the YbSi /Si Schottky contact and smooth

YbSi /Si interface. It can be concluded that YbSi is a much better silicide material than the usually used ErSi for N-SSDT.

REFERENCES

[1] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-ef-fect transistor using Schottky barrier contacts for source and drain,”

Proc. IEEE, vol. 56, pp. 1400–1401, 1968.

[2] M. Nishisaka, S. Matsumoto, and T. Asano, “Schottky source/drain SOI MOSFET with shallow doped-extension,” in Int. Conf. Solid-State

De-vices and Materials, 2002, pp. 586–587.

[3] H.-C. Lin, M. F. Wang, F. J. Hou, H. N. Lin, C. Y. Lu, J. T. Liu, and T. Y. Huang, “High- performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions,” IEEE

Electron Device Lett., vol. 24, pp. 102–104, Jan. 2003.

[4] J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T. J. King, and C. H. Hu, “Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime,” in IEDM Tech. Dig., 2000, pp. 57–60. [5] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of

short-channel Schottky source/drain metal–oxide–semiconductor field-effect transistor on silicon-on-insulator substrate and demonstra-tion of sub50-nm n-type devices with metal gate,” Jpn. J. Appl. Phys., vol. 38, pp. 6226–6231, 1999.

[6] S. Y. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Schottky barrier source/drain MOSFETs with high- gate dielectrics and metal gate electrode,” IEEE Electron Device

Lett., vol. 25, pp. 268–270, Mar. 2004.

[7] L. E. Calvet, H. Luebben, M. A. Reed, C. Wang, J. P. Snyder, and J. R. Tucker, “Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors,” J. Appl. Phys., vol. 91, no. 2, pp. 757–759, 2002.

[8] M. Jang, J. Oh, S. Maeng, W. Cho, S. Lee, K. Kang, and K. Park, “Char-acteristics of erbium-silicided n-type Schottky barrier tunnel transis-tors,” Appl. Phys. Lett., vol. 83, no. 13, pp. 2611–2613, 2003. [9] R. T. Tung, “Recent advances in Schottky barrier concepts,” Mater. Sci.

Eng., vol. 35, pp. 1–138, 2001.

[10] S. Y. Zhu, H. Y. Hu, J. D. Chen, S. J. Whang, J. H. Chen, C. Shen, C. X. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, “Low temperature MOSFET tech-nology with Schottky barrier source/drain, high- gate dielectric and metal gate electrode,” Solid State Electron., to be published.

[11] S. Y. Zhu, R. L. Van Meirhaeghe, C. Detavernier, F. Cardon, G. P. Ru, X. P. Qu, and B. Z. Li, “Barrier height inhomogeneities of epitaxial CoSi Schottky contacts on n-Si(100) and (111),” Solid State Electron., vol. 44, no. 4, pp. 663–671, 2000.

[12] C. H. Luo and L. J. Chen, “Growth kinetic of amorphous interlayers and formation of crystalline silicide phases in ultrahigh vacuum deposited polycrystalline Er and Tb thin films on (001)Si,” J. Appl. Phys., vol. 82, no. 8, pp. 3808–3814, 1997.

[13] A. Travlos, N. Salamouras, and N. Boukos, “Growth of rare earth sili-cides on silicon,” J. Phys. Chem. Sol., vol. 64, pp. 87–93, 2003. [14] K. S. Chi and L. J. Chen, “Formation of ytterbium silicide on (111) and

(001)Si by solid-state reactions,” Mater. Sci. Semicond. Processing, vol. 4, pp. 269–272, 2001.

[15] P. Muret, T. A. N. Tan, N. Frangis, and J. van Landuyt, “Unpinning of the Fermi level at erbium silicide/silicon interface,” Phys. Rev. B, Condens.

Matter, vol. 56, no. 15, pp. 9286–9289, 1997.

[16] G. Kaltsas, A. Travlos, N. Salamouras, A. G. Nassiopoulos, P. Revva, and A. Traverse, “Erbium silicide films on (100) silicon, grown in high vacuum, fabrication and properties,” Thin Solid Films, vol. 275, pp. 87–90, 1996.

[17] Z. Xu, Properties of Metal Silicides, K. Maex and M. Van Rossum, Eds. London, U.K.: Inspec, 1995, pp. 217–224.

[18] M. Tao, S. Agarwal, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, “Low Schottky barriers on n-type silicon (001),” Appl. Phys. Lett., vol. 83, no. 13, pp. 2593–2595, 2003.

[19] M. Q. Huda and K. Sakamoto, “Use of ErSi in source/drain contacts of ultrathin SOI MOSFETs,” Mater. Sci. Eng., vol. B89, pp. 378–381, 2002.