Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers

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Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers


Michael Henderson Perrott

Bachelor of Science in Electrical Engineering New Mexico State University, December 1988

Master of Science in Electrical Engineering and Computer Science Massachusetts Institute of Technology, June 1992

Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of

Doctor of Philosophy in Electrical Engineering and Computer Science

at the

Massachusetts Institute of Technology September 1997

 1997 Massachusetts Institute of Technology. All rights reserved.c

Signature of Author

Department of Electrical Engineering and Computer Science September 3, 1997 Certified by

Charles G. Sodini, Ph.D.

Professor of Electrical Engineering Thesis Supervisor Certified by

Mitchell D. Trott, Ph.D.

Professor of Electrical Engineering Thesis Supervisor Accepted by

Arthur Clarke Smith, Ph.D.

Chairman, Committee on Graduate Students Department of Electrical Engineering and Computer Science


Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers


Michael Henderson Perrott

Submitted to the Department of Electrical Engineering and Computer Science on September 3, 1997 in partial fulfillment of the requirements for the degree of

Doctor of Philosophy in Electrical Engineering and Computer Science


A digital compensation method is described that allows fractional-N frequency syn- thesizers to be directly modulated at high data rates while simultaneously achieving good noise performance. The technique allows digital phase/frequency modulation to be achieved at high data rates (> 1 Mbit/s) without mixers or D/A converters in the modulation path. The resulting transmitter design is primarily digital in nature and reduced to its fundamental components — a frequency synthesizer that accurately sets the output frequency, and a digital transmit filter that provides good spectral efficiency.

The synthesizer is implemented as a phase locked loop (PLL). To achieve good noise performance with a simple design, the PLL bandwidth is set to a low value relative to the data bandwidth. A digital compensation filter is then used to undo the attenuation of the PLL transfer function seen by the data. This filter adds little complexity to the transmitter architecture since it can be combined with the digital transmit filter; the overall filter is efficiently implemented by using a ROM to perform the required convolution with input data.

Measured results from a prototype indicate that good performance, low power operation, and high levels of integration are achieved with the approach. Specifically, a 1.8 GHz transmitter was built that supports data rates in excess of 2.5 Mbit/s using Gaussian Frequency Shift Keying (GFSK), the same modulation method used in the digital enhanced cordless telecommunications (DECT) standard. The phase noise of the unmodulated synthesizer was measured at -132 dBc/Hz at 5 MHz offset from the carrier frequency. (Simulations show that the modulated synthesizer achieves -132 dBc/Hz at 5 MHz offset at 1.25 Mbit/s data rate.)

The key circuits in the prototype were implemented on a custom, 0.6 um CMOS IC that consumes 27 mW. Included on the IC are an on-chip filter that requires no tuning or external components, a digital MASH Sigma-Delta converter that achieves low power operation through pipelining, and an asynchronous, 64 modulus divider (prescaler) that supports any divide value between 32 and 63.5 in half cycle increments of its input. An external divide-by-2 prescaler allows the divider to operate at half



Thesis Supervisors: Charles G. Sodini and Mitchell D. Trott Titles: Professor of Electrical Engineering



He had no beauty or majesty to attract us to him, nothing in his appearance

that we should desire him.

But he was pierced for our transgressions, he was crushed for our


the punishment that brought us peace was upon him, and by his wounds we are


Isaiah 53:2,5




The work presented in this thesis could not have happened without the help and support of many people. Mitch Trott introduced me to communication theory, and was supportive of my efforts to pursue the hardware side of that field. His sugges- tions were invaluable to my efforts of modeling the modulated PLL. Charlie Sodini introduced me to analog circuit design and device physics; he believed in me from the beginning of this effort, and has been a constant source of encouragement throughout its duration. Ted Tewksbury championed the project at Analog Devices, and saved the day many a time when implementation obstacles arose. Hae-Seung Lee taught me the art of analog circuit design; I am indebted to his instruction. Anantha Chan- drakasan taught me low power circuit design techniques, and spent time with me as I investigated low power Σ-∆ topologies.

The people at Analog Devices played crucial roles in the design and implementa- tion of the synthesizer. Jean-Marc Mourant and Geoff Dawe provided guidance on RF issues; their insight overcame many mysteries in that field. Peter Katzin was a sounding board for system issues, and helped me avoid pitfalls that only experience can warn you about. Zoran Zvonar listened to my ideas for modulation methods, and was a strong influence in my final choice of GFSK. Dan Fague provided insight of practical issues related to GFSK and the DECT standard. Paul Ferguson gave valu- able advice related to the layout of my circuits, and analysis of their behavior. Bob Broughton helped me through the difficult task of making phase noise measurements of the system. Rob Weiner did an amazing job of bonding the die.

My colleagues at MIT provided a great deal of technical assistance, and also enriched my experience with their friendships. Jeff Gealow taught me many things about UNIX; he and Jen Lloyd provided the framework I used for writing the Cadence technology file needed for layout of the IC. Dan McMahill tested and built several circuits that allowed me to demonstrate the transmitter, and provided help with many practical matters. Don Hitko also provided practical insight, especially with respect to FrameMaker. Duke Xanthopoulos and Jim Goodman came to my aid when I encountered problems with software tools.

Marilyn Pierce helped me through many administrative matters in the EECS department; Monica Bell and Lisa Bella provided assistance in this area, as well. Pat Varley guided me through the paperwork involved in my many purchases, and did an



measurement methods and PLL design issues. DARPA provided funding for this project under contract DAAL-01-95-K-3526.

I would like to thank my parents, Charles and Emily, and my sisters, Nikki and Missy, for their love, support, and encouragement through these many years of grad- uate school. I thank God for bringing me through this experience; to Him be the glory.




1 Introduction 21

1.1 Area of Focus . . . 22

1.2 Modulator Architectures . . . 22

1.3 Phase Locked Loop Frequency Synthesis . . . 25

1.4 Direct Modulation of a Frequency Synthesizer . . . 28

1.5 The Challenge of Achieving High Data Rates and Low Noise . . . 31

1.6 Proposed Method . . . 32

1.7 Issues . . . 34

1.8 Implementation Highlights . . . 35

1.8.1 Divider . . . 37

1.8.2 Loop Filter . . . 38

1.8.3 Σ-∆ structure . . . 39

1.9 Contributions . . . 40

1.10 Overview of Thesis . . . 41

2 Modeling 43 2.1 PLL Basics . . . 43

2.2 Frequency Domain Model . . . 44

2.2.1 Definition of Phase/Frequency Signals . . . 44

2.2.2 Derivation of PFD Model . . . 46

2.2.3 Derivation of Divider Model . . . 47

2.2.4 Modeling of Divider Sampling Operation . . . 48

2.2.5 Overall Model . . . 49

2.3 Parameterization of the PLL Model . . . 51

2.4 Frequency Control Without Σ-∆ Modulation . . . 52

2.5 Σ-∆ Modulation Principles . . . 53

2.5.1 Fractional-N Modulator Model . . . . 54

2.6 Summary . . . 56

3 Noise Properties of a Modulated Synthesizer 57 3.1 The Relationship Between Φtn(t), Φmod(t), and the Output Spectrum 57 3.2 Interaction of Modulation and Noise on Output Spectrum . . . 59



3.3 The Influence of PLL Parameters on Noise Performance . . . 60

3.3.1 Qualitative Analysis . . . 61

3.3.2 Quantitative Analysis . . . 62

3.4 Summary . . . 64

4 The Challenge of High Data Rate Modulation 65 4.1 Data Rate versus PLL Bandwidth . . . 67

4.2 Data Rate versus PLL order and Σ-∆ Sample Rate . . . 69

4.3 Summary . . . 70

5 Proposed Approach 73 5.1 Derivation of Compensated FIR Filter Under GFSK Modulation . . . 74

5.2 Implementation of Compensated FIR Filter . . . 75

5.3 Achievable Data Rates . . . 76

5.3.1 Available Dynamic Range . . . 76

5.3.2 Dynamic Range Requirements Versus Data Rate . . . 78

5.3.3 Achievable Data Rates versus n and 1/T . . . . 82

5.3.4 Simulated Signals at 3.33 Mbit/s . . . 83

5.4 ROM Power Savings . . . 84

5.5 Summary . . . 84

6 The Influence of Mismatch 87 6.1 The Choice of Loop Filter . . . 87

6.2 Resulting Closed Loop Behavior . . . 88

6.3 Effect on Compensation . . . 89

6.4 Additional Sources of Mismatch . . . 91

6.5 Minimization of Mismatch . . . 91

6.6 Summary . . . 93

7 Divider 95 7.1 Architectural Approach . . . 95

7.1.1 The Dual-Modulus Divider . . . 96

7.1.2 A Multi-Modulus Divider Architecture . . . 97

7.1.3 Divide-by-2/3 Architecture . . . 97

7.2 Implementation . . . 103

7.2.1 Divide-by-2/2.5/3/3.5 Core Design . . . 103

7.2.2 Divide-by-2/3 Core Design . . . 110

7.2.3 Control Qualification Circuits . . . 113

7.2.4 Mapping Logic . . . 114

7.3 Summary . . . 115



8 Digital Data Path 117

8.1 Topology . . . 118

8.2 Pipelining Technique . . . 119

8.3 Depth of Pipelining . . . 121

8.4 Circuit Implementation . . . 122

8.5 Summary . . . 124

9 Analog Phase Comparison Path 125 9.1 Implementation . . . 126

9.1.1 PFD . . . 126

9.1.2 Charge Pump . . . 129

9.1.3 Loop Filter . . . 131

9.1.4 D/A Converter and Biasing . . . 133

9.2 Modeling . . . 133

9.2.1 Switched Capacitor Implementation . . . 136

9.2.2 Integrating Section . . . 141

9.2.3 Overall Model . . . 142

9.3 The Impact of Large Pulse Widths in Ie(t) . . . . 144

9.3.1 Examination of Power Spectrum of IIN(t) at 2.5 Mbit/s . . . . 146

9.3.2 Explanation for Existence of Spurs at Multiples of 1/Td . . . . 148

9.4 Summary . . . 150

10 Prototype System 153 10.1 Implementation . . . 153

10.2 Linearized Model . . . 154

10.3 Selection of Parameters . . . 155

10.4 Noise Calculations . . . 159

10.4.1 A Simplified Model for Noise Analysis . . . 160

10.4.2 Resulting Transmitter Output Noise . . . 162

10.5 Summary . . . 164

11 Results 165 11.1 Baseline Performance . . . 165

11.1.1 Ideal Performance . . . 166

11.1.2 Influence of Noise on Output Spectrum . . . 167

11.2 Modulation Performance . . . 167

11.2.1 Simulation Results . . . 168

11.2.2 Measured Results . . . 171

11.3 Noise Performance . . . 173

11.3.1 Noise Measurement Considerations . . . 173

11.3.2 Simulated Results . . . 175

11.3.3 Measured Results . . . 178


11.4 Summary . . . 178

12 Conclusions 181 12.1 Future Research . . . 182

References 183 A Board Design 189 A.1 Overview . . . 189

A.2 Schematics . . . 190

A.3 Layout . . . 190

A.4 Mechanical Information . . . 193

B Bonding Diagram 199


List of Figures

1.1 A driving application: wireless video. . . 21

1.2 General block diagram of a narrowband transmitter. . . 22

1.3 Two current approaches of modulation upconversion: (a) mixer based, (b) direct modulation of VCO. . . 24

1.4 A phase locked loop frequency synthesizer. . . 26

1.5 The fractional-N synthesizer architecture. . . . 27

1.6 Signals associated with fractional-N synthesis with N=4.25. . . . 27

1.7 A 1-bit Σ-∆ D/A converter. . . 28

1.8 Direct modulation of a frequency synthesizer. . . 29

1.9 A spectrally efficient, fractional-N modulator. . . . 30

1.10 Linearized model of fractional-N modulator. . . . 30

1.11 The conflict of high data rate and low noise performance. . . 31

1.12 Achievable data rates vs. PLL order and Σ-∆ sample rate. . . 32

1.13 Proposed compensation method. . . 33

1.14 Comparison of achievable data rates with and without compensation vs. PLL order and Σ-∆ sample rate. . . 34

1.15 The effect of mismatch. . . 35

1.16 High data rate costs dynamic range. . . 35

1.17 Overall System. . . 36

1.18 An asynchronous, 8-modulus divider topology. . . 38

1.19 An asynchronous, 64 modulus divider implementation. . . 38

1.20 PFD, charge pump, and loop filter. . . 39

1.21 A second order, digital MASH, Σ-∆ structure. . . 40

1.22 A pipelined adder topology. . . 40

2.1 A PLL and associated signals when the divide value is varied. . . 44

2.2 Definition of tk. . . 45

2.3 Frequency domain modeling of discrete-time signals in PLL. . . 49

2.4 Linearized models of PLL components. . . 50

2.5 Overall PLL model. . . 51

2.6 Parameterized PLL model. . . 52

2.7 Simple FSK modulation of the PLL. . . 52

2.8 Σ-∆ modulation applied to Fractional-N synthesis. . . . 54 13


2.9 Model of frequency modulation of the PLL output when its divide

value is dithered by a Σ-∆ modulator. . . 55

2.10 Alternate representation of Σ-∆ model. . . 55

2.11 Separation of PLL model into signal and noise sections. . . 56

3.1 Illustration of the relationship between modeled phase, Φout(t), and the transmitter output, Out (t). . . . 58

3.2 Signal and noise components of the modulated output spectrum. . . . 60

3.3 View of noise components. . . 61

3.4 Calculation of fo, 1/T , and n that achieve Stn,q(f ) of -136 dBc/Hz at 5 MHz offset. . . 64

4.1 A spectrally efficient, fractional-N modulator. . . 66

4.2 Linearized model of fractional-N modulator. . . 66

4.3 Model of data path. . . 67

4.4 Normalized Eye Diagrams for various values of foTd: (a) foTd = ∞, (b) foTd = 0.7, (c) foTd= 0.5. . . . 69

4.5 Achievable data rates vs. PLL order and Σ-∆ sample rate when SΦtn,q(f ) is -136 dBc/Hz at f = 5 MHz. . . . 70

5.1 Compensation Method . . . 73

5.2 The relationship between inw(t) and data(t). . . . 75

5.3 Phase/Frequency modulation using divider in PLL. . . 76

5.4 Implementation of D/A Function within G(f). . . 77

5.5 Linearized model of fractional-N modulator with compensation. . . . 79

5.6 Resulting signal deviation of insd(t) as a function of 1/(foTd) for 1/T equal to 20, 40, and 80 MHz. . . 80

5.7 Block diagram of transfer function relationship between inw(t) and ˆΦe(t). 80 5.8 Rearranged block diagram of transfer function relationship between inw(t) and ˆΦe(t). . . . 80

5.9 Percent deviation of Φe(t) versus 1/(foTd). (100 % deviation corre- sponds to a peak-to-peak deviation of Φe(t) that is 2π.) . . . . 81

5.10 Comparison of achievable data rates with and without compensation vs. PLL order and Σ-∆ sample rate. . . 83

5.11 Simulated signals within PLL at 3.33 Mbit/s data rate when using compensation: (a) divider input deviation, (b) VCO input, (c) VCO input after being filtered with a 7 MHz Hamming filter. . . 85

5.12 Simulated signals within PLL at 3.33 Mbit/s data rate when using compensation (reduced time scale): (a) divider input deviation, (b) PFD output, (c) VCO input, (d) VCO input after being filtered with a 7 MHz Hamming filter. . . 86

6.1 Laplace domain PLL model with extraneous signals removed. . . 87



6.2 Root locus of PLL transfer function. . . 89

6.3 Intersymbol interference due to parasitic pole/zero. . . 91

6.4 Root locus of PLL transfer function. . . 92

6.5 Accurate setting of fp using a switched capacitor technique . . . 92

7.1 An 8/9 dual modulus divider. . . 96

7.2 An 8 modulus divider. . . 98

7.3 A divide-by-2 circuit implemented as a Johnson counter. . . 99

7.4 Example of divide-by-2/3 implementation using gating logic. . . 99

7.5 A divide-by-2/3 core circuit implemented by gating the feedback in a Johnson counter. . . 100

7.6 A divide-by-2/3 core circuit implemented by multiplexing the divided output of a Johnson counter. . . 101

7.7 A divide-by-4/5 structure implemented by multiplexing a 4 phase divide- by-2 circuit. . . 101

7.8 Timing diagram of a divide-by-4/5 structure performing a divide-by-7 operation by swallowing 3 input cycles per OUT period. . . . 102

7.9 A 64 modulus divider architecture. . . 103

7.10 Divide-by-2/2.5/3/3.5 architecture. . . 104

7.11 A four-phase divide-by-2 circuit. . . 105

7.12 High speed ECL to CMOS amplifier. . . 105

7.13 Multiplexer topology. . . 106

7.14 Multiplexer control strategy to realize glitch-free phase switching. . . 107

7.15 State transition diagram to achieve phase switching control strategy. . 108

7.16 An efficient implementation of the phase switching state diagram. . . 108

7.17 Proposed PMOS-coupled latch design. . . 109

7.18 Complete state diagram to realize appropriate transitions between and selective stopping on divider phases. . . 110

7.19 Selective-blocking (SB) register using PMOS-coupled (PC) latches. . 110

7.20 Complete state machine implementation to control phase transitions. 111 7.21 Divide-by-2/3 core design. . . 111

7.22 Multiplexer for divide-by-2/3 core. . . 112

7.23 Divide-by-2/3 phase transition timing. . . 113

7.24 Divide-by-2/3 state transition diagram. . . 113

7.25 Divide-by-2/3 state machine implementation. . . 114

7.26 Qualification circuit and timing for divide-by-2/2.5/3/3.5 section. . . 115

7.27 Qualification circuit and timing for divide-by-2/3 sections. . . 115

7.28 Mapping logic from divide value to control signal for divide-by-2/2.5/3/3.5 section. . . 116

7.29 Mapping logic from divide value to control signal for divide-by-2/3 section. . . 116


8.1 Digital data path to divider input. . . 117

8.2 Bit alignment between modulation signal and Nnom when added to form INsd[k]. . . . 118

8.3 A second order, digital MASH structure. . . 119

8.4 A pipelined adder topology. . . 120

8.5 A pipelined accumulator topology. . . 120

8.6 A pipelined, second order, digital MASH structure. . . 121

8.7 Pipelined digital data path to divider input. . . 121

8.8 A static mirror adder circuit. . . 123

8.9 Dynamic TSPC register circuits: (a) inverting, (b) non-inverting. . . 123

8.10 Measured power dissipation of Σ-∆ vs. supply voltage. . . 124

9.1 Analog phase comparison path consisting of a PFD, charge pump, and loop filter. . . 126

9.2 Schematic diagram of PFD. . . 127

9.3 XOR characteristic and associated signals within the PFD. . . 128

9.4 State transition diagram of the frequency detector portion of the PFD. 128 9.5 Example of signals produced from PFD when Div frequency is too high.129 9.6 Effect of transient time and mismatch on duty cycle range. . . 130

9.7 Charge pump implementation. . . 130

9.8 Interface circuitry between PFD and charge pump that level converts E from digital to analog supplies, and sets the sign of the open loop gain. . . 131

9.9 Loop filter implementation. . . 132

9.10 Opamp implementation for loop filter. . . 133

9.11 D/A converter (5-bit) and biasing circuitry. . . 134

9.12 Characterization of 5-bit D/A converter. . . 134

9.13 Decomposition of IIN(t). . . . 135

9.14 Loop filter model. . . 137

9.15 Model of first order switched capacitor filter. . . 138

9.16 Example signals occurring in first order switched capacitor filter. . . . 139

9.17 Definition of QL[k] and QR[k]. . . . 140

9.18 Signals associated with switched capacitor filter. . . 141

9.19 Frequency domain view of switched capacitor filter, PFD, and charge pump assuming the pulse widths in Ie(t) are small and to= 0. . . 141

9.20 Integrating portion of loop filter. . . 142

9.21 Signals associated with integrating portion of loop filter. . . 143

9.22 Frequency domain model of integrating portion of loop filter, PFD, and charge pump assuming the pulse widths in Ie(t) are small and to = 0. 143 9.23 Overall model of PFD, charge pump, and loop filter assuming the pulse widths of Ie(t) are small and to = 0. . . 143

9.24 Comparison of |H(f)|, |HD(f )|, and |HR(f )| (scale is normalized). . . 145



9.25 Comparison of the magnitude and phase of H(f ) and HD(f ). . . . 145

9.26 Power spectra of (a) ˆΦe(t) and (b) IIN(t) under 2.5 Mbit/s GFSK modulation. . . 147

9.27 Power spectrum of IIN(t) at high frequencies. . . . 148

9.28 Computed value of g(t) from simulation data. . . . 151

10.1 Block diagram of prototype system. . . 154

10.2 Die photo of custom IC used in the prototype. . . 155

10.3 Linearized, frequency-domain model of prototype system. . . 156

10.4 Root locus of PLL. . . 156

10.5 Expanded View of PLL System. . . 158

10.6 Model of test system with lumped noise sources added. . . 161

10.7 The lumping together of current noise sources entering OP2. . . 162

10.8 Calculated noise spectra of synthesizer: (1) charge pump induced, SΦi(f ), (2) VCO and opamp induced, SΦv(f ), (3) Σ-∆ induced, SΦq(f ), (4) overall, SΦ(f ). . . . 163

11.1 Ideal results for GFSK modulation (machine computed): (a) eye dia- gram at 1.25 Mbit/s, (b) output spectrum, Soutm(f ), at 1.25 Mbit/s, (c) eye diagram at 2.5 Mbit/s, (d) output spectrum, Soutm(f ), at 2.5 Mbit/s. . . 166

11.2 Comparison of simulated modulation and calculated noise spectra (Soutm(f ) and SΦtn(f ), respectively): (a) 1.25 Mbit/s, (b) 2.5 Mbit/s. . . . 168

11.3 Simulated results at 1.25 Mbit/s data rate: (a) eye diagram, (b) output spectrum, Sout(f ). . . . 169

11.4 Simulated eye diagrams at 1.25 Mbit/s for three different open loop gain settings: (a) -25% gain error, (b) 0% gain error, (c) 25% gain error.169 11.5 Graphical explanation of cause of deviation error and ISI. . . 170

11.6 Simulated results at 2.5 Mbit/s data rate: (a) eye diagram, (b) output spectrum, Sout(f ). . . . 171

11.7 Simulated eye diagrams at 2.5 Mbit/s for three different open loop gain settings: (a) -25% gain error, (b) 0% gain error, (c) 25% gain error. . 171

11.8 Graphical explanation of dependence of ISI level on data rate. . . 172

11.9 Measured results at 1.25 Mbit/s data rate with zero open loop gain er- ror: (a) eye diagram, (b) output spectrum (1.84 GHz center frequency, 5 MHz span). . . 172

11.10Measured results at 2.5 Mbit/s data rate with zero open loop gain error: (a) eye diagram, (b) output spectrum (1.84 GHz center frequency, 10 MHz span). . . 173


11.11Measured eye diagrams at 1.25 Mbit/s and 2.5 Mbit/s for three differ- ent open loop gain settings: (d) 1.25 Mbit/s, -25% gain error, (e) 1.25 Mbit/s, 0% gain error, (f) 1.25 Mbit/s, 25% gain error, (a) 2.5 Mbit/s, -25% gain error, (b) 2.5 Mbit/s, 0% gain error, (c) 2.5 Mbit/s, 25%

gain error. . . 174

11.12Binary dithering sequence fed into least significant bit of digital mod- ulation path. . . 175

11.13Simulated phase noise, SΦtn(f ), of unmodulated synthesizer: (a) Σ-∆ removed, (b) Σ-∆ in place and appropriately dithered. . . 176

11.14Simulation results of PLL output spectrum with noise sources included: (a) SΦout(f ) at 1.25 Mbit/s, (b) Sout(f ) at 1.25 Mbit/s, (c) (a) SΦout(f ) at 2.5 Mbit/s, (d) Sout(f ) at 2.5 Mbit/s. . . . 177

11.15Measured phase noise, SΦtn(f ), of unmodulated synthesizer and of open loop VCO: (a) Σ-∆ removed, (b) Σ-∆ in place and appropriately dithered.179 A.1 Description of layers in PC board. . . 189

A.2 Preliminary layout of PC board. . . 191

A.3 Illustration of plated through holes in PC board. . . 192

A.4 Mount points on PC board. . . 193

A.5 Primary schematic diagram of PC board. . . 195

A.6 Schematic diagram of I/O section of PC board. . . 196

A.7 Schematic diagram of RF section of PC board. . . 197

A.8 Schematic diagram of power regulating section of PC board. . . 198

B.1 Bonding diagram of custom PLL IC. . . 199


List of Tables

1.1 Theoretically achievable data rates using compensation for second or-

der PLL. . . 33

1.2 Modulator specifications. . . 36

3.1 Influence of parameters in G(f ) and of 1/T on individual noise source contributions to the overall phase noise spectral density, SΦtn(f ), at intermediate frequency offsets. . . 62

5.1 Range of divide values for multi-modulus divider used in prototype. . 77

5.2 Parameter values for evaluation of achievable data rates using compen- sation. . . 82

5.3 Achievable data rates with compensation. . . 83

8.1 Energy consumed by circuit blocks within the digital data path with a 1.5 volt supply . . . 122

8.2 Number of adders and registers for the pipelined (2-bit) and non- pipelined case of the digital data path. . . 124

10.1 Power dissipation of IC circuits. . . 154

10.2 Open loop parameter settings in PLL that achieve a closed loop re- sponse with fo = 84 kHz. . . 158

10.3 Component values for prototype system. . . 159

10.4 Simulated opamp specifications. . . 159

10.5 Values of noise sources within PLL. . . 160

A.1 Parts list for PC board in prototype . . . 194



Chapter 1 Introduction

The use of wireless products has been rapidly increasing the last few years, and there has been world wide development of new systems to meet the needs of this growing market. Characteristics such as low power operation, small size, and low cost have become the dominant design criteria by which these systems are judged.

As a result, new circuit techniques have been sought to allow increased integration of radio transmitters and receivers, along with new radio architectures that take advantage of such techniques.

Motivated by the above goals, a low power and high performance narrowband transmitter for wireless communication that is highly integrated in silicon technology is presented in this thesis. As a driving application, the transmitter has been designed to meet the needs of a wireless video system depicted in Figure 1.1. Such a system requires digital modulation to be performed at data rates in excess of 1 Mbit/s. Rather than incrementally improving an existing design, a digital compensation technique is presented that allows the transmitter to be reduced to its fundamental components so that high integration and low power dissipation are achieved. New circuit techniques are employed to obtain high performance in the proposed design.

Imager A/D DSP Transmitter Electronic Camera

Figure 1.1: A driving application: wireless video.

The remainder of this chapter presents an overview of the thesis. We will begin by narrowing the focus of the project and presenting performance goals. Background information related to transmitter architectures is reviewed, and motivation for the proposed transmitter topology presented. The challenges of implementing such a de-



sign are then discussed, and an implementation that overcomes the primary obstacles is outlined. Finally, a detailed outline of the thesis is presented.

1.1 Area of Focus

Figure 1.2 displays a general block diagram of a narrowband transmitter capable of digital communication. The system consists of a modulator block that varies the

Amplitude/Phase Amp Modulator Data Bits

Carrier Frequency


Figure 1.2: General block diagram of a narrowband transmitter.

amplitude, phase, or frequency of an output sine wave in response to an incoming bit sequence, a power amplifier, and a bandpass filter that is broad enough to pass all allowable communication channels. Assuming Figure 1.2 is representative of all narrowband transmitters, modifications to its architecture are primarily limited to the modulator block. Because of this fact, the focus of this thesis will be restricted to this block; the power amp and bandpass filter will be considered only in enough detail to address their impact on the modulator design.

The primary aspect of the modulator block that must be considered in relation to the power amp is the choice of modulation. Since power amps are most power efficient when producing a constant envelope signal [1–3], amplitude modulation should be avoided. Therefore, we will restrict our attention to phase or frequency modulation.

The impact of the bandpass filter on the modulator is limited primarily to noise issues. Since it must be wide enough to pass all channels, the filter does little to attenuate noise produced by the modulator just outside of the desired channel band- width. Therefore, the modulator must meet fairly stringent noise requirements, as will be specified below.

1.2 Modulator Architectures

Radio transmitters revolve around a common goal — a low frequency modulation sig- nal must be translated to a desired RF band. Since the advent of the superheterodyne design by Armstrong (which dates back to 1918 [4]), the majority of high performance, narrowband transmitters have accomplished this frequency translation using mixers



and an intermediate frequency (IF) region of operation to perform highly-selective filtering [4]. While such an approach offers excellent radio performance (low spurious noise for transmitters), it carries with it a high cost of implementation in light of efforts to integrate radio architectures. Specifically, this approach is impeded by the inability to integrate the high-Q, low-noise, low-distortion bandpass filters required at IF frequencies (often on the order of 70 to 100 MHz for 900 MHz systems) [5].

For the above reasons, research into non-heterodyne architectures has taken place over the last few years in response to the growing demand for portable communication devices. Indeed, the use of direct carrier modulation has now become widespread in transmitters [5], which allows the channel shaping filters to be implemented at baseband and thus be integrated. A large wave of such designs implementing the global system for mobile communication (GSM) standard at 900 MHz in bipolar technology have appeared in the last five years, as described in [6–11]. Boasting of high integration, these chips achieved transmitter power consumptions as low as 162 mW [8], not including the power amplifier or baseband circuitry. In an effort to further reduce power through integration, Abidi et al. set out to create an all-CMOS transceiver that would implement all functions associated with their own frequency- hopped, 900 MHz, spread spectrum modulation scheme on one chip with the exception of the antennas and 900 MHz passive bandpass filters [12]. The power consumption of the transmitter portion of this chip is currently estimated at 300 mW, of which 60 mW can be attributed to the on-chip power amplifier. All told, the lowest power consumption of any high performance transmitter to date at 900 MHz (excluding the power amplifier) is probably around 200 mW, and is based on the design described by Stetzler et al. with an estimate of 30 mW for the baseband circuitry [13].

Motivated by the existing digital enhanced cordless telecommunications stan- dard (DECT) [14], and the newly allocated PCS band in North America, a push for transceivers that operate at 1.8 GHz in silicon technology has recently taken place [15–19]. Of the new designs, the one that appears most promising in terms of power consumption involves the direct modulation of a VCO. An example of this approach was described by Heinen et al. in [15], which claimed a transmitter power consumption of 90 mW (excluding PLL circuitry, baseband circuitry, and power am- plifier). Estimating the total power consumption of this approach at 150 mW (the power amplifier is excluded, the power consumption of the PLL circuitry is assumed to be 30 mW [20], and the baseband circuitry is assumed to be 30 mW [13]), we are led to the conclusion that this new design dissipates less power than its direct conversion counterparts operating at half the carrier frequency (i.e., 900 MHz).

What is the advantage of directly modulating the VCO? To answer this question, Figure 1.3 displays the basic operations that are used to perform frequency translation in the above designs. The prevalent method, shown in part (a), is to use a mixer to multiply the modulation signal by a periodic waveform produced by a voltage controlled oscillator (VCO) whose frequency is precisely set through the action of a frequency synthesizer. In the case of direct conversion, the modulation waveform is


an analog signal composed of I and Q channels which are directly translated from baseband to the desired RF frequency and then added together. The superheterodyne approach uses at least two stages of mixers to accomplish the frequency translation so that an intermediate filtering stage can be employed. As discussed above, the direct conversion method is preferred to achieve high integration. However, it should be noted that this method requires two mixers and D/A converters to accommodate the I and Q channels.


Select Frequency Synthesizer

Modulation Out

Freq. Out Select


Frequency Synthesizer

(a) (b)

Figure 1.3: Two current approaches of modulation upconversion: (a) mixer based, (b) direct modulation of VCO.

The removal of all mixers can be accomplished by using the VCO to perform the required frequency translation. As illustrated in part (b) of the figure, the translation is accomplished by injecting the baseband, analog modulation signal into the input of the VCO after the frequency synthesizer has guided the VCO output to the desired carrier frequency. (Note that a multi-bit D/A converter is required to produce the analog modulation signal.) The advantage of Heinen’s approach is now seen — the transmitter is reduced to a simpler structure since all mixers are removed. This technique restricts the modulated RF output to be phase or frequency modulated, but this is desirable from the standpoint of achieving high efficiency in the power amp as previously discussed.

Although simple in theory, there are many challenging implementation issues as- sociated with direct modulation of the VCO. The primary source of difficulty is that the mapping from the VCO input to its output frequency is sensitive to process and temperature variations, thus requiring control by the frequency synthesizer to achieve an accurate frequency setting. However, if the frequency synthesizer is allowed to in- fluence the VCO during modulation, it will interfere with the modulated data. This problem is solved by using an ‘open loop’ approach in which the frequency synthe- sizer is disconnected during transmission. However, in the absence of influence by the synthesizer, the frequency setting of the VCO becomes very sensitive to undesired perturbations. As a result, great steps must be taken to achieve high isolation of the VCO input from such perturbations, and all leakage currents must be minimized to avoid significant frequency drift during modulation. As Heinen explains in [21],



the isolation requirements for this method exclude the possibility of a one chip solu- tion. Therefore, while the approach offers a significant advantage in terms of power dissipation, the goal of high integration is lost.

In contrast to the approach of directly modulating the VCO, Riley et al. introduced a technique in [22] to indirectly modulate the VCO by varying the divide value within a phase locked loop. In order to get fine resolution on the divide value, Riley made use of a fractional-N architecture with noise shaping discussed in [23–25]. The beauty of this technique lies in the fact that modulation of the VCO is performed in a closed loop manner through the influence of the frequency synthesizer. Therefore, the problem of frequency drift during modulation is eliminated, and the isolation requirements at the VCO input are greatly reduced at frequencies within the PLL bandwidth. The input to the synthesizer is digital in nature, which allows elimination of the multi-bit D/A converter that is required when directly modulating the VCO. In effect, Riley’s approach amounts to directly modulating a frequency synthesizer.

1.3 Phase Locked Loop Frequency Synthesis

The first step toward implementing a modulated frequency synthesizer is to choose the synthesizer topology. The indirect method which involves the use of a phase locked loop (PLL) has the advantages of low power, feasibility of monolithic imple- mentation, and phase coherence during frequency transitions [23, 26, 27]. There have been many approaches to the topological design of such synthesizers over the last 20 years represented in the literature [23–25, 27–38], with implementations in silicon at and above the 1 GHz range given in [39–45]. The point that is important to glean from these many approaches is that it is quite challenging to build a monolithic, low complexity synthesizer that simultaneously has low phase noise, fine frequency resolution, and fast dynamics.

Figure 1.4 displays the classical PLL frequency synthesizer topology consisting of a voltage controlled oscillator (VCO), a phase/frequency detector (PFD), a loop filter, a divider, and reference frequency source. Accurate control of the phase, and thus frequency, of the VCO is achieved through the feedback action of the loop. This feat is accomplished by using an error signal to control the VCO — specifically, the PFD produces a signal corresponding to the phase difference between the divided output and a reference frequency source, which is then ‘smoothed’ by the loop filter and fed into the VCO input. In equilibrium, the actions of the PLL lead to a condition known as ‘lock’ in which the frequency of the VCO, Fout, tracks that of the reference frequency, Fref, such that

Fout = N Fref,

where N is the value of the divider. Assuming the reference frequency is held constant, the VCO frequency is changed by altering the divide value, N .


PFD Loop Filter


Ref Out


Out Ref Div

Freq. Select Vin

F Vin


Figure 1.4: A phase locked loop frequency synthesizer.

Physical implementation of the divider within a PLL is easily accomplished using digital circuit techniques so long as N is constrained to be an integer. This restriction sets the resolution of the synthesizer to the value of the reference frequency, so that high frequency resolution requires the choice of a low reference frequency. In order to prevent large spurious noise levels, a low reference frequency must be accompanied by a small PLL bandwidth, which leads to slow dynamics [46]. Thus, there is a very restrictive tradeoff involved in achieving high bandwidth and high resolution in the classical PLL structure, which has prompted research into modifications of this architecture to ease this tradeoff.

The method of fractional-N synthesis was introduced in an effort to improve the resolution vs. bandwidth relationship of the classical PLL structure by removing the restriction that N be an integer [46]. The benefit of this approach is the uncou- pling of the output frequency resolution from the choice of reference frequency — high resolution can be achieved even when a high reference frequency is chosen. Fig- ure 1.5 illustrates this technique, and reveals that noninteger N values are produced by dithering between integer values. Specifically, the carry out bit of an accumulator circuit is used to control the choice of instantaneous divide value, which leads to a periodic dithering pattern. An illustration of typical signals associated with such an approach, as shown in Figure 1.6, reveals that the periodic dithering pattern leads to a periodic phase error pattern of lower frequency than that of the reference frequency.

Suppression of the resulting spurious noise requires that the bandwidth of the PLL be placed well below the frequency of the periodic error pattern, which undermines the effort to obtain a high bandwidth.

As a means toward improving the performance of fractional-N synthesis, Fisher et



PFD Loop

Filter N/N+1

Ref Out






carry out 1-bit n-bits


4 5 4

Out Div Carry Out N

Figure 1.5: The fractional-N synthesizer architecture.

Carry Out Out

Div Ref E phase error

Figure 1.6: Signals associated with fractional-N synthesis with N=4.25.

al. proposed a technique now referred to as phase interpolation [29,30] to increase loop dynamics while maintaining low phase noise and fine frequency resolution. Fisher’s approach made use of a D/A converter to cancel out spurious noise caused by the periodic dithering pattern described above. While high performance can be achieved with this approach, power dissipation is increased since a high speed D/A converter is required.

Rather than canceling out spurious noise with a D/A converter, Riley et al.

in [23, 27] and Miller et al. in [24, 25] described a technique that prevents such noise from being produced by altering the dithering pattern in fractional-N synthesis. Here a connection was made between fractional-N synthesis and Σ-∆ D/A converters, the action of which is illustrated in Figure 1.7. The drawing depicts time and frequency domain views of a Σ-∆ D/A converter that achieves M-bit resolution by dithering a 1-bit D/A with a Σ-∆ modulator and smoothing the two-level sequence with an


analog lowpass filter to produce the desired analog output. High order Σ-∆ modu- lators are known to exhibit low spurious content when an input signal of sufficient activity is used [47]. In addition, an attractive aspect of Σ-∆ modulators is their property of shaping the resulting quantization noise into high frequencies. This last characteristic allows the analog lowpass filter to attenuate much of the quantization noise without affecting the input signal, whose energy is assumed to be confined to low frequencies. Application of this method to fractional-N synthesis is accomplished by simply replacing the digital accumulator with a Σ-∆ modulator.

Digital S-D Modulator

M-bit Input 1-bit

1-bit D/A

Analog Output


Quantization Noise

S-D Digital Input

Spectrum Analog Output

Spectrum Time Domain

Frequency Domain

Figure 1.7: A 1-bit Σ-∆ D/A converter.

1.4 Direct Modulation of a Frequency Synthesizer

Given the PLL structure discussed above, we are now ready to attack the issue of modulation. Phase and/or frequency modulation of a frequency synthesizer is ac- complished by varying its divide value according to input data. A simple method of performing this task is shown in Figure 1.8. Binary input data selects the divide ratio to be either N or N + 1 depending on whether the input is 0 or 1, and N is chosen to achieve the desired carrier frequency. The output frequency settles to Fout = N Fref, so that binary frequency shift keying (FSK) modulation is produced as N is varied.

In the figure, the resulting output spectrum is illustrated under the assumption that Fref = 20 MHz and that N = 90. The carrier frequency is seen to be 1.81 GHz, and the modulation frequency deviation equals Fref.

Unfortunately, the FSK modulation method depicted in Figure 1.8 is not practical for most applications due to its inefficient use of spectrum. The spectral efficiency is greatly improved if a smooth transition is made during frequency transitions and the



frequency resolution = Ref

PFD Loop



Ref Out


Data Out

(20 MHz) (1.8 GHz)

1.80 1.82 GHz 1-bit

Figure 1.8: Direct modulation of a frequency synthesizer.

modulation deviation is optimized. Figure 1.9 illustrates a fractional-N modulator that achieves high spectral efficiency by using a digital transmit filter to obtain smooth transitions in the modulation data, and a digital Σ-∆ modulator to dither the divide value according to the resulting modulation sequence. This architecture was proposed by Riley et al. in [22]. The resulting spectrum is compact, and its overall shape is set by the digital filter assuming that the PLL dynamics have sufficient bandwidth. The digital transmit filter would typically be implemented as an FIR filter, which allows the convolution operation between it and the binary input data to be carried out with a lookup procedure that maps current and previous data samples, along with time information, to the filtered output waveform [22]. Physical implementation of the lookup procedure is accomplished with a ROM whose address lines are controlled by the input data and time information generated by a counter.

A direct analogy between the above fractional-N modulator and Σ-∆ D/A con- verter can be made by deriving a linearized model of the synthesizer dynamics. Fig- ure 1.10 depicts such a model in the frequency domain. The digital transmit filter confines the modulation data to low frequencies, the Σ-∆ modulator adds quantiza- tion noise that is shaped to high frequencies, and the PLL acts as a lowpass filter that passes the input but attenuates the Σ-∆ quantization noise. The output of the lin- earized model corresponds to the instantaneous frequency of the synthesizer, which is considered analog in nature. A key constraint to consider is that the PLL bandwidth must be greater than the transmit filter bandwidth in order to avoid distortion of the modulation signal.

The modulator structure depicted in Figure 1.9 can well be considered the minimal topology necessary for frequency or phase modulation. Its architecture is composed of two core components — a frequency synthesizer and a transmit filter. The synthesizer is necessary in order to produce an RF output waveform that can be accurately set to desired frequencies. The transmit filter is necessary to produce a spectrally efficient modulation signal. Thus, the approach presented by Riley would appear to be the


PFD Loop Filter


Transmit Filter

(20 MHz)Ref (1.8 GHz)

Data Digital S-D

Modulator 1-bit





1.80 GHz


1-bit K-bits

Figure 1.9: A spectrally efficient, fractional-N modulator.


Transmit Filter PLL Dynamics Quantization


Data Fout

Digital S-D Modulator

PFD Loop

Filter N/N+1

Transmit Filter

Ref Out


digital analog

Figure 1.10: Linearized model of fractional-N modulator.

optimal topology to achieve low power operation, high integration, and high spectral efficiency.



1.5 The Challenge of Achieving High Data Rates and Low Noise

There is one significant drawback to Riley’s modulator topology — the modulation bandwidth must be less than the PLL bandwidth. This constraint imposes a severe conflict between achieving high data rates and good noise performance. Figure 1.11 illustrates that high data rates require a wide PLL bandwidth, but low output noise requires a low PLL bandwidth in order to properly attenuate the Σ-∆ quantization noise.


Tran. Fil. PLL

Data Fout

Low noise Low PLL bandwidth

Highdata rate High PLL bandwidth

Figure 1.11: The conflict of high data rate and low noise performance.

How low must the PLL bandwidth be set to achieve the required noise perfor- mance? The answer to this question depends on three parameters:

• The required noise specification,

• The order of the Σ-∆ modulator and PLL transfer function,

• The sample rate of the Σ-∆ (i.e., the value of the Fref).

By increasing the order of the Σ-∆, the noise is further pushed to high frequencies, allowing a wider PLL bandwidth. However, the order of the PLL transfer function must also be increased to achieve acceptable attenuation of the noise at high frequen- cies. The setting of the sample rate of the Σ-∆ provides another handle for achieving the required noise performance — high sample rates distribute the quantization noise over a wide frequency region, therefore allowing a wider PLL bandwidth.

Figure 1.12 displays the required combination of PLL (Σ-∆) order and Σ-∆ sam- ple rate to achieve a variety of data rates where the output phase noise due to Σ-∆


quantization noise is set to -136 dBc/Hz at 5 MHz offset from the carrier. (A But- terworth transfer function is assumed for the PLL, and the relation between PLL bandwidth, fo, and data rate, 1/Td, is assumed to be foTd = 0.7. An explanation for these settings is provided later in the thesis.) This noise specification is chosen to achieve an overall noise specification that is less than -131 dBc/Hz at 5 MHz offset after accounting for the effect of VCO noise.

Increased Digital Power

Increased Analog Power

400 Kbit/s 1 Mbit/s

2 Mbit/s

3 Mbit/s

PLL order


Sample Rate (MHz)

20 40 60 80 100

2 3 4 5

Figure 1.12: Achievable data rates vs. PLL order and Σ-∆ sample rate.

Figure 1.12 reveals that the achievement of high data rates requires high PLL orders and high Σ-∆ sample rates. An increase in PLL order leads to increased power and complexity in the analog section of the PLL in order to realize additional poles and/or zeros, and perform tuning [48] to insure that these poles/zeros are accurately set. Such tuning is particularly critical for PLL orders greater than 2 in order to assure stable PLL dynamics. An increase in Σ-∆ sample rate leads to increased power in the digital section of the modulator since it leads to an increased clock speed for the Σ-∆ and ROM circuitry. Thus, the figure reveals that an increase in data rate leads to increased power levels in the fractional-N modulator.

1.6 Proposed Method

The primary contribution of this thesis is a proposed compensation method that al- lows the data bandwidth to exceed the PLL bandwidth by over an order of magnitude



with little increase in the power dissipation or complexity of the fractional-N modu- lator. As illustrated in Figure 1.13, the increase in data rate is achieved by cascading a digital compensation filter, which is the inverse of the PLL transfer function, with the digital transmit filter. The resulting transfer function seen by the data is flat, which allows the data rate to exceed the PLL bandwidth. The compensation filter can be implemented by simply combining it with the transmit filter and altering the ROM storage values. Noise is not amplifed by using the compensation method since it alters the transmit filter rather than acting on an analog input signal.

Compensated Transmit Filter

Trans. Fil. S-D PLL

Data Fout

Compensation Filter

Overall Dynamics

digital analog

Figure 1.13: Proposed compensation method.

Table 1.1 displays the achievable data rates at different Σ-∆ sample rates using compensation; the noise specification was identical to that used to generate Fig- ure 1.12, and the order was restricted to two for reasons discussed later in the thesis.

Figure 1.14 compares the achievable data rate with compensation at a Σ-∆ sample rate of 20 MHz to the achievable data rates without compensation; we see that com- pensation allows high data rates to be achieved with relatively low complexity and power dissipation. The calculated data rates with compensation are based on the available dynamic range within the implemented PLL, a point that is touched upon below.

Σ-∆ sample rate 20 MHz 40 MHz 80 MHz Max. data rate 3.4 Mbit/s 4.8 Mbit/s 4.9 Mbit/s

Table 1.1

Theoretically achievable data rates using compensation for second order PLL.


With compensation Without compensation

Increased Digital Power

Increased Analog Power

400 Kbit/s 1 Mbit/s

2 Mbit/s 3 Mbit/s

PLL order


Sample Rate (MHz)

20 40 60 80 100

2 3 4 5

3.4 Mbit/s

Figure 1.14: Comparison of achievable data rates with and without compensation vs. PLL order and Σ-∆ sample rate.

1.7 Issues

There are two issues that must be considered when implementing the proposed com- pensation method. The first is that, in practice, mismatch will occur between the compensation filter and PLL dynamics. While the compensation filter is digital and therefore fixed, the PLL dynamics are analog in nature and sensitive to process and temperature variations. Figure 1.15 illustrates that a parasitic pole/zero pair and high frequency gain error occurs when the bandwidth of the PLL is too high. A simi- lar situation occurs when the gain is too low. As will be described later, the parasitic pole/zero pair causes intersymbol interference and modulation deviation error. Thus, it is important to strive for a PLL implementation that has accurate PLL dynamics despite process and temperature changes.

The second issue is that the achievement of high data rates requires a large dy- namic range in the modulation path. As shown in Figure 1.16, the compensated transmit filter amplifies high frequency components in the input data stream. The resulting modulation signal experiences an increased signal swing that must be ac- commodated in the modulation path. To achieve data rates in excess of 1 Mbit/s, the 1-bit pathway into the divider is not sufficient. An increase in this pathway requires the use of multiple-bit output Σ-∆ and a multi-modulus divider that supports a wide



Trans. Fil. 1-bit S-D PLL

Data Fout

Comp. Fil.

Compensated Transmit Filter

Figure 1.15: The effect of mismatch.

range of divide values.

Digital S-D Modulator

PFD Loop

Filter N/N+1

Ref Out


Data Mod

Mod Data Compensated

Transmit Filter

Figure 1.16: High data rate costs dynamic range.

1.8 Implementation Highlights

To show proof of concept of the proposed compensation method, the system depicted in Figure 1.17 was built using a custom, CMOS fractional-N synthesizer that contains several key circuits. Included are an on-chip, continuous-time filter that requires no tuning or external components, a digital MASH Σ-∆ modulator with 6 output bits that achieves low power operation through pipelining, and a 64 modulus divider that


supports any divide value between 32 and 63.5 in half cycle increments. The inclusion of the external divide-by-2 prescaler allows the CMOS divider input to operate at half the VCO frequency, and changes the range of divide values to all integers between 64 and 127.

1.8 - 1.9 GHz

0.6 m CMOS IC

Digital S-D Modulator


20 MHz


64 Modulus Divider



digital data stream Carrier


Figure 1.17: Overall System.

Table 1.2 lists the specifications of the prototype frequency synthesizer IC. The power of the proposed system is roughly half that of a DECT system described by Heinen in [15], which is believed to be representative of the lowest power transmitter architecture available at the present time. It should be noted that the spurious noise was measured without an output bandpass filter on the transmitter. The inclusion of this filter should lower the spurious response to less than -80 dBc.

Power consumption 27 mW Maximum Data Rate 2.85 Mbit/s

Carrier Frequency 1.81 GHz to 1.89 GHz Modulation GFSK

Spurious Noise <−60 dBc

Phase Noise <−131 dBc/Hz at 5 MHz offset Table 1.2

Modulator specifications.

The modulation method chosen for the prototype is Gaussian Frequency Shift Key- ing (GFSK). This method is similar to Gaussian Minimum Shift Keying (GMSK) [49], the difference being that GFSK allows a tolerance on the modulation index, h. (By definition, h is the ratio of the peak-to-peak frequency deviation of the transmitter output to its data rate.) This tolerance is necessary when using the compensation method since mismatch between the compensation filter and PLL dynamics changes



the frequency deviation of the transmitter output. (An explanation of this phe- nomenon is provided in Chapter 6.) The value of h is 0.5 in the case of GMSK, which causes the phase of the transmitter output to increment or decrement by π/2 radians during each data symbol period. In the case of GFSK as used in DECT, h = 0.5± 0.05.

Although the proposed compensation method is applicable to modulation meth- ods other than GFSK, we will restrict our analysis to this case since it provides a benchmark for our results. Specifically, we will strive to meet the performance stan- dards of DECT; our primary goal will be the achievement of a data rate in excess of 1 Mbit/s with a noise spectral density that is less than -131 dBc/Hz at 5 MHz offset.

In the implementation, the 64 modulus divider and 6 output bit Σ-∆ modulator provide a dynamic range for the compensated modulation data that is wide enough to support data rates in excess of 2.5 Mbit/s. The on-chip loop filter allows an accurate PLL transfer function to be achieved by tuning just one PLL parameter — the open loop gain. A brief overview of each of these components will now be presented.

1.8.1 Divider

To achieve a low power design, it is desirable to use an asynchronous divider struc- ture to minimize the amount of circuitry operating at high frequencies. As such, a multi-modulus divider structure was designed that consists of cascaded divide- by-2/3 sections [50]; this architecture is an extension of the common dual-modulus topology [45, 51–53]. Shown in Figure 1.18 for an 8-modulus example, this divider structure allows a wide range of divide values to be achieved by allowing a variable number of input cycles to be ‘swallowed’ per output cycle. Each divide-by-2/3 stage normally divides its input by two in frequency, but will swallow an extra cycle per OUT period when its control input, Di, is set to 1. As shown for the case where all control bits are set to 1, the number of IN cycles swallowed per OUT period is binary weighted according to the stage position. For instance, setting D0 = 1 causes one cycle of IN to be swallowed, while setting D2 = 1 causes 4 cycles of IN to be swallowed. Proper selection of {D2D1D0} allows any integer divide value between 8 and 15 to be achieved.

The 64 modulus divider that was developed for the prototype system uses a similar principle to that discussed above, but has a modified first stage to achieve high speed operation. Specifically, the implemented architecture consists of a high speed divide-by-4/5/6/7 state machine followed by a cascaded chain of divide-by-2/3 state machines as illustrated in Figure 1.19. The divide-by-4/5/6/7 stage accomplishes cycle swallowing by shifting between 4 phases of a divide-by-2 circuit. Each of the 4 phases is staggered by one IN cycle, which allows single cycle pulse swallowing resolution despite the fact that two cascaded divide-by-2 structures are used. This phase shifting approach, which is also advocated in [53], allows a minimal number of components to operate at high frequencies — the first two stages are simply divide-


D2 = 1 D1 = 1 D0 = 1

(1 per OUT period)

2/3 2/3 2/3


D0 D1 D2

Di = 1 Di = 0 2


8 + D0*20 + D1*21 + D2*22 Cycles Swallow cycle

Figure 1.18: An asynchronous, 8-modulus divider topology.

by-2 circuits, not state machines. Also, the fact that control signals are not fed into the first divide-by-2 circuit allow it to be placed off-chip in the prototype.

2 2 FF2 F34 F1 4/5/6/7

4 to 1 MUX

D2 D3 D4 D5




2/3 2/3 2/3

IN 2/3


Figure 1.19: An asynchronous, 64 modulus divider implementation.

1.8.2 Loop Filter

The achievement of accurate PLL dynamics is accomplished in the prototype system with the variable gain loop filter topology depicted in Figure 1.20. Surrounding stages relevant to the loop filter description are included and will now be described. The PFD output is a square wave voltage waveform whose duty cycle varies according to the input modulation data. The shaded region corresponds to the approximate duty cycle span that 2.5 Mbit/s would take up in the prototype. A conversion of the PFD output from voltage to current is made by the charge pump, which yields two complementary current waveforms with modulated duty cycles. These current




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