Unit 11
Latches and Flip-Flops
閂與正反器
Learning Objectives
Explain in words the operation of S-R and gated D latches
Explain in words the operation of D, D-CE, S-R, J-K, and T flip-flops
Make a table and derive the characteristic (next-state) equation for such latches and flip-flops.
State any necessary restrictions on the input signals.
Draw a timing diagram relating the input and output of such latches and flip-flops.
Show how latches and flip-flops can be constructed using gates.
Analyze the operation of a flip-flop that is constructed a
gates and latches.
Unit 11 Latches and Flip-Flops 3
Latches and Flip-Flops
11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch
11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
11.6 J-K Flip-Flop 11.7 T Flip-Flop
11.8 Flip-Flops with additional Inputs
Introduction 簡介
Sequential switching circuits (序向電路):
輸出不只和目前的輸入有關,
亦和過去的輸入序列有關。
feedback(回授):
某一邏輯閘的輸出連接至電路中其他邏輯閘的輸
入,因此形成一個封閉的迴路。
Unit 11 Latches and Flip-Flops 5
Latches and Flip-Flops
11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch
11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
11.6 J-K Flip-Flop 11.7 T Flip-Flop
11.8 Flip-Flops with additional Inputs
Set-Reset Latch
設定-重置閂
如果輸入 S = R =0,(Fig.11-3a)
電路可以假設處於
Q =0且 P =1的穩定狀態,
因為
P
=1回饋到第2個閘強迫輸出Q
=0, 然後
Q
=0回饋到第1個閘讓它的輸出為1。 如果將 S 變成1, (Fig.11-3b)
P
會變成0,
瞬間導致第2個閘的輸入和輸出兩者皆為0,
這是電路的一種非穩定情況或狀態;
因此
Q
會變成1,導致如圖11-3(b)所示的穩定狀態。
Unit 11 Latches and Flip-Flops 7
Set-Reset Latch (Cont’d)
如果 S 變回成0, (Fig.11-4a)
因為
Q =1回饋到第1個閘使得 P 維持在0,
所以電路不會改變狀態。
這時輸入再一次是
S
=R
=0,但是輸出和我們開始推衍時不 同,因此這個電路對同一組輸入而言,具有兩種不同的穩定 狀態。 如果現在將 R 換成1,(Fig.11-4b)
Q
會變成0且P
接著會變回成1。 如果接著將
R
變回成0,則電路會保持在這個狀態,又回到 開始的情況。Set-Reset Latch (Cont’d)
這種電路被稱為具有『記憶』
的能力,
它的輸出不僅和目前的輸入有關,
並且和過去的輸入序列也有關。
如果我們限制輸入的條件,
不允許R = S = 1,
則輸出P 和Q 的穩定狀態永遠互 為補數,亦即
P = Q ′
。Unit 11 Latches and Flip-Flops 9
Set-Reset Latch (Cont’d)
設定-重置( S - R )閂: (不允許 S = R = 1 )
Timing Diagram for S-R Latch
當
S
在時間t
1變成 1 時,
Q 在極短時間(ε)之後變成 1。
ε
代表閂的反應時間或延遲時間。 在時間
t
2時,當S
變回成0,
Q
沒有變化。 在時間
t
3時,R
變成 1,
Q
在極短時間(ε)之後變回成0。
為了讓Q 的狀態能發生改變,
S
(或R
)輸入脈衝的維持時間必須 至少大於ε
。 如果
S
=1 的時間少於ε
,將無法 改變邏輯閘的輸出,所以閂將無法 改變狀態。S
R Q
Q’
Unit 11 Latches and Flip-Flops 11
S-R Latch Operation
Next State characteristic equation (特性方程式)
S
R Q
Q’
Q: current state Q
+: next state
Review Question
【習題11.1】 (page 310):
Assume that the inverter in the given circuit has a propagation delay of 5 ns and the AND gate has a propagation delay of 10 ns.
Draw a timing diagram for the circuit showing X, Y,
and Z. Assume that X is initially 0, Y is initially 1, X
becomes 1 for 80 ns, and then X is 0 again.
Unit 11 Latches and Flip-Flops 13
Review Question
【習題11.2】 (page 310):
A latch can be constructed from an OR gate, an AND gate, and an inverter shown above.
What restriction must be placed on R and H so that P will always equal Q’ (under steady-state conditions)?
Construct a next-state table and derive the characteristic
(next-state) equation for the latch.
Complete the following timing diagram for the latch.
Review Question
【習題11.3】(page 310):
This problem illustrates the improper operation that can occur if both inputs to an S-R latch are 1and are changed back to 0.
For Figure 11-6, complete the following timing chart, assuming that each gate has a propagation delay of exactly 10ns.
Assume that initially
P=1 and Q=0.
Note that when t=100 ns,
S and R are both changed to 0.
Then 10 ns later, both P and Q
will change to 1.
Because these 1’s are fed back to the gate inputs,
what will happen after
another 10 ns?
Unit 11 Latches and Flip-Flops 15
Switch Debouncing with an S-R Latch
S - R 閂的應用:消除開關的彈跳
這種消除彈跳線路需要雙擲開關,能在兩個 接點之間切換。(單擲開關只能在一個接點 和開路之間切換所以無法運作。)
S-R Latch
運用NAND閘形成的 S - R 閂:稱為 S − R 閂 。
Unit 11 Latches and Flip-Flops 17
Latches and Flip-Flops
11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch
11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
11.6 J-K Flip-Flop 11.7 T Flip-Flop
11.8 Flip-Flops with additional Inputs
Gated D Latch
閘控D閂有2個輸入:
一個資料輸入(
D
)和 一個閘控輸入(
G
)。
D
閂可以用S
-R
閂和邏輯閘組成。Unit 11 Latches and Flip-Flops 19
Gated D Latch (Cont’d)
當 G =0時,
S
=R
= 0,所以Q
不會改變。 當 G =1且 D =1時,
S =1且 R =0,
所以
Q
被設成1, Q
輸出的值跟隨著D
輸入的值。 當 G =0時,
Q
輸出保留D
最後的值(沒有狀態變化)。 這種形式的閂也稱為 transparent latch (穿透閂),
因為當
G =1時, Q
輸出和D
輸入相同。 此閂的特性方程式為
Q
+= G ′ Q + GD
Symbol and Truth Table for Gated Latch
閘控D閂的符號與真值表:
Unit 11 Latches and Flip-Flops 21