Turbo-like Decoding Algorithm for Structured LDPC codes
Ajit Nimbalker, Yufei Blankenship and Brian Classon Motorola Labs - Wireless and Solutions Research,
1301 E. Algonquin Road, Rm:2928, Schaumburg, IL 60196 USA
Email: {A.Nimbalker, Yufei.Blankenship, Brian.Classon}@motorola.com
Abstract – This paper presents a high-speed “turbo- like” decoding algorithm for certain structured LDPC codes such as those adopted in IEEE 802.16e and in the draft 802.11n standards. It is shown that after a key modification, such LDPC codes may be processed as Generalized Repeat Accumulate codes, codes which are known to support “turbo-like” decoding. A GRA-like encoder of structured LDPC codes is derived, which in turn leads to the decoding algorithm. It is also shown that the “structured” properties result in an inherent parallelism, leading to an efficient high speed decoder implementation.
I. INTRODUCTION
Low-density parity-check (LDPC) codes [1] are powerful error-correcting codes that are appearing in standards such as IEEE 802.16e [2] and 802.11n, Digital Video Broad- cast, etc. Extensive research in recent years has focused on exploring the theoretical performance of LDPC codes, and on the design of practical encoding/decoding techniques.
LDPC codes are usually decoded via iterative message passing algorithms such as the standard belief propagation (SBP) or the layered BP (LBP) [3]. Although LDPC codes may be viewed as general codes on graphs, additional matrix properties may allow more specific encod- ing/decoding algorithms. For instance, the class of LDPC codes known as Generalized Repeat Accumulate codes (GRA) allows linear time encoding [4].
By definition, a GRA code is a serial concatenation of several component codes, such as repetition codes, single- parity-check (SPC) codes, and Accumulator (ACC).
Therefore, such LDPC codes support both LDPC-like and
“turbo-like” decoding algorithms [5]. In general, the par- ity-check matrix of GRA codes has a full dual-diagonal parity-check portion including a weight-1 parity column.
However, the weight-1 column (when used in structured LDPC codes) leads to a performance loss and hence, matrices with partial dual-diagonal parity-check portion are often preferred in practice, e.g., in IEEE802.16e and 802.11n. These LDPC codes are still easily encodable [6], but it is not clear if such codes still support the “turbo- like” decoding algorithms [5].
This paper describes a method that allows turbo-like de- coding of structured LDPC codes. These LDPC codes [7]
have parity check matrices (H) that comprise of all-zero or shifted identity submatrices, and they also have a partial dual-diagonal parity portion. An interpretation that allows a parallelized “turbo-like” decoding (TLD) algorithm of such LDPC codes is presented. TLD can reuse technolo- gies developed for turbo decoders such as log-MAP proc- essors, fixed point analysis, and parallelization techniques, and it can potentially combine the features of LDPC and turbo decoders to achieve high throughput and good per- formance.
II. BACKGROUND
An LDPC code is specified by a sparse parity-check ma- trix H, with , where “T” denotes matrix trans- pose, 0 is a zero vector. The codeword is x=[s p]=[s0, s1,
…, sk-1, p0, p1, …, pm-1], where p0, . . , pm-1are the parity- check bits; and s0, . ., sk-1 are the systematic bits. An H matrix of an LDPC code is often described by a bipartite graph which also provides a framework for deriving (and visualizing) iterative message passing algorithms. Each 1 in H defines an edge (i.e., a connection between a variable node and a check node) in the bipartite graph, each column in H corresponds to a variable node and each row in H corresponds to a check node.
T
T 0
Hx
For example, let an n = 12, rate-1/2 code be defined by
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with the left side portion corresponding to k (=6) informa- tion bits s, the right side portion corresponding to m (=6) parity-check bits p. By definition, the H in (1) defines six parity-check equations shown in (2). Since H is full-rank, and the systematic bits (i.e.,x0 through x5) are known, the six equations can be solved to obtain the six unknown parity-check bits ([x6, x7, …, x11]), thus providing the codeword after systematic encoding.
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From a decoding perspective, turbo-like decoding of an LDPC code is easiest when the entire parity-check portion of the H matrix is dual-diagonal as shown in (3). In such a case, all the parity-check bits are obtained by a repeat- accumulate structure and this serial concatenation leads to the “turbo-like” decoding algorithm.
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However, the matrix in (1) is only partial dual-diagonal (since the first column of Hp is different from the first column in (3)), and it is not clear how to handle LDPC codes of (1) with a GRA-like structure. The following sections show how to modify GRA-like algorithms [5] to handle LDPC codes with partial dual diagonal parity- check portion.
III. A GRA-LIKE ENCODER
This paper illustrates the key ideas using the H matrix in (1), and they can be readily extended to other LDPC codes with a partial dual-diagonal parity portion. Consider- ing a systematic encoding, the six equations of (2) can be solved to obtain the parity bits in two steps as follows:
i).The systematic portion of the codeword is used to com- pute the parity bit corresponding to the non-dual- diagonal portion of Hp, which is the first parity bit x6 for (1). Simply adding all the parity-check equations in (2) cancels all unknown variables except x6.
ii).The parity bits corresponding to the partial dual- diagonal portion, which are (x7,x8, x9, x10,x11) for (1), are obtained through successive back-substitution (i.e., ac- cumulation) using the parity-check equations in (2).
The rest of the paper considers Step ii), which is a GRA- like structure, leading to the proposed decoding algorithm.
First the input bits [x0, x1, x2, x3, x4, x5, x6] (including a computed parity bit x6) are repeated according to the number of times each bit appears on the right-hand-side (RHS) of (2). The output of the repetition code is rear-
ranged via an interleaver so that the bits can be grouped in the order they appear on the RHS of (2). The RHS of (2) represents SPC codes, whose outputs are accumulated (i.e., the back substitution on the LHS of (2)) using an ACC. The ACC begins and ends in zero-state, and its last output of the ACC is always 0 (thus not transmitted), because the sum of the LHS (and RHS) of (2) is zero.
Figure 1. A GRA-like encoder of H matrices with a partial dual- diagonal parity portion. The input consists of the information bits and one parity bit (x0 through x6). Vector Q contains the repetition factors, and vector J contains the SPC parameters.
While all parity bits are computed using GRA structure in [5], the new method pre-computes the parity bit of the non-dual-diagonal portion (parity bit x6) in a non-GRA fashion, before applying a GRA-like encoder to compute the remaining parity bits. A block diagram of a GRA-like encoder for the H of (1) is shown in Figure 1. The GRA- like encoder may be interpreted as follows (using the notation of [5]).
The input [x0, x1, x2, x3, x4, x5, x6] passes through a repeti- tion code with a repetition factor Q = [Q0, Q1, Q2, Q3, Q4, Q5, Q6], where input bit xi is repeated Qitimes. The P/S indicates the bits generated in parallel are converted to serial. An interleaver permutes the output of repetition code before the SPC encoder according to a permutation ȡ.
The SPC code outputs one bit for every Ji serialized input bits (Ji [J0, J1, J2, J3, J4, J5]). The S/P indicates that Jibits are input to the SPC to obtain a temporary bit ui, where ui
is equal to the RHS of ith equation in (2). The ui’s are accumulated to obtain remaining unknown parity-check bits.
The exact parameters of the GRA-like encoder may be obtained by partitioning H into two parts, H = [HGRA Hp2], as shown in (4), where Hp2 is the partial dual-diagona parity portion. Note that the columns of HGRAcorrespond to the systematic bits and one parity bit.
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Parameter Qi is equal to the number of ones in ith column of HGRA, i = 0, 1,…, k. Parameter Ji is equal to the number
of ones in the ith row of HGRA, i = 0, 1,…, m-1. The inter- leaver (ȡ) length W is equal to the number of ones in HGRA. By definition, the ith input bit is permuted to the ȡ(i)th position in the output as a result of the permutation (ȡ), which is obtained as follows. Label the ones (i.e., edges) in HGRA in a column-wise order starting with the left-most column as shown in the left hand side of (5). These indices sequentially number the edges after repetition and before interleaving. Label the ones in HGRA in a row-wise order from the top-most row as shown on the right hand side of (5). These indices sequentially number the edges after interleaving, before being input to the SPC. The permuta- tion (ȡ) is given by reading the row-wise label in column- wise order.
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(5)
For the (12,6) code of (1), the parameters are Q = [2 2 2 2 2 2 3], J = [3 2 3 2 2 3], and the interleaver is ȡ = [0 8 3 10 1 5 9 12 4 11 6 13 2 7 14], with W=15.
IV. A TURBO-LIKE DECODER
The GRA-like encoder described in the previous section is used to derive a corresponding “turbo-like” decoder whose graphical model with corresponding GRA-parameters is shown in Figure 2. Solid circles indicate repetition nodes (variable nodes corresponding to non-dual diagonal parity portion), the solid squares represent the SPC nodes (or the check nodes) and empty circles represent the variable nodes corresponding to the dual-diagonal parity portion.
The non-dual-diagonal parity bit is highlighted to show that it can be treated as a systematic bit during decoding.
A TLD for LDPC codes consists of two component decod- ers - a repetition decoder which is similar to the variable node update in conventional LDPC decoders, and a com- bined SPC-ACC decoder (below the interleaver in Figure 2). The SPC-ACC concatenation is equivalent to a 2-state state convolutional code with irregular puncturing (with periods given by vector J). Therefore, a trellis-based SPC- ACC decoder can be used as a constituent decoder of a
“turbo-like” decoder. Note that as the values of Ji in- creases, there is increased puncturing in the trellis and hence the resulting SPC-ACC decoder (and the overall TLD) becomes weaker. This property of TLD is further discussed in Section VI.
An iteration of TLD consists of the repetition decoding followed by SPC-ACC decoding (see [5] for trellis update equations). From a graph perspective, the two decoders iteratively exchange extrinsic LLRs related to the edges of
HGRA via the (de)interleaver. Therefore, the extrinsic message memory is proportional to the number of 1’s in HGRA which is the interleaver size W. The proposed TLD algorithm updates all edges connected to the systematic bits and one parity bit while the GRA decoder of [5] only updates the edges connected to the systematic bits.
The SPC-ACC processing in TLD is similar yet different from the “check node update” (CNU) in LDPC literature.
In TLD, several parity-check equations are linked directly through the ACC. This allows the check nodes to send messages to each other directly during the SPC-ACC decoding. In contrast, in a SBP decoder, parity-check equations do not interact with each other directly.
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y7 y8 y9 y10 y11
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Figure 2. A graphical model of a turbo-like decoder of an LDPC code with a partial dual-diagonal parity portion.
V. STRUCTURED LDPC CODES
Structured LDPC codes are constructed with all-zero submatrix and shifted identity submatrices as building blocks [7]. This enables block-wise or vectorized encoding and decoding which leads to efficient hardware de- signs [2]. In addition, such codes can also be designed to have a block-wise partial dual-diagonal parity portion, (e.g., in IEEE 802.16e, 802.11n) for easy encoding. This section extends the TLD algorithm of previous sections to structured LDPC codes by deriving an equivalent GRA- like encoder. In particular, the resulting TLD is shown to be highly parallelizable because of the contention-free memory access property of the GRA-like interleaver [8].
A structured LDPC code design starts with a small mbunb
base matrix Hb, makes z copies of Hb, and interconnects the z copies to form a large MuN binary H matrix, where M= mbuz, N= nbuz. The binary H matrix is obtained by replacing each 1 in Hb by a zuz shifted identity matrix (P), and each 0 in Hb by a zuz all-zero matrix. Hence, the H matrix can also be described by an mbunb model matrix Hbm, which is obtained by replacing each 0 in Hb by “–1”
(to denote a zuz all-zero matrix), and by replacing each hi,j=1 in Hb by a shift size p(i,j) to denote a zuz identity matrix whose columns are cyclically shifted by p(i,j).
For example, the matrix in (1) may be used as a base matrix Hb to build a model matrixHbmin (6). When z=3, Hbm is converted to a (6uz)u(12uz) binary matrix H by
replacing each –1 with a 3u3 all-zero matrix and each i with Pi, i=0, 1, 2, where Pi is a 3u3 identity matrix whose columns are cyclically shifted to the right by i positions.
The resulting H matrix has a codeword size N=12u3=36, and an information block size K=6u3=18.
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It was shown earlier that base matrix Hb of (1) can be encoded and decoded using GRA-like structure. If such a base matrix is used to create an H matrix by expansion (e.g., as in (6)), then the resulting H matrix also has a GRA-like encoder which bears many similarity to that of the base matrix Hb.
Let S = [S0,S1,…,Sk-1] and X = [X0, X1,…,Xn-1] represent the information block and the codeword block, respec- tively, where each element is a z-bit vector (i.e., size zu1).
The blockwise encoding may be done as follows.
i). Fill the systematic portion of codeword with a direct copy of the information bits [S0, S1,…, Sk-1], i.e., X0=S0, X1=S1, X2=S2,…,Xk-1=Sk-1.
ii). Compute the parity block (Xk) related to the non-dual- diagonal parity portion (i.e., by solving the corre- sponding parity-check equations).
iii). Compute the parity blocks related to the partial dual- diagonal parity portion (Xk+1,…,Xn-1) using a struc- tured GRA-like encoder (block-wise accumulation).
Note that the third step is similar to GRA-like encoding at a blockwise level, which can be divided in z equivalent bitwise counterparts. As illustrated in Figure 3, the encoder consists of z copies of the GRA-like encoder of the base matrix Hb interconnected by a vector interleaver. The figure assumes that each group of z bits is represented by a column vector.
The main advantage of using a structured LDPC is evident from Figure 3 : highly parallelizable encoding/decoding operations. Note also that the parameters Qb, and Jb of all z copies of structured GRA-like encoder are identical to that of the base matrix. The vector interleaver consists of two stages: i) a permutation (ȡ) of the extrinsic LLR vectors that is the same as the base matrix permutation, and ii) a set of shift sizes (Rbm) corresponding to rotation within each extrinsic LLR vector which depends on the model matrix. Referring to Figure 3, the two stages of permuta-
tions correspond to column permutations and column rotations, respectively.
Figure 3. A GRA-like encoder of a structured LDPC code.
For the (36, 18) code of (6), the GRA parameters are identical to those of the base matrix Hb of (1):Qb = [2 2 2 2 2 2 3], Jb = [3 2 3 2 2 3], the permutation is ȡ = [0 8 3 10 1 5 9 12 4 11 6 13 2 7 14].
The only new parameter required to describe structured GRA-like encoder are the shift values Rbm, which are obtained from the model matrix of (6) by reading the shift sizes in a columnwise order starting from the left hand side of the Hbm,GRA shown in (7) . This leads to a set of shift sizes given by Rbm=[1 2 2 1 0 1 1 0 0 0 2 1 0 2 0].
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(7)
The TLD of structured LDPC codes can also be performed in a structured (or parallelized) manner, analogous to the structured encoding. The parallelized turbo-like decoder consists of z identical copies of repetition and SPC-ACC decoders that are interconnected through the vector inter- leaver (z copies of Figure 2). The received LLR values are suitably distributed to the appropriate decoders alike Figure 2.
High speed TLD is achieved by using several (up to z) processors operating in parallel. The LLRs are stored in multiple memories to allow several concurrent read/write operations. In the iterative process, the extrinsic LLRs are exchanged between the processors (through memory operations) according to the vector interleaver.
The vector interleaver of structured LDPC codes can be described as a contention-free (CF) inter-window shuffle (IWS) interleaver [8]. CF interleaving is important for maximizing decoder throughput as it ensures that concur- rent read/write operations for the z processors do not result in any memory access contentions, thereby minimizing (de)interleaving latency in the iterative decoding.
The interleaver of a structured LDPC code may be inter- preted as a CF interleaver by making the following obser- vation about the two stages of the permutation. The cyclic shift of individual vectors (i.e., column rotation) as speci- fied by Rbm is equivalent to the inter-window shuffle pattern, while the permutation among the vectors (i.e., column permutation) as specified by ȡ is equivalent to the intra-window permutation described in [8].
In general, the CF interleaver can be described as
S
i U
imodW
WM¬iW¼
imodW
, (8) where vector ȡ defines the intra-window shuffling, ij(i) defines inter-window shuffling for the ith index of the window. For the structured TLD decoder, the window size is W which is the length of the base matrix interleaver ȡ, and ij(i) is the cyclic shifted index vector with shift size Rbm(i). For the (36, 12) code of (6), if Rbm(i) = 2, ij(i) = (2, 3, …, z-1, 0, 1). Mathematically, the inter-window shuffle pattern can be expressed as follows,
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In the next section, performance results for TLD and SBP are shown using IEEE 802.16e LDPC codes.
VI. PERFORMANCE
Structured LDPC codes from the IEEE 802.16e are chosen to compare the proposed algorithm with SBP decoding. In the IEEE 802.16e standard, the model matrices of all the code rates (1/2, 2/3, 3/4, 5/6) have 24 columns, while the number of rows is a function of the code rate. Different codeword sizes are obtained by suitably choosing an expansion factor z. For example, the rate-1/2 code has a 12u24 base matrix, and with an expansion factor of z=24, it results in a 576-bit codeword.
The 20th iteration FER performance of the IEEE 802.16e LDPC codes with rates-1/2, 2/3 and 3/4, and an expansion factor z=96 (N=2304-bit codeword) is shown in Figure 4 for a BPSK-modulated AWGN channel. The complexity of the SBP and TLD algorithms per iteration is assumed to be similar as the number of equivalent check node updates is the same. Figure 4 indicates that TLD outperforms SBP when the LDPC code has a substantial dual-diagonal parity portion, i.e., at lower code rates.
As the rate increases (e.g., from rate-1/2 to 2/3 or 3/4), the number of dual-diagonal parity columns decreases, and each ACC trellis of the TLD now connects fewer check equations together. This can also be interpreted as in- creased puncturing in the SPC-ACC trellis, and therefore the performance advantage of TLD performance over SBP is reduced as the rate increases.
1 1.5 2 2.5 3 3.5
10Ŧ4 10Ŧ3 10Ŧ2 10Ŧ1 100
Eb/N0 (dB)
FER
IEEE 802.16e, code size=2304, AWGN, QPSK BP, 50 iter BP, 20 iter turbo, 20 iter
RateŦ1/2
RateŦ2/3A
RateŦ3/4A
Figure 4. IEEE 802.16e LDPC codes, N = 2304 (with z=96), R = 1/2, 2/3 and 3/4 with flooding schedule for both standard BP and
“turbo-like” decoding. For rate-2/3 and 3/4, the codes designated as 2/3A and 3/4A were simulated.
VII. CONCLUSIONS
In this paper, a turbo-like decoding (TLD) algorithm is proposed for structured LDPC codes with partial dual- diagonal parity portion. The encoding and turbo-like decoding algorithm is described for such LDPC codes by deriving a GRA-like structure. It is demonstrated that structured LDPC codes facilitate high speed TLD due to the contention-free property of its interleaver. The per- formance of the TLD algorithm is compared with standard belief propagation using IEEE 802.16e LDPC codes. It is noted that the proposed algorithm successfully applies the turbo decoding concepts to the decoding of LDPC codes and has the potential of achieving better complex- ity/performance tradeoffs.
VIII. REFERENCES
[1] R. G. Gallager, “Low density parity check codes,” IRE Trans. Inform. Theory, IT-8, pp. 21-28, Jan. 1962.
[2] IEEE Std 802.16e-2005, approved Dec 2005, pub. Feb 2006.
[3] M. Mansour, N. Shanbag, “High-throughput LDPC decod- ers”, IEEE Trans. on VLSI, vol. 11, pp. 976-996, Dec. 2003.
[4] H. Jin, A. Khandekar, and R. McEliece, “Irregular Repeat- Accumulate Codes,” in Proc. 2nd Int. Symp. Turbo Codes and Rel. Topics, Brest, pp. 1-8, Sep. 2000.
[5] K. M. Chugg, P. Thiennviboon, G. D. Dimou, P. Gray, and J. Melzer, “A new class of turbo-like codes with universally good performance and high-speed decoding”, MILCOM, 2005.
[6] T. Richardson and R. Urbanke, “Efficient encoding of low- density parity-check codes,” IEEE Trans. Inform. Theory, vol. 47, pp. 638-656, Feb. 2001.
[7] D. Sridhara, T. Fuja, and R. M. Tanner, “Low density parity check codes from permutation matrices”, Conf. on Inform.
Sciences and Sys., John Hopkins University, Mar. 2001.
[8] A. Nimbalker, T. K. Blankenship, B. Classon, T. Fuja, and D. J. Costello, Jr, “Inter-window shuffle interleavers for high throughput turbo decoding”, in 3rd Int. Symp. On Turbo Codes and Rel. Topics, Brest, pp. 355-358, Sep. 2003.
