922 25300 Computer Organization and Assembly Languages National Taiwan University
Fall 2007 Department of CSIE
Homework 1
October 8, 2007 Due date: October 22, 2007
• Signed integers are represented using two’s complement representation.
• Please use the following notations for logic gates. Feel free to change the orientations of the gates and the positions of inputs and outputs. You are free to use other circuits. However, if they are not introduced in the class, you have to implement them before using them.
NOT gate AND gate OR gate NAND gate XOR gate
1. (10%) What are the 8-bit binary representations of the following signed decimal integers? Convert them into hexadecimal.
a. 51 b. -5
2. (10%) Prove that (a){NOT, OR} and (b) {NAND} are universal.
3. (10%) (a) Create the truth table for the 3-input Boolean function, Even, which returns 1 if the number of zeros in inputs is even, 0 otherwise. (b) Implement this function with logic gates AND, OR and NOT.
4. (20%) Follow the conventions in the following figure. Design a 7-segment display driver which accepts a 4-bit input (ABCD where A is the MSB) and outputs 7 bits which controls the on/off status of a 7-segment display as shown in the above figure. (a) List the truth table for the driver. (b) Write down the Boolean expressions for segments a and e.
(a) 7-segment display driver (b) names of segments (c) Configurations for 16 hexadecimal digits
5. (15%) As shown in the following diagram, design a 4-bit comparator which has two 4-bit unsigned integer inputs, X3X2X1X0and Y3Y2Y1Y0, and a 3-bit output for the conditions of X > Y , X = Y and X < Y , respectively. Hint: design a 1-bit comparator first.
4-bit comparator
X Y
4 4
X>Y X=Y X<Y
X>Y X=Y X<Y
1
6. (20%) Design a binary multiplier that multiplies two 3-bit unsigned integers, X = X2X1X0 and Y = Y2Y1Y0, and a 6-bit output Z = Z5Z4. . . Z0and Z = X × Y , where X0, Y0and Z0are LSBs. You may use the notation X[n..m] to identify a portion of wires. For example, X[2..1] means the set of wires, X2X1. 7. (15%) Refer to the following figure for TOY architecture. Please specify the operations of M U XA, M U XB, M U XC, M U XD, M U XE, REGW, M EMW and ALUOP during the execution stage for the instructions ”load address”, ”store indirect” and ”branch zero”. For example, the answer for ”jump and link” would be M U XA = 0, M U XB = ∗, M U XC = ∗, M U XD = 1, M U XE = 01, REGW = 1, M EMW = 0, ALUOP = ∗.
1 2
1 2
1 2
1 2 11
12 21
MUXA
MUXB
MUXC
MUXD MUXE
000 add/sub 001 and 010 xor 011 shift 100 input 2
ALUOP
MEMW
REGW
2
