An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder
CHIA-YULIN, CHAO-YUANYU,ANDMONG-KAIKU Department of Computer Science and Information Engineering
National Taiwan University, Taipei, Taiwan 106, ROC Email: {f93084, r95162, mku}@csie.ntu.edu.tw Abstract— In this paper, a FPGA implementation of IEEE 802.16e
LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.
Index Terms — LDPC codes, dual-diagonal, encoding.
I. INTRODUCTION
Low Density Parity Check (LDPC) codes proposed by Gallager in 1962 [1] have attracted much attention in the last decade due to their capacity-approaching error correcting performance [2]. One drawback of LDPC codes is their high encoding complexity. In order to reduce encoding complexity, LDPC codes with dual diagonal structure is adopted by the latest next-generation wireless LAN standard, IEEE 802.11n [3]
and wireless metropolitan area network (MAN) standard, IEEE 802.16e (WiMAX). This class of codes can be encoded in near- linear time by the method proposed in [4] and in linear time by the sequential method in [5]. A nother efficient encoding scheme [6][7] for dual-diagonal LDPC codes is based on arbitrary bit generation and correction. This approach achieves low encoding complexity and reduces the number of required cycles for encoding each codeword. The matrix structure is exploited in the encoding process to correct the parity bits.
However, their approach can not be directly applied to encode IEEE 802.11n or 802.16e LDPC codes. For this reason the scheme [6] modified the matrix structure. But, this modification causes performance degradation and higher error floors compared to the original 802.11n dual-diagonal codes.
In this paper we apply the scheme[8] that can encode IEEE 802.11n and 802.16e dual-diagonal LDPC codes without any matrix modification. The proposed encoder is implemented on FPGA to show the throughput improvement. And this encoder support code lengths from 576 to 2304 and four different code rates which are 1/2, 2/3A, 3/4A, and 5/6. The remainder of this paper is organized as follows. Section II introduces dual- diagonal LDPC codes. Section III presents the prediction and correction based encoding algorithm that we used in our encoder design. In section IV, the encoder architecture is described.
Section V shows the hardware implementation results and section VI concludes this paper.
II. ENCODING OF DUAL-DIAGONAL LDPC CODES A. Matrix Structure Of DUAL-DIAGONALLDPC CODES
The dual-diagonal parity check matrix H of size m
n in IEEE 802.16e is defined as0,0 0,1 0,2 0, 1
1,0 1,1 1,2 1, 1
s p 2,0 2,1 2,2 2, 1
1,0 1,1 1,2 1, 1
P P P P
P P P P
H= (H ) | (H ) = P P P P
P P P P
b b
b
b b b b b
n n
m k m m n
m m m m n
(1)
where Hs corresponds to the information bits and Hp corresponds to the parity bits. Pi,j is either a circulant permutation matrix or a zero matrix of size z. A circulant permutation matrix is formed by circularly shifting the rows of an identity matrix of size z to the right by several locations. The matrix H is expanded from a base matrix Hb
s p
b b b
H = (H ) | (H )
b b b b
mk mm
(2)
where mb = m/z and kb = k/z. Each element in Hb is a nonnegative number or -1 to represent the shift quantity of the corresponding permutation matrix or a zero matrix. The structure of Hbpis further defined as
bp 1 ( 1)
0 0 0
0 H = (t) | ( h ) 0
0 0 0
0
b b b
m m m
d
d
(3)
where t is a weight-3 column and h is a dual-diagonal structure (Note that d is a positive number and all blank entries are elements of -1). By exploiting this structure, the codeword can be encoded recursively in linear time and the encoder complexity can be reduced significantly. However, the data dependency in the process increases the number of clock cycles needed to encode a codeword.
The supported block lengths ( n) in IEEE 802.16e are ranged from 576 to 2304 with z = 24 to 96. The supported code rates in both standards are 1/2, 2/3, 3/4, and 5/6. Fig. 1 shows an example code in 802.16e with rate 1/2, n = 2304, and z = 96.
- 94 73 - - - - - 55 83 - - 7 0 - - - - - - - - - - - 27 - - - 22 79 9 - - - 12 - 0 0 - - - - - - - - - - - - 24 22 81 - 33 - - - 0 - - 0 0 - - - - - - - - 61 - 47 - - - - - 65 25 - - - - - 0 0 - - - - - - - - - 39 - - - 84 - - 41 72 - - - - - 0 0 - - - - - - - - - - 46 40 - 82 - - - 79 0 - - - - 0 0 - - - - - - - 95 53 - - - - - 14 18 - - - - - - - 0 0 - - - - - 11 73 - - - 2 - - 47 - - - - - - - - - 0 0 - - - 12 - - - 83 24 - 43 - - - 51 - - - - - - - - 0 0 - - - - - - - 94 - 59 - - 70 72 - - - - - - - - - 0 0 - - - 7 65 - - - - 39 49 - - - - - - - - - - - - 0 0
43 - - - - 66 - 41 - - - 26 7 - - - - - - - - - - 0
Fig. 1. Base matrix of rate 1/2 and n = 2304 IEEE 802.16e LDPC code.
B. Encoding Concept
For easy explaining the encoding algorithm we used , we denote s = [a0a1 … ak-1] as the information block and si= [aiz
aiz +1… a(i+1)z- 1] for i = 0, 1, … , kb-1 as the information subblock.
Also, p = [b0 b1 … bm-1] is the parity block and pi= [biz biz+1… b(i+1)z-1] for i = 0, 1, … , mb-1 is the parity subblock. The prediction vector pi’ = [b’izb’iz +1… b’(i+1)z-1] is denoted as the predicted solution of pi. x is the row index of the nonnegative entry in the middle of the weight-3 column in Hbp. Note that all operations discussed in the following are modulo -2 operations.
By definition, a valid codeword c = [s|p] must satisfy the following equation
ts p
Hct(H )m k| (H )m m s | p 0. (4) Replacing Hsand Hp by the dual-diagonal matrix definition in section II, we get
t t
0 1
t t
t 1
1 2
0, 0
t 1
1,
0 t t
-1
t t t
0 +1
t t
+1 +2
t t
t 1
2 1
1, 0
t t
0 1
(p ) p
p p
P s P s
p p
p p p 0
p p
p p
P s
(p ) p
b
b
b
b b
b
b d k
j j j k
j j j
x x
x x
x x
k
k k
m j j
j
d k
(5)
where (p0)dis p0with d-position circularly shifting to the left.
Sum all rows in (6), we can obtain
1
0 0
p mb i
i
(6)where t 1 , t
0 P s
kb
i j i j j
. For sequential encoding, p0 must be calculated first by a series of shifting and accumulation in (6).Then p1 to pmb -1 can be obtained by forward or backward substitution through the equations in (5). Due to the data dependency among the parity subblocks, the calculation of p0
and the derivation of p1to pmb-1can not be done in parallel.
In the scheme [8], instead of calculating p0first, we set p0as an arbitrary vector p0’ and immediately calculate the prediction vectors pi’s. p1’ and pmb- 1’ can be obtained by p '1 0 (p ')0 d
and p -1' -1 (p ' )0
b b
m m d respectively. Then the other prediction vectors pi’s are obtained by forward substitution
-1 -1
p 'i i p 'i (7)
for i = 2, 3, … , x and backward substitution
p 'i i pi1'. (8) for i = mb-2, mb-3, … , x+1. After backward substitution, an additional operation py x px1'is needed and py will be used in the following computation. It is known there exists a relationship that(p )0 d(p ')0 d pi p 'i for i = 1, 2, … , mb-1.
We define the correction vector f as
0 0 0 0
f (p )d(p ')d (p p ')d. (9)
f is unknown right now because p0is not available. However, It is known that
1 1 1
pxpx(px f) (px f) p ' px x'. (10) Hence from the x-th equation in (6), we can calculate p0by
0 1 1
p x px px x p ' px x' p ' px y. (1 1)
Then f can be obtained by (10). If we set p0’ as a zero vector at first, then f is just (p0)d, the shifted version of p0. Finally, the other parity subblocks can be obtained by
pi p ' fi . (13)
The detail of the encoding procedure is described in [8].
III. PROPOSED FLEXIBLE ENCODER ARCHITECTURE A. Combined multiple rate & multiple code length encoder
It is straight forward to implement a multiple code rate &
multiple code length encoder by putting these encoders with different rates & lengths together. Table II shows the comparison of synthesis results between individual encoders and the combined encoder at the code length 576 on Xilinx FPGA environment. From Table II, we see that the design combining four individual encoders proposed in [8] doesn’t save much area, and the clock rate is much slower than individual encoders with single code rate.
TABLE II
SYNTHESISRESULTSONXILINXFPGAAT CODE LENGTH576
Slice FFs LUTs CLK
(MHz)
Total gate count Original 1/2 1,414 1,124 2,500 96.555 23,129 Original 2/3 1,774 1,168 3,066 123.348 21,854 Original 3/4 2,326 1,313 4,077 133.15 21,481 Original 5/6 3,058 1,553 5,325 127.698 33,231
Combine 4 Rates
5,840 2,235 11,338 71.612 97,359
B. Proposed Flexible Encoder Architecture
The proposed encoder architecture with multiple code rates (1/2, 2/3, 3/4, and 5/6) and code lengths (576 to 2304) is shown in Fig. 3. We change the processing order of the parity check matrix used in [8] from row-by-row to column-by-column.
There are two reasons for this idea. First, for serial -input architectures, Kb clock cycles are needed to input the information block if one subblock takes one cycle. Row-by-row processing used in the schemes [8][9] can not start until the whole information block is input. However column -by-column processing can utilize these clock cycles. Second, we found that the area size of the design is related to the number of the barrel shifters. Using this idea can reduce lots number of the barrel shifters.
To support multiple code rates, it’s necessary to setup the number of barrel shifter to maximum. There are 36 barrel shifters needed for parsing the matrix row by row. In the proposed column -by-column design, there are only 6 barrel shifters needed. Table III show s the comparison between encoders parsing in different direction. The implementation environment is on Virtex-4 XC4VSX35 FPGA device and synthesized with Xilinx ISE.
TABLE III
SYNTHESISRESULTSONXILINX AT CODE LENGTH576
Slice FFs LUTs total
(1/2+2/3+3/4+5/6)
8572 5158 14968
Row parsing 5840 2235 11,338 Column parsing 2338 1204 4479
In our architecture shown in Fig. 3
matrix_5 store only the shift quantity of each nonzero circulant permutation matrix in Hs, hence it can get shift values immediately and reduce the Rom size and barrel
be idle due to the existence of zero submatrices in
In order to reduce the area for saving shift values, we had tried to use one matrix with the shift values for the code length 2304 to replace the matrix_1 to matrix_5. After that, using a component to receive the shift values from matrix and then calculate the correct shift values. Table IV shows the comparison between these two implementations.
TABLE IV
TWO TYPE OF MATRIX IMPLEMENT RESULT WITH MULTIPLE RATE AND LE ONXILINX
Slice FFs LUTs
One matrix + calculate IP
14,860 7,182 25,706 131.105
Using 5 matrix
13,803 4,026 25,659 178.591
We can find that the area didn ’t become smaller and the clock rate decrease because of the additional logic computation.
So, we use five matrices to save the shift values.
Fig. 3. Proposed encoder architecture.
Based on the algorithm in scheme [8]
architecture is partitioned into six phases shown in Fig. 3 initial prediction vector p0’ is set to zero to simplify the hardware. In the first two steps, the matrix_1 to matrix_5 select shift values according to the type of code rate. Then the mux choose the right shift values received from matrices by the type of code length. In the third to fifth phase
computed after barrel shifter and accumulator. In the step five, the prediction parity vectors pi are derived after the forward /backward derivation. In the last stage,
vector can be obtained by circularly shifting the sum of p0’ to the left by d positions . Then the prediction are corrected by the correction vector via XOR gates correct parity bits.
By the definition in [9], CPC represents the
of clock cycles required for encoding per codeword. The CPC of the proposed encoder is explained as follows. I
phase, parse one column in Hs in a cycle,
CLK (MHz)
Total gate count 133.15
(Fasted)
99,695
71.612 97,359 145.001 28,539
shown in Fig. 3 , the matrix_1 to store only the shift quantity of each nonzero circulant
, hence it can get shift values barrel shifters will not to the existence of zero submatrices in Hs.
In order to reduce the area for saving shift values, we had tried to use one matrix with the shift values for the code length 2304 to replace the matrix_1 to matrix_5. After that, using a shift values from matrix and then calculate the correct shift values. Table IV shows the comparison between these two implementations.
MULTIPLE RATE AND LE NGTH
CLK (MHz)
Total gate count 131.105 248,531
178.591 211,897
t become smaller and the clock rate decrease because of the additional logic computation.
use five matrices to save the shift values.
in scheme [8], the encoder shown in Fig. 3. The is set to zero to simplify the atrix_1 to matrix_5 select shift values according to the type of code rate. Then the mux choose the right shift values received from matrices by the type phase, values arei after barrel shifter and accumulator. In the step five, are derived after the stage, the correction by circularly shifting the sum of p0and prediction parity vectors via XOR gates to get the ], CPC represents the required number of clock cycles required for encoding per codeword. The CPC of the proposed encoder is explained as follows. I n the first
in a cycle, so Kb cycles are
required. From second phase cycles to accumulate the
ithe fifth phase, it takes two prediction vector. In the sixth phase,
to correct the prediction vectors. Because all done in a pipelined way, it takes a total of codeword.
Because of dependence between parity vector to parity vector , all the parity bits can
values of
is and p0are computedencoding schemes [5][9]. But, the encoder we proposed break the data dependency in the encoding operations. By using proposed architecture, our encoder
and thus increases the throughout
(Fig. 1) as an example, our new encoder needs 18
encode one codeword while the sequential encoder architecture in [ 9] needs 62 cycles at code length 2304
IV. IMPLEMENTATION Based on IEEE 802.16e LDPC codes encode the codes with multiple
block length ranging from 576 to 2304.
giving different parameter to this encoder without rewriting the code and synthesizing again.
performed on Altera Stratix EP1S80F1508C5 Programmable Gate Array (FPGA)
Quartus II. Table V show the
results to [8] and [9] with additional input clock cycles for the code rate 1/2. Note that the
support single code rate and single code lenght. Table VI shows the synthesis result of the proposed encoder with code rates 1/2, 2/3, 3/4, and 5/6. T he information throughput (IT) is
as m×Clk/CPC where Clk is the clock fre
TABLE SYNTHESISRESULTSON Code
Length
Area
(LE )
Clk
[8] 576 2473 112.36
[9] 3391 192.23
[8] 960 3820 96.43
[9] 5100 159.57
[8] 1440 6370 85.76
[9] 7012 164.83
[8] 1920 9302 78.05
[9] 8924 148.72
[8] 2304 11393 78
[9] 10339 148.41
TABLE
Proposed encoder Synthesis Results On
Code Length
Area (LE)
Clk (MHz)
Proposed 576
20960 97.58 960
1440 1920
second phase to fourth phase, it takes three
i value for each block column. In cycles to calculate and store the . In the sixth phase, one clock cycle is needed to correct the prediction vectors. Because all operations are done in a pipelined way, it takes a total of Kb+6 cycles per ecause of dependence between parity vector to another all the parity bits can not be derived until all the computed in conventional sequential . But, the encoder we proposed break up ncy in the encoding operations. By using the , our encoder required less clock cycles throughout. Take the matrix at rate 1/2 our new encoder needs 18 cycles to encode one codeword while the sequential encoder architectureat code length 2304.
IMPLEMENTATION RESULTS
ased on IEEE 802.16e LDPC codes , our encoder can multiple code rate (1/2, 2/3, 3/4, 5/6) and from 576 to 2304. All we need to do is giving different parameter to this encoder without rewriting the code and synthesizing again. The hardware implementation was
Altera Stratix EP1S80F1508C5 Field Array (FPGA) device and synthes ized with show the comparison of implementation to [8] and [9] with additional input clock cycles for the
Note that the architectures in [8] and [9] only support single code rate and single code lenght. Table VI shows nthesis result of the proposed encoder with code rates 1/2, he information throughput (IT) is calculated
the clock frequency.
TABLE V
NFPGA IN[8][9]ONQUARTUSII Clk(MHz) IT(Gbps) IT/ Total Area
(Mb per Le)
112.36 1.678 0.0503
192.23 2.129 0.0612
96.43 2.314 0.0694
159.57 2.253 0.0648
85.76 3.089 0.0925
164.83 2.697 0.0776
78.05 3.746 0.1123
148.72 2.644 0.0761
78 4.493 0.1347
148.41 2.758 0.0793
TABLE VI
Synthesis Results OnQuartus II
IT (Gbps)
Rate 1/2
IT/Total Area (Mb per Le)
rate1/2 IT (Gbps)
Rate 2/3
IT/Total Area (Mb per Le)
rate2/3 1.561 0.07447 1.703 0.08125 2.602 0.12414 2.839 0.13544 3.903 0.18621 4.258 0.20314 5.204 0.24828 5.677 0.27084
2304 6.245 0.29794
Code Length
Area (LE )
Clk (MHz)
IT (Gbps)
Rate 3/4
IT/Total Area (Mb per Le)
rate3/4
Proposed 576
20960 97.58
1.756 0.08377
960 2.927 0.13964
1440 4.391 0.20949
1920 5.855 0.27934
2304 7.026 0.3352
Fig. 4 compares the throughput of the proposed architecture with [8] and [9]. We see that the proposed encoder architecture provides better throughput than the other two when code length longer than 960. However, we use less area (20960 LEs) to implement a single encoder supporting multiple code rates and multiple code lengths. Take the scheme [9] as an example, it need 161087 Les to have the same choices on code rates and lengths. The proposed architecture saves 87% area.
Fig. 4. Information throughput comparison over different code lengths.
Fig. 5. IT comparison between [9] and proposed encoder
Fig. 5 and Fig. 6 shows the IT comparison and the throughput/area ratio comparison between the proposed and the scheme [9]. We assume that the area of scheme [9] is the total amount of consumed LEs for those single code rate encoders. In our design, the area of our design would not change while the code rate or code length is different. In Fig. 5, the IT of our proposed is better than [9] when code length is longer than 1200. And in Fig. 6, the proposed
outperforms the work in [ 9] in terms of throughput/area ratio by 1.216 to 3.757 times.
0 2 4 6 8
576 960 1440 1920
Code length Throughput(Gbps)
0 2 4 6 8
576 960 1440 1920 Code length
Throughput(Gbps)
IT comparison
0.29794 6.813 0.32504
Total Area (Mb per Le)
rate3/4 IT (Gbps)
Rate 5/6
IT/Total Area (Mb per Le)
rate5/6 0.08377 1.801 0.08592 0.13964 3.002 0.14322 0.20949 4.504 0.21488 0.27934 6.005 0.29649 0.3352 7.206 0.34379
Fig. 4 compares the throughput of the proposed architecture the proposed encoder architecture than the other two when code length longer than 960. However, we use less area (20960 LEs) to implement a single encoder supporting multiple code rates and [9] as an example, it s to have the same choices on code rates and lengths. The proposed architecture saves 87% area.
over different code lengths.
proposed encoder.
IT comparison and the comparison between the proposed encoder and the scheme [9]. We assume that the area of scheme [9] is mount of consumed LEs for those single code rate encoders. In our design, the area of our design would not change while the code rate or code length is different. In Fig. 5, the IT of our proposed is better than [9] when code length is d in Fig. 6, the proposed encoder
throughput/area ratio by
Fig. 6. IT/area ratio over different code lengths rate.
V. CONCLUSIONS
We implemented an efficient multiple code rate and code length encoder for dual
parity bit prediction and correction. This hardware architecture can be employed to encode dual
IEEE 802.16e and IEEE 802.11n
modifications. With low data dependency and shorter clock cycle the proposed encoder can encode
higher throughput than conventional sequential encod implementation area is more economical than the total area account used in [8] a nd [9]
throughput/area ratio for all code
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proposed 1/2 proposed 2/3 proposed 3/4 proposed 5/6 [9] 1/2 [9] 2/3 [9] 3/4 [9] 5/6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
576 960
IT/LE
Code length IT/LE(Mb per LE)
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implemented an efficient multiple code rate and multiple dual-diagonal LDPC codes based on tion and correction. This hardware architecture be employed to encode dual-diagonal codes defined in both IEEE 802.16e and IEEE 802.11n standards without any matrix With low data dependency and shorter clock cycle the proposed encoder can encode continuously and get higher throughput than conventional sequential encod er. Our implementation area is more economical than the total area
nd [9]. We accomplishedbetter code lengths and code rates.
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1440 1920 2304
Code length
IT/LE(Mb per LE) proposed1/2
proposed 2/3proposed 3/4proposed 5/6
