Lo-Mei Chang 張洛梅
3F., No.14, Ln. 201, Zhulin Rd., Yonghe Dist., Phone: +886-952125786 New Taipei City 234, Taiwan natsuki011077@gmail.com
Education
National Taiwan University
Bachelor, Department of Computer Science & Information Engineering 2004.09 – 2008.06 - Major GPA: 4.00 Overall GPA: 3.91
- Ranked 6th place out of 118 graduates
National Taiwan University
Graduate Institute of Electronics Engineering, ICS Group 2008.09 – 2013.02 - DSP/IC Design Lab Advisor: Prof. Liang-Gee Chen
Research Experiences
Electronic System Level (ESL) Low Power Design for SoC 2007.09 – 2008.06 Advisor: Professor Chia-Lin Yang
- Participate in the design of NTU Co-Sim – a HW-SW co-simulation framework for platform based SOC.
- Evaluate system-level performance/power tradeoffs of platform-based SoC at early design stage.
NOR Flash Memory Models and Controller Design for SoC 2008.02 – 2008.06 Advisor: Professor Liang-Gee Chen
- Deliver system level models for NOR Flash Memory with SystemC.
- Design suitable NOR Flash memory controller with Verilog/SystemC.
- Improve the speed of simulation and verification for SoC system designs.
Bandwidth-Efficient MC Architecture Design for H.264/AVC Decoder 2008.07 - 2009.06 Advisor: Professor Liang-Gee Chen
- Cache-based MC architecture: exploits both intra-MB and inter-MB data reuse and reduce up to 46% MC bandwidth compared to conventional scheme.
- DRAM-friendly data access: DRAM-friendly data mapping and access control are designed to reduce the row pre-charge/active frequency and access latency of DRAM.
Specialties
- Software Programing: C/C++, MATLAB, SystemC - Hardware Programing: Verilog
- Languages: English (TOEFL iBT: R28 L30 S23 W24, Total 105)
Honors and Awards
- Third Place, IC Design Contest - Cell Based Design Category (2009) - Winner, 47nd DAC/ISSCC Student Design Contest (2010)
Publications
T.-D. Chuang, L.-M. Chang, T.-W. Chiu, Y.-H. Chen and L.-G. Chen, "Bandwidth-Efficient cache- based motion compensation architecture with DRAM-friendly data access control ", in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp. 2009 – 2012, May 2009.
T.-D. Chuang, P.-K. Tsung, P.-C. Lin, L.-M. Chang, T.-C. Ma, Y.-H. Chen and L.-G. Chen, "Low Bandwidth Decoder Framework for H.264/AVC Scalable Extension", in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2960–2963, May 2010.
T.-D. Chuang, P.-K. Tsung, P.-C. Lin, L.-M. Chang, T.-C. Ma, Y.-H. Chen and L.-G. Chen, "A 59.5mW Scalable/Multi-view Video Decoder Chip for Quad/3D Full HDTV and Video Streaming Applications", in IEEE International Solid-State Circuits Conference (ISSCC), 2010.
