Control Method for Voltage Source Converters in Systems with High Frequency Variability
Herbert L. Ginn III
Department of Electrical and Computer Engineering Mississippi State University
MsState, MS, U.S.A.
ginn@ece.msstate.edu
Guangda Chen
School of Power and Mechanical Engineering Wuhan University
Hubei, Wuhan, China gdchen@whu.edu.cn
Abstract— In recent years there has been much attention on the proportional plus resonant (P-R) current regulators for grid connected voltage-source converters (VSCs). Many strategies have been proposed for use of P-R controllers both in the stationary and in the synchronous reference frame that demonstrate VSC performance can be improved under non-ideal supply conditions such as supply asymmetry and supply voltage distortion. However, when employed in systems with high frequency variability such as micro-grids, the phase-locked loop (PLL) required for operation in the synchronous reference frame or for dynamic retuning of the resonant controller may experience poor performance or even loss of phase-lock. A method is presented here based on current decomposition that uses an efficient RDFT algorithm to compute equivalent admittances and allows control of grid connected VSCs to be performed in the stationary reference frame without supply synchronization. While only slightly more computationally burdensome, the method provides better performance in systems with high frequency variability. In this paper the proposed method is described and then performance is evaluated for systems with high frequency variability such as micro-grids with large step or pulsed loads.
Keywords- voltage-source converters; three-phase current regulation; synchronization; VSC control
I. INTRODUCTION
The use of the synchronous reference frame with PI current control is perhaps the most common method for grid connected voltage source converter based applications. Of course, to apply the synchronous reference frame requires a PLL.
Therefore, the behavior of the control system during frequency variation depends on the transient response of the PLL. This is generally not an issue since for most applications frequency variation is very small. However, for systems with high frequency variability, such as micro-grids with large step or pulsed loads, performance may become unacceptable or in extreme cases the VSC may even be tripped due to loss of phase-lock [1]. In recent years much attention has been given to proportional plus resonant controllers due to performance advantages over PI control [2]-[5]. An overview of the proposed control strategies using P-R control is given in [2] for both the synchronous and stationary reference frames.
However, even for stationary reference frame methods, P-R control requires a PLL to dynamically retune the resonant filter
if used in systems with frequency variation [3]. In the paper we present a VSC control method that does not require a PLL and is suitable for systems with high frequency variation. The performance of the proposed method for systems with high supply voltage frequency variation is investigated and both simulation and experimental results are presented.
II. PROPOSED CONTROL METHOD
The proposed control method is adapted from the control method presented in [6]. The reference signal generator that allows the proper currents to be generated by the converter current control is based on an efficient recursive discrete Fourier Transform (RDFT) algorithm for computing fundamental components of the measured quantities. Then a CPC [7]-[8] based current decomposition algorithm is used to provide separate control of orthogonal current components such as active and reactive current. The behavior of the RDFT as well as the current decomposition algorithm under frequency variation are first analyzed, then a control structure that allows proper operation of a VSC under large frequency variation and without synchronization is developed.
A. Frequency Variation Effect on RDFT
With the moving-window approach a computationally efficient recursive expression for the DFT can be obtained [9]- [10], which is expressed as
[ ] 1
1 1
( )k (k 1) 2 ( ( )x k x k N( )) e j gk N
ω
= − + − − −
X X . (1)
There are mainly two types of operational errors with expression (1). The first one is a calculation error due to the truncation error of multiplication in the fixed-point digital controller. This error will be accumulated in the recursive expression (1), therefore, it is called accumulation error in this paper. To avoid accumulation of errors caused by multiplication rounding, the following expression
1 1 1
1 1
( ) Re{ ( )} Im{ ( )}
[Re{ ( 1)} ( ) ( )]
[Im{ ( 1)} ( ) ( )]
k k j k
k P k P k N
j k Q k Q k N
= +
= − + − −
+ − + − −
X X X
X X
(2)
was developed in [6], where
1
( ) 2 ( ) cos g
P k x k k
N ω
= , (3)
1
( ) 2 ( ) cos g
P k N x k N k
N ω
− = − , (4)
1
( ) 2 ( )sin g
Q k x k k
N ω
= , and (5)
1
( ) 2 ( )sin g
Q k N x k N k
N ω
− = − . (6)
The second source of error occurs when the frequency of the input signal deviates from the nominal frequency generated in the converter control ω1g, and will be denoted as frequency deviation error. That error is the main source of concern for systems with high frequency variability. If the input signal frequency is slightly changed by an amount of Δω, while the sampling clock frequency remains fixed, then the estimated output will contain some errors due to the inherent feature of the RDFT.
In order to analyze the effects of the error without losing generality, assume that the input signal is a pure sinusoid
2 sin[( 1g ) ]
x= A ω + Δω t+ , ϕ (7) where, ω1g, generated by the implementation device, is equal to the nominal frequency of the power system and Δω expresses the frequency drift. The discrete output of (2), in this case, becomes
1 1
1 1
Re{ ( )} sin[(2 ) ]
sin[( ) ]
Im{ ( )} cos[(2 ) ]
cos[( ) ]
g
g
k A k
A k
k A k
A k
γ ω ω δ ϕ
λ ω δ ϕ
γ ω ω δ ϕ
λ ω δ ϕ
= + Δ − +
+ Δ − +
= + Δ − +
− Δ − +
X
X , (8)
where
1g
δ ωπ ω
=Δ , sin 2 γ δ
= π δ
+ and λ sinδ
= δ .
If the frequency of measured signal x drifts from its nominal frequency ω1g by Δω, then the estimated outputs of the RDFT will involve two frequency components. The first one is a high frequency component. Its frequency is around two times of ω1g
with the amplitude of γA. The second one is a low frequency component that mainly determines the features and precisions of the estimated outputs. Note, as long as there exists Δω, the estimated outputs will become, neglecting the high frequency component, alternating sinusoids with Δω and λA as their frequency and amplitude respectively. Furthermore, the estimated magnitude and phase of the measured signal, without considering the effects of the high frequency components, can be written as
2 2
1 1 1
|X ( ) |k ≈ (Re{X ( )})k +(Im{X ( )})k =λA (9)
and
cos[( ) ]
arctan
sin[( ) ] 2
( ) ( )
2 2
Phase k
k
k k
ω δ ϕ π
ω δ ϕ
π ω δ ϕ ϕ ϕ π
− Δ − +
≈ +
Δ − +
= − + Δ − + = Δ + −
. (10)
Simulation results for the RDFT output under variable supply frequency are presented in Fig. 1(a) and 1(b). The real and imaginary components are shown in Fig. 1(a) and the phase is shown in Fig. 1(b). As expected, the outputRe{X1( )}k and Im{X1( )}k of the RDFT swing between -λA and λA, and |X1( ) |k behaves as a DC quantity having λA as its magnitude. The oscillatory behavior of the real and imaginary components disturbs the phase computation
In order to use the RDFT with fixed reference frequency ω1g for VSC control, the magnitudes of the error factors γ and λ must be within an acceptable level. In order to evaluate these two error factors, Fig. 2 gives the relations of γ (Δω/ω1g) and λ(Δω/ω1g),
(a)
(b)
Figure 1. Simulation results for the RDFT output (a) real and imaginary components for variable input signal frequency (b) phase.
The error factor γ determines the magnitude of the high frequency component in the estimated Re{X1( )}k or
Im{X1( )}k . The error factor λ, on the other hand, represents amount of deviation of the measured current or voltage from the true value. It is also observed from (10) and Fig. 1 that there exists phase error Δφ(k) of estimated signal x due to the frequency deviation.
Figure 2. ε ω ω(Δ / 1g)andλ ω ω(Δ / 1g). B. Frequency Variation Effect on CPC Based Current
Decomposition
An orthogonal decomposition appropriate for most grid- connected VSC applications is provided by the CPC theory developed by Czarnecki [8]. For sinusoidal conditions, a subset of the theory decomposes the current into active, reactive and unbalanced components. In order to perform this decomposition the system, as seen from the point of measurement, is expressed in terms of two admittances, the equivalent admittance and the unbalanced admittance. The equivalent admittance is expressed as
e=Ge+ jBe = RS+ ST + TR
Y Y Y Y (11)
where Ge and Be are the equivalent conductance and equivalent susceptance respectively. The unbalanced admittance is
( * )
j
ST TR RS
eϕ α α
= = − + +
A A Y Y Y (12)
where α=1ej120° and α*=1e-j120°. Having these admittances the three-phase current vector
[iR iS iT]
= T
i (13)
can be decomposed into mutually orthogonal components as
a r u
= + +
i i i i (14)
As shown in [8] the actual admittances at the point of measurement do not need to be known. Furthermore only two admittances are needed. Calculating the CRMS values of the measured voltages and currents using (2) their ratio can be interpreted as admittances for the fundamental frequency. The value of these admittances can change as the N-sample moving window of the RDFT advances. Therefore, the admittances are considered as time varying quantities denoted by the ~ symbol.
The two necessary admittances are referred to as time varying admittances of an equivalent load and are calculated by
, S
R
TR ST
RT ST
= =
I
Y I Y
U U . (15)
Having these two admittances the time varying equivalent admittance is given by
=Ge+ jBe = ST + TR
Ye Y Y , (16) and the time varying unbalanced admittance is given by
( )
j
ST TR
eϕ α
= = − +
A A Y Y . (17)
A main advantage can now be seen with regard to the phase error, Δφ(k), introduced by frequency deviation error of the RDFT. Note that the phase error will be canceled in the admittances calculation since Δφ(k) exists in both phase expressions for the voltage and current, thus, their difference will exclude the phase error Δφ(k). Therefore, only a small error will be introduced in the magnitude of the admittance calculations due to the magnitude error factor λ.
Finally, the time varying equivalent and unbalanced admittances can be used to generate current reference signals.
A three-wire system is assumed so that only two phases are needed. With the time varying equivalent and unbalanced admittances, current components can be generated as shown in [6] with expression
1 1
1 1
Re{ }cos Im{ }sin
2 Re{ }cos Im{ }sin
Ra R g R g
e
Sa S g S g
i U k U k
i G U k U k
ω ω
ω ω
⎡ − ⎤
⎡ ⎤= ⎢ ⎥
⎢ ⎥ ⎢ − ⎥
⎣ ⎦ ⎣ ⎦
(18)
for active current in phases R and S,
1 1
1 1
Re{ }sin Im{ }cos
2 Re{ }sin Im{ }cos
Rr R g R g
e
Sr S g S g
i U k U k
i B U k U k
ω ω
ω ω
⎡− − ⎤
⎡ ⎤= ⎢ ⎥
⎢ ⎥ ⎢− − ⎥
⎣ ⎦ ⎣ ⎦
(19)
for the reactive currents, and
1 1
1 1
(Re{ }Re{ } Im{ }Im{ }) cos 2 (Re{ }Re{ } Im{ }Im{ }) cos (Re{ }Im{ } Im{ }Re{ })sin (Re{ }Im{ } Im{ }Re{ })sin
Ru R R g
Su T T g
R R g
T T g
i A U A U k
i A U A U k
A U A U k
A U A U k
ω ω ω ω
⎡ − ⎤
⎡ ⎤= ⎢ ⎥
⎢ ⎥ ⎢ − ⎥
⎣ ⎦ ⎣ ⎦
⎡ + ⎤
−⎢ ⎥
+
⎢ ⎥
⎣ ⎦
(20)
for the unbalanced currents.
Unfortunately, even though the calculated values of Ge, Be, and A have negligible error even for large frequency deviations, the CRMS values of the voltages computed by the RDFT have a non-negligible phase error. Thus, current reference signals generated using (18)-(20) will have a phase error. Fortunately, as shown below the correct phase of the admittances allows correction of the current phase error.
C. Control Structure with Phase Error Correction
A control method for grid-connected converters without supply synchronization has been developed by removing the phase error present in expressions (18) and (19). Here only fundamental components are considered with a symmetrical
supply voltage, thus expression (20) is not considered.
However, (20) could be included for more general cases. A simplified block diagram of the proposed control structure is shown in Fig. 3.
The main feature of this control is the RDFT and CPC based current decomposition that provides the current reference signals. The reference signal generator is shown divided into two parts: the RDFT measurement and decomposition algorithm used for measuring the necessary voltages and currents and decomposing them into equivalent and unbalanced admittances, and the current waveform reconstruction algorithm that transforms the frequency-domain values G e* andB back to time-domain current waveforms. In addition to e* these there are two feedback control loops associated with the reference signal generation. The first is an active current controller which determines the value of G associated with *e the active current at the fundamental as required by the active power of the load plus power losses in the converter system. Of course, it is the typical DC bus voltage controller found in most VSC control systems. The second is a reactive current controller that ensures the reactive current is equal to the set- point in the presence of the RDFT induced phase error.
As discussed earlier, because the RDFT calculation of the measured voltage contains a phase error given by (8) the reference currents generated by the current reconstruction algorithm will also contain a phase error. However, unlike the voltage phase error, the current phase error does not vary in time. This can be seen by applying (8) to the expression for current (18). For phase R this gives the expression
1 1
2 sin[( ) ]cos
2 cos[( ) ]sin
Ra e g
e g
i G U k k
G U k k
λ ω δ ϕ ω
λ ω δ ϕ ω
= Δ − +
+ Δ − +
(21)
which is equal to
2 sin[ 1 ]
Ra e g
i = G U λ ω k+ Δωk− +δ ϕ . (22) Thus, the reference current has the same frequency as the voltage, ω1g + Δω, but contains a phase error equal to δ. This introduces a phase shift in the active rectifier output relative to the desired phase setting. However, the CPC equivalent admittance computed at the active rectifier input terminals is
computed correctly due to cancellation of the phase error in the admittances calculation. This provides a correct value of the equivalent susceptance, Be, that can be used to correct the phase error in the current. The addition of a control loop to force Be equal to the desired set-point will remove the phase error introduced into the current reconstruction algorithm by the RDFT of the measured supply voltage.
A typical approach was taken for the control layers below the reference signal generator, i.e. those components that enable the converter to act as a controlled current source.
Current references are provided to a dead-beat current controller in the stationary reference frame, and the modulator uses a standard SVPWM algorithm.
III. TEST SYSTEM SIMULATION RESULTS
A three-phase active rectifier test system was simulated to show the performance of the proposed control method. A diagram of the test system is shown in Fig. 4 and important system parameters are provided in Table I. To simplify the test setup only a large inductor was Lc=1mH as opposed to a more complex input filter as this does not affect the performance of the active rectifier as it relates to supply frequency variations.
Simulation results during a frequency step change of –10Hz are shown. Figure 5 shows the real and imaginary components as well as magnitude and phase of the voltage URT computed by the RDFT before and after the frequency step change.
Simulation results without compensation for the phase error, i.e. without the reactive current controller, are shown in Fig. 6.
The Equivalent Conductance shown in Fig. 6 does not change since the active current controller is regulating the DC bus voltage at the set-point by maintaining the required load active power. However, the Equivalent Susceptance must change due to the phase error introduced into the current reference.
Equivalent Conductance and Susceptance with compensation for the phase error are shown in Fig. 7. The ripple is noticeable due to the large deviation from the nominal frequency
The VSC supply voltage and phase R current are shown in Fig. 8 for the proposed control with reactive current controller.
The performance is good with a slight phase-shift that returns to zero within two cycles of the supply.
IGBT3- Phase bridge AC side
inductor s
iR
iS
iT
uR
uS
uT
vR
vS
vT d
C U
SVPWM modulation Phase R current
controller (DB)
Phase S current controller (DB)
6 measurement & RDFT
decomposition algorithm
Nominal Freq generator, ,sinω1gt cosω1gt
current waveform reconstruction
algorithm R
i
iS
*
iR
*
iS
Ud
0 Reactive current
controller (PI)
Ge
Be
Udcmd
+ iSR
i uRT
uST
Active current controller (PI)
*
Be
*
Ge
Figure 4. Active Rectifier Test System.
TABLE I. TEST SYSTEM PARAMATERS
Electrical Parameters Parameter Description Value Supply Voltage Line-to-Line 208 V
Coupling Inductor, Lc 1mH DC Bus Capacitor, C 900uF
DC Load 15.5kW
Control Parameters
Parameter Description Value
Sampling Frequency, Ts 12kHz Generated Nominal Freq. 60Hz
Active Current Control Kp 0.00368
Active Current Control KI 0.325
Reactive Current Control Kp 0.368
Reactive Current Control KI 32.5
UdSET 500V
BeSET 0
IV. HARDWARE VALIDATION
An experimental prototype was developed and built in order to validate the proposed method. The prototype is composed of a designed digital controller based on the Texas Instruments TMS320F2812 32-bit fixed-point digital signal processor and American Superconductor’s PM-1000 PEBB- based bi-directional VSC module. A simplified diagram of the
system hardware is shown in Fig. 9(a) and a photo of the prototype is shown in Fig 9(b).
Because a supply of variable frequency was not available for the experimental validation the nominal frequency of the control was set to ω1g = 70Hz to provide a Δω= -10Hz. All other parameters were the same as in Table I. The experimental results in steady-state are shown both without and with the phase error correcting reactive current controller in Fig. 10(a) and Fig. 10(b) respectively. Results during a transient in which the reactive current controller is initially disabled and then suddenly enabled are shown in Fig. 11. Experimental results match the simulation results very closely validating the proposed control method.
Figure 5. CRMS value of voltage URT before and after -10Hz frequency step change without reactive current control loop.
Figure 6. Equivalent Conductance and Susceptance before and after -10Hz frequency step change without reactive current control loop.
Figure 7. Equivalent Conductance and Susceptance before and after -10Hz frequency step change with reactive current control loop.
0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 -200
-150 -100 -50 0 50 100 150 200
Time
Voltage and Current
Phase R Voltage and Current Frequency Step Change -10Hz
Figure 8. Simulation results with a 10Hz frequency step change using the proposed control structure.
Analog Signal Conditioner W3100A hardware stack
TCP/IP interface
TMS320F2812 (32 bit fixed point DSP) 16
To Supervisory System
XC95288XL(CPLD)
American Superconductor PM-1000 (PEBB) Protection Logic and Driver
Interface 6 CHD/A
6
SPI
(a)
(b)
Figure 9. Simplified diagram of the system hardware (a) and photo of the experimental setup (b)
Figure 10. Experimental steady-state results without reactive current control loop (a) and with reactive current control loop (b).
Figure 11. Experimental results showing the transient resulting from the sudden enabling of the reactive current control loop.
V. CONCLUSIONS
A VSC control method that does not require a PLL and is suitable for systems with high frequency variation has been developed. The control structure is almost immune to frequency variations with only very small high frequency ripple resulting from frequency deviation from the nominal set- point. The transient time of any noticeable phase error during frequency step changes is less than two cycles of the supply.
Furthermore, it is not possible for the developed control scheme to lose phase-lock since it does not require supply synchronization to operate.
REFERENCES
[1] W. Ren, M. Steurer, L. Qi, “Evaluating dynamic performance of modern electric drives via power-hardware-in-the-loop simulation,” IEEE International Symposium on Industrial Electronics (ISIE 2008), June 30 -July 2 2008, pp. 2201 – 2206.
[2] R. Teodorescu, F. Blaabjerg, M. Liserre, and P. Loh, “Proportional- resonant controllers and filters for grid-connected voltage-source converters, IEE Proc. Electr. Power App. Vol. 153, No. 5, Sept. 2006, pp. 750-762.
[3] A. Timbus, M. Ciobotaru, R. Teodorescu and F. Blaabjerg, “Adaptive Resonant Controller for Grid-Connected Converters in Distributed Power Generation Systems,” Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, (APEC '06), 19-23 March 2006, 6 pp.
[4] M. Liserre, R. Teodorescu, F. Blaabjerg, “Multiple Harmonics Control for Three-Phase Grid Converter Systems With the Use of PI-RES Current Controller in a Rotating Frame,” IEEE Trans. on Power Electronics, Vol. 21, No. 3, May 2006, pp. 836-841.
[5] D. N. Zmood, D. G. Holmes, “Stationary Frame Current Regulation of PWM Inverters with Zero Steady-State Error,” IEEE Trans. on Power Electronics, Vol. 18, No. 3, May 2003, pp. 814-822.
[6] H. Ginn, G. Chen, “Flexible Active Compensator Control for Variable Compensation Objectives”, IEEE Trans. on Power Electronics, Vol.
23, Issue 6, Nov. 2008, pp. 2931 – 2941.
[7] L. S. Czarnecki, “Power Theory of Electrical Circuits with Quasi- Periodic Waveforms of Voltages and Currents,” ETEP, Vol. 6, No. 5, September/October 1996.
[8] L. S. Czarnecki, “Orthogonal decomposition of the current in a three- phase nonlinear asymmetrical circuit with nonsinusiodal voltage,” IEEE Trans. Instrum. Meas., Vol. IM-37, pp. 30-34, Mar. 1988.
[9] Hatem A. Darwish and Magdy Fikri, “Practical Considerations for Recursive DFT Implementation in Numerical Relays”, IEEE Trans. on Power Delivery, Volume 22, Issue 1, Jan. 2007, pp. 42 – 49.
[10] J. A. Rosendo Macfas, A. Gomez Exposito, “Efficient Moving-Window DFT Algorithms,” IEEE Trans. On Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, No. 2, February 1998.
