http:empc1.ee.ncku.edu.tw/ CCE/EE NCKU
A 60-GHz High-Gain, Low-Power, 3.7-dB Noise-Figure Low-Noise Amplifier in 90-nm CMOS
Hsin-Chih Kuo and Huey-Ru Chuang
Institute of Computer and Communication Engineering, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C.
CIRCUIT DESIGN
First two stage current density: 156 μA/μm
Lm resonates Cds1 & Cgs2 (Lm=0.17 nH, Q=16)
NF improvement : 4.9 to 3.7 dB @ 60 GHz
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Lm (nH) 3.5
4 4.5 5 5.5 6
Noise Figure (dB)
Ls = 0.05 nH Ls = 0.1 nH Ls = 0.15 nH Ls = 0.2 nH Ls = 0.25 nH Ls = 0.3 nH
0 10 20 30 40 50 60 70 80 90 100
Frequency (GHz) 0.14
0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3
L (nH)
2 4 6 8 10 12 14 16 18
Q factor
L Q
0 0.2 0.4 0.6 0.8 1 1.2
VGS (V) -0.4
-0.2 0 0.2 0.4 0.6 0.8
gm3 (A/V
3 )
VB = 0 V VB = 0.2 V VB = 0.4 V W/O Linearization
NFMEASUREMENT SETUP
45 50 55 60 65 70
Frequency (GHz) -10
-5 0 5 10 15 20 25 30
S21 (dB)
Meas. (PNA) Sim.
Meas. 1 @ NFA, 299.8 K Meas. 2 @ NFA, 297.9 K
50 53 56 59 62 65
Frequency (GHz) 1
3 5 7 9 11 13
Noise figure (dB)
Sim.
Meas. 1 @ 60 cm, 299.8 K Meas. 2 @ 120 cm, 297.9 K
Min. NF=3.7 dB @ 61 GHz Avg. NF=4.3 dB
MEASURED S-para.,IP1dB,&IIP3
IRL & ORL are well below -10 dB @ 57 - 64 GHz
IP1dB: -23 dBm & IIP3: -12 dBm @ 60 GHz
40 45 50 55 60 65 70
Frequency (GHz) -25
-20 -15 -10 -5 0
S11 (dB)
Meas.
Sim.
40 45 50 55 60 65 70
Frequency (GHz) -16
-14 -12 -10 -8 -6 -4 -2 0
S22 (dB)
Meas.
Sim.
-40 -35 -30 -25 -20
Input Power (dBm) 12
13 14 15 16 17 18 19 20 21
Gain (dB)
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2
Output Power (dBm)
Meas. Gain Sim. Gain
Meas. Output Power Sim. Output Power
1-dB Sim. Meas.
-40 -35 -30 -25 -20 -15 -10 -5
Input Power (dBm) -80
-70 -60 -50 -40 -30 -20 -10 0 10 20
Output Power (dBm)
Meas. Pout1 @ 60 GHz Meas. Pout3 @ 60 GHz Meas. Pout1 @ 60 GHz, Vg4=0.38V Meas. Pout3 @ 60 GHz, Vg4=0.38V
PERFORMANCE COMPARISON
Ref. Tech.
(CMOS)
Supply
Voltage (V) Topology Gain (dB) IIP3 (dBm)
IP1dB
(dBm)
NFmin
(dB)
Powerdiss
(mW) FOM
2010 IMS 0.13 m 1.5 Current-reused 13.2 @ 58 GHz -4.7 -15 4.9 29.1 6.8 2011 MWCL 0.13 m 1.5 3-stage cascode 21 @ 53 GHz -16 -25 8.3 15.1 1.9
2011 RFIC 65 nm 1.2 3-stage cascade
(with T-Line) 20.6 @ 60 GHz N/A -29 4.9 @ 58
GHz 33.6 --
2012 RFIC 65 nm 1.25 3 CS TF + CF 23 @ 60 GHz ~ -16.5 -26.5 4 8 22.2 This Work 90 nm 1.5 2-stage cascode + 1
CS 22 @ 57.3 GHz -13 -23 3.7 @ 61
GHz 13.5 25.4
KEYNOTE:
1. Two-stage cascode structure with a common-source buffer amplifier.
2. Inter-stage noise matching inductor + derivative superposition (DS) method Good NF & linearity 3. Max. gain: 22 dB @ 57.3 GHz 4. Min. NF: 3.7 dB @ 61 GHz 5. Power consumption: 13.5 mW
Chip size:0.76×0.78 mm2
s
ds m s ds
m m
m m L
C g L SC
L I S Z V
1 1 1
1
2
3 , 3
12 12 23,2
12 23,1 23
1 1
IP IP
IP
IP A A A
A
PDC NF
f IIP Gain
] FOM [
1 3
TFMS spiral inductors (more layout flexibility)
Lm
