An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires
Ya-Chi Huang1, Meng-Hsueh Chiang1, Sumeet Kumar Gupta2 and Shui-Jinn Wang1
1Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
2School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
Email: [email protected]
Abstract –
Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked GAA MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.Stacked GAA MOSFET Structure
Conceptual process of stacked GAA MOSFET
Conclusion -
We have proposed a multi-Vt 6-T SRAM design methodology using stacked NWs with Lg = 9.3 nm to provide Vt selectivity in the SoC application and achieve low-voltage 6-T SRAM with 20% saving in area.By tuning the doping level and channel configuration in stacked NWs, multiple Vt is achieved for flexible design.
3-D view of stacked GAA MOSFET and 2-D cross-sections of the n-channel GAA MOSFET (not to scale).
Session F3
0.0 0.1 0.2 0.3 0.4 0.5 0.6
10-8 10-7 10-6 10-5 10-4 10-3
1 channel 1x1015 2x1019
2 stacked nanowires (bottom/top channel)
1x1015/1x1015 2x1019/2x1019 2x1019/1x1019
I DS (A/m)
VGS (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6
0 100 200 300 400 500 600
1 channel 1x1015 2x1019
2 stacked nanowires (bottom/top channel)
1x1015/1x1015 2x1019/2x1019 2x1019/1x1019
I DS (A/m)
VGS (V)
Axis Design rule Symbol Size (nm)
x
Contact width CW 8
Equivalent oxide thickness EOT 1 Contact edge to diffusion CD 8
Poly to Poly P 5.25
Poly to Dif. Ext. Tg 3
Channel thickness tSi 4
Fin pitch FP 10
y
Gate length Lg 9.3
Contact length CL 8
Gate to contact Lsp 3.1
Gate pitch GP 26
z
Channel height hSi 4
BOX thickness TBOX 50
Substrate thickness TSub 20 Supply voltage VDD 0.6 V
Doping (cm-3) HD and LV Design RSNM (mV) IW (μA) 1х1015
(undoped)
1 NW (HD area) 87.32 3.02
2 parallel NWs (LV area) 125.24 2.46 2 stacked NWs (HD area) 132.53 2.51 2х1019
1 NW (HD area) 104.62 1.31
2 parallel NWs (LV area) 130.71 0.84 2 stacked NWs (HD area) 155.03 0.77 Bottom/top channel @ 2х1019/1х1019
2 stacked NWs (HD area) 157.44 0.76
Simulated I
DS-V
GScharacteristics
IDS-VGS characteristics of 1 NW and 2 stacked NWs (VDS = 0.6 V) with different doping concentrations combinations to achieve multi-Vt design.
Parameters of GAA MOSFET and SRAM layout
SNM and I
Wvalues for different designs
Results of 6-T SRAM circuit and schematic layout
0 100 200 300 400 500
10-12 10-11 10-10 10-9 10-8 10-7
1 channel
2 nanowires, bottom/top different doping same doping
I off (A/m)
Ion (A/m)
I
onvs. I
offcharacteristics Doping scheme window
Different stacked doping levels from undoped to 1х1020 cm-3
Predicted multi-Vt vs. channel dopings for 2 stacked NWs
IW vs. RSNM characteristics.
LV SRAM with 2 parallel NWs requires 20%
more area.
PU:PG:PD=1:1:1 and 1:1:2 for high-density and low-voltage respectively
HD LV
