Abstract—This brief presents a frequency tracking loop (FTL)
to realize a crystalless wireless sensor node (WSN) for wireless body area network (WBAN). By tracking a remote wireless RF reference for system clock calibration, the proposed FTL allows WSNs to tolerate a large-frequency error from on-chip CMOS oscillators. Moreover, to achieve energy-efficient transmissions in crystalless, a sufficiently accurate convergence clock is required to enable burst overmegabits-per-second system throughput with minimized operation duty cycle. For the dedicated purpose, a comparison-based binary-search tracking scheme, which ensures accurate and robust convergence against noisy wireless channel, is further developed to manage the operation of FTL. The in-termediate frequency back-end part of FTL is implemented in 90-nm CMOS process. Measurement results show that the FTL extends an initial tolerance of system clock error to ±3% and achieves a final quartz-crystal comparable ±50-ppm accuracy. This enables 4.85-Mb/s wireless links and improves 79% energy efficiency by RF operation-time reduction, giving a power-saved and miniaturized WSN device for WBAN applications.
Index Terms—Crystalless, frequency calibration, on-chip
oscil-lator, process, voltage and temperature (PVT) variation, wireless body area network (WBAN).
I. INTRODUCTION
C
URRENTLY, an emerging standard for wireless body area network (WBAN) applications is under development by IEEE 802.15 Task Group 6 [1]. Different from Bluetooth and ZigBee, it is specifically designed for medical or multimedia communication in, on, or around human bodies. A typical WBAN system contains several wireless sensor nodes (WSNs) for data sensing, storing, and processing, whereas a central processing node (CPN) is in charge for collecting WSNs data through a short-range channel for back-end services [2].WSN design has various severe restrictions. First of all, it is essential to use small battery or energy harvesting tech-niques, whose available output power is often less than 500 μW [3], to avoid expensive and impractical battery replacement. Hence, under the supply power limitation while maintaining several years’ lifetime, WSN power must be extremely low. On the other hand, minimized production cost and tiny size integration for comfortable wearing are also crucial consid-erations. Unfortunately, the quartz crystal, as a conventional reference frequency generator, remains a bottleneck to meet Manuscript received April 8, 2011; revised June 17, 2011; accepted July 25, 2011. Date of publication October 6, 2011; date of current version October 19, 2011. This work was supported by the Ministry of Economic Affairs of Taiwan under Grant 98-EC-17-A-03-S1-0005. This paper was rec-ommended by Associate Editor T. Li.
The authors are with the Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: whsung@si2lab.org; cylee@si2lab.org).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2011.2164155
these requirements. Its heterogeneous integration with a CMOS process occupies bulky on-board passive components, which increase power, area, and manufacture cost at the same time. Consequently, it is desirable to replace the quartz crystal with an on-chip CMOS oscillator in WSN [4]–[6].
The major design challenge to realize an all-CMOS crystal-less WSN is the limited system throughput caused by degraded oscillator frequency accuracy. Due to process, voltage and temperature (PVT) variations, the achievable accuracy in stand-alone CMOS oscillators based on analog or digital compensa-tion circuits is between±0.5% to ±3% [7], [8]. However, the conventional timing and frequency synchronization techniques in wireless systems could only tolerate few hundreds parts per million of carrier frequency offset and sampling clock offset. In order to compromise such incompatible provided accuracy, existing crystalless systems usually operate at submegabits-per-second data rate under specific modulation scheme and protocol [4] or merely rely on constant voltage and temperature environ-ments [5], which certainly constrains WBAN operation scenar-ios. Inevitably, the limited throughput results in longer system duty cycle (wakeup duration) and inefficient energy dissipations from power-hungry RF front-end static bias currents. For an optimized energy-efficient link, a sufficiently accurate system clock is required to enable burst overmegabits-per-second data transmissions [9], [10] and thus minimize the system operation duty cycle.
Accordingly, to achieve all-CMOS crystalless integration, a frequency tracking loop (FTL) [12], which calibrates the WSN clock frequency by tracking a sinusoidal RF reference broadcasted from CPN wirelessly, is proposed to extend the system clock error tolerance compatible with on-chip oscilla-tors [7], [8]. Moreover, to enhance the throughput of crystalless systems for energy saving, a comparison-based binary-search tracking (CBST) scheme, which ensures robust and accurate convergence performance against noisy wireless channel, is further developed to manage the operation of FTL.
In this brief, the FTL design [12] is presented in detail. The rest of the parts are organized as follows. Section II discusses the FTL architecture and highlights major design consider-ations of system stability. Section III introduces the CBST scheme for robust FTL control and analyzes its convergence performance. Section IV reports the experimental results of the proposed FTL. Finally, this work is concluded in Section V.
II. SYSTEMDESCRIPTIONS
A. FTL Architecture
Fig. 1 shows a crystalless WSN receiver architecture with the proposed FTL, where notation f on data paths indicates the signal frequency. In CPN, target clock frequency fO is
Fig. 1. Crystalless WSN receiver architecture with the proposed FTL. multiplied NSYNtimes by the synthesizer as single-carrier RF
reference fREF transmitted to WSN. In WSN, for the simple
property of frequency tuning, a digitally controlled oscillator (DCO) is utilized to generate system clock (fDCO), whose
frequency error is defined as ε =|(fDCO− fO)/fO|. By
down-converting RF reference, IF signal reflects the degree of DCO frequency error, i.e., fIF= NSYN· fO· ε. To identify ε, a
fre-quency detector (FD) is applied to quantize fIF. According to
FD outputs, FTL controller generates digital codeword (CDCO)
to adjust fDCOtoward fOiteratively.
Similarly, [6] and [13] perform wireless reference tracking for on-chip synthesizer voltage-controlled oscillator calibra-tion. As a contrast, in the proposed FTL, decision blocks and related signal processing are entirely designed in mixed-signal and digital domains at low-IF band, whereas RF front-end structures remain unchanged. Instead of NSYNadjustment
(RF-band fSYNcalibration), the architecture of direct fDCOcontrol
prevents using power-hungry fractional-N synthesizer and extra frequency dividing for system clock usage. Additionally, since the FTL is a frequency lock loop using noisy wireless reference, this digital implementation is necessary and much easier to ensure tracking accuracy and stability at the same time, which have not been considered and solved in [6] and [13].
B. System Stability Considerations
FTL is designed to detect a frequency error up to εmax and
calibrates fDCOto an error less than εOfor
overmegabits-per-second links. To cover large εmaxfrom CMOS oscillators, the
LPF bandwidth must extend to at least BWIF= fREF· εmax.
Thus, IF signal, represented as IF(t), not only contains the interested sinusoidal signal fIF but also carries a noise term
with bandwidth BWIF. Inevitably, the convergence accuracy
becomes quite sensitive to SNR condition. The choice of FD and corresponding FTL ε cancellation scheme are critical de-sign issues of stability.
The FD design in FTL negative feedback loop can be real-ized by two approaches. One intuitive approach is applying a frequency estimator (FE) to determine exact fIF values. The
optimal maximum-likelihood FE for sinusoidal signals is dis-crete Fourier transform (DFT), but it requires high sample rate (2BWIF) analog-to-digital converter for large εmax and
high-point DFT for accurate εO. A low-complexity alternative is to
use a frequency counter (FC) shown in Fig. 2(a) according to
|ˆε| = NIF/(NDCO· NSYN− NIF) Δ
= εFE (1)
where fDCO and fIF are quantized to NDCOand NIFby two
edge counters. Target CDCOis calculated by multiplying 1±
Fig. 2. FD design based on (a) frequency counter estimation and (b) PFD.
Fig. 3. Estimation performance of FC-FE approach under different SNR.
εFE. Another approach is to utilize a phase-frequency detector
(PFD) to detect the lead and lag information in phase domain, as shown in Fig. 2(b), where φSYNand φIFare the phases of
syn-thesizer output and IF(t). Based on [6], fDCOcan be calibrated
to fO by modifying the reference signal to fREF = fREF·
(NSYN− 1)/NSYN. However, for a received noisy wireless
reference, conventional FDs and control schemes cannot ensure robust convergence as in normal phase/frequency-locked loop (PLL/FLL) circuits. The relatively wideband noise certainly influences FDs to extract real fIF from IF(t), particularly
when ε is approaching to εO. FD’s trigger clock, i.e., IF(t)
or φIF in Fig. 2, contains induced glitches that disturb actual
clock positions or edge counting values. As a result, minimal detectable ε is limited. For instance, Fig. 3 shows the estimation performance of FC-FE approach in (1). The final accuracy sat-urates early at thousands part per million before FTL achieves target region in a low-SNR case.
Although a Schmitt trigger circuit can be applied in FDs to suppress external noise, its comparison threshold is not suitable to rise too much in our case. This is because the gain stages in FTL signal path are not specifically designed for IF(t) whose bandwidth is much wider than original baseband signal. Without modifying the gain control specification, the FTL only applies the Schmitt trigger to filter few noise transitions around zero crossing. For entirely stable convergence, a CBST scheme with modified FD is then proposed to manage FTL operations.
III. PROPOSEDCBST CONTROLSCHEME
A. CBST Control Operation
Fig. 4 shows the simplified block diagram of the proposed CBST controller in FTL and its related signal path. One counter
Fig. 4. Simplified block diagram of CBST controller and related signal path.
Fig. 5. Search procedure of the proposed CBST controller.
is triggered by DCO clock, and the other is triggered by IF(t). The FE-like counting structure provides wide detectable range for large εmax. To prevent unstable loop behavior, the decisions
of CBST scheme do not rely on either exact edge trigger counts or positions that may have external noise included. Instead, the NIF values corresponding to different fDCO are
compared. Then, target CDCO is determined by searching the
frequency with relatively lower NIF, which represents that the
selected frequency is closely adjacent to fO. For this purpose,
the counter in Fig. 4 is in charge to set up constant time duration TACCaccording to appropriate NDCOcontrol for NIF
accumulation.
Fig. 5 illustrates the search procedure of the CBST controller. Assume that the channel noise is temporarily ignored. The V-shape characteristic curve indicates the relation of fDCOand
NIF values within TACC duration. Since accumulated NIF is
directly proportional to ε, it is straightforward to adjust fDCO
toward our target region within (1± εO)· fOby searching the
valley in the characteristic curve. To speed up FTL tracking time, the proposed search procedure operates based on a binary-search manner modified from fast locking PLL controllers [11]. For the ease of explanation, frequency search window Sn for
nth binary-search iteration is defined by its lowest, highest,
and median frequencies, denoted by fL,n, fH,n, and fM,n,
respectively. Note that fM,nrepresents the FTL search result in
nth iteration. Initially, fM,1is set to the DCO free-running
fre-quency whose error is less than tolerable value εmax, whereas
fH,1 and fL,1are set to (1 + /− εmax)· fM,1, respectively, to
construct S1. Starting from S1, which determines the maximum
search boundary, the CBST search procedure is performed by continuously comparing NIFvalues corresponding to fL,nand
fH,n, denoted by NL,nand NH,n. The frequency with less NIF
value in fL,n and fH,n, together with fM,n, is chosen to set
up next window Sn+1. For example, S2 is set up by fH,1 and
fM,1 from S1 since NH,1 is less than NL,1. This procedure
always chooses the frequency region corresponding to the half-side characteristic curve with lower ε. Search window Sn is
iteratively reduced by half from initial±εmaxto convergence
Fig. 6. (a) PDF of w(n). (b) Probability of EGfor a given s(n).
±εO, and median frequency fM,n finally locates in target
region afterlog2(εmax/εO) iterations.
The CBST controller generates control code CDCOfor fDCO
adjustment according to relation fDCO= (fO· εO)/CDCO,
which is a reciprocal ratio transform. Thus, binary search median fM,n can be controlled by CM,n= 2· (CL,n·
CH,n)/(CL,n+ CH,n), where CL,n and CH,n are CDCO for
fL,n and fH,n, respectively. In addition, the relation also
im-plies that the frequency scalar operation, such as (1± εmax)·
fM,1 for S1setup or NDCO control for constant TACC setup,
can be performed by direct scalar division of CDCO.
B. Convergence Analysis
In the following, the channel noise is considered for FTL convergence stability analysis. IF(t) consists of sinusoidal sig-nal s(t) = sin(2π· fIF· t) and carried noise w(t). The NIF
value, triggered by IF(t), is written as NIF= TACC/TIF+
NG, where NG is unwanted glitch counting from w(t) and
TIF= 1/fIF. Note that the notation underlined represents a
random variable. The distribution of NG can be modeled as
a binomial (Bernoulli) experiment of glitch occurrence, which is called event EG, under NTrail= TACC/TD times of trails,
where TD is the minimum glitch transition width that can
be captured by the counter as one success trigger count. The condition for event EGto happen is
EG: IF(n) = s(t)+w(t)|t= n TD
≥+VTH, for s(n) < 0
≤−VTH, for s(n) > 0 (2)
where VTH is the decision threshold of limiting comparator
(or Schmitt trigger circuit). Assume that the probability density function (PDF) of w(n), denoted by pw(x) = P [w(n) = x], is
white Gaussian distribution∼ Normal(0, σ2
w). The probability
of EGunder deterministic s(n), denoted by P [EG|s(n)] shown
in Fig. 6(b), can be calculated by integrating pw(x) values
for x satisfying (2), as the tail regions indicated in Fig. 6(a). Hence, the expected P [EG|s(n)] in one TIF duration, that is,
P (EG) = E[P [EG|s(n)]], is derived from
P [EG|s(n)] = ∞ (VTH+|s(n)|) σw e−x2/2 √ 2π dx Δ = Q VTH+|s(n)| σw Then, P (EG) = 1 TIF/TD · TIF/TD−1 n=0 Q VTH+|s(n)| σw (3) where Q(·) is the right-side tail probability of standard normal distribution. For large NTrail, binomial NG can
Fig. 7. CBST search procedure considering channel noise influence.
Fig. 8. Simplified PDF model for CBST convergence ability analysis. be approximated to Gaussian distribution with E[NG] =
NTrail· P (EG)= NΔ Bias and Var[NG] = NTrail· P (EG)·
[1− P (EG)] Δ
= σ2
G. Obviously, NBias and σ2G are mainly
determined by NTrail and σw but remain nearly constant for
different ε after averaging. Considering the effect of NG, the
CBST operation in Fig. 5 is redrawn as Fig. 7, where original
NIFis shifted upward by NBiasand appears within the region
of variance σ2
Gin statistics.
It is hard to estimate NG from NIFsince either IF(t) under large ε or low-SNR condition eventually increases NIFat the
same time. Instead of general NG extractions, the proposed
CBST search scheme mutually compares NIF between fL,n
and fH,n to cancel the nonzero biased NBias automatically.
Thus, the FTL convergence is only affected by σ2
G. If we further
enlarge TACC period to TACC = TACC· L for time average,
σG2 can be reduced to σ2G= σG2/L based on the central limit
theorem. Then, the boundary condition at final iteration n = K in Fig. 7 can be analyzed to investigate whether the decision of
NL,K > NH,Kis correct. As the simplified PDF model shown in Fig. 8, the comparison between NL,K and NH,Kis equiva-lent to detection hypothesis H1: NH1= NL,K− NH,K> 0,
where NH1is Gaussian with E[NH1] = TACC · fREF· εOand
Var[NH1] = 2σG2. In other words, the detection rate of H1is
written as P (EC), where ECrepresents the event of successful
convergence. For required convergence rate P (EC)≥ 1 − α,
an appropriate TACC targeted at final accuracy εO is
deter-mined by Q ⎛ ⎝ 0− E[NH1,K] V ar[NH1,K] ⎞ ⎠ = Q −T ACC· fREF· εO 2σ2G ≥ P (EC) = 1− α. (4)
As the equality in (4) holds, the corresponding period, denoted by TACC,K , is sufficient to discriminate minimal search win-dow SK+1 from SK. In fact, TACC for iteration n < K need
not to be the same as TACC,K . It is because, for Snwith search
region±εn larger than final±εO, the corresponding E[NH1]
is much far away from zero and less L increment is enough.
Fig. 9. FTL convergence under AWGN channel and circuit distortions. Therefore, the optimal TACC for nth iteration is obtained by replacing εOin (4) with εn.
IV. EXPERIMENTALRESULTS
To verify our proposal, the IF back-end part of FTL is fabricated in 90-nm standard CMOS process. All related RF front-end circuits are set up by the commercial frequency-shift keying (FSK) chip targeted at 433/915-MHz ISM-band. In our demonstration, εmax is set to±3% compatible with [7]
and [8], and εO requires to be less than ±50 ppm to enable
overmegabits-per-second WBAN systems [9], [10].
In IF-FTL, a DCO is embedded to generate target fO=
5-MHz system clock with 50-ppm tuning ability. By applying power-of-two (P2) delay structure based on hysteresis delay cells, it covers wide tuning range (200 ns–10 ps) and achieves optimal power and area efficiency for low-power crystalless integrations. Initially, the free-running DCO is self-calibrated by a PVT detector [12] to maintain ±3% clock accuracy for basic WSN operations. As the reference is downconverted, IF(t) is converted to IF(t) by a Schmitt trigger for coarse noise filtering and square limiting. Then, IF-FTL iteratively performs the CBST calibration.
Fig. 9 shows the simulation results of FTL convergence in AWGN channel. Nonideal circuit distortions in signal path are also considered, including−110 dBc/Hz synthesizer phase noise at 1-MHz offset [6] and IF(t) gain mismatch from ampli-fication stages. For satisfying P (EC)≥ 99.5%, the proposed
FTL ensures the residual frequency error less than±50 ppm as SNR≥ 5 dB. To tolerate possible gain mismatch, comparison threshold VTH is chosen at the level no more than 30% full
swing voltage. The results show the FTL is able to tolerate 3-dB gain mismatch (29.2% voltage distortion) under our re-quirement. The proposed scheme is more accurate and reliable than conventional FE/PFD approach against noise.
Fig. 10 shows the measured FTL convergence accuracy and the required operation time at SNR = 7 dB. From initial 3% frequency error, the FTL tracks a fREF = 435 MHz(NSYN=
87) reference signal transmitted from CPN. By CBST search, DCO accuracy is converged toward ±50 ppm as the curve indicated from the right side to the left side. To achieve final 23.5-ppm accuracy, the required CBST tracking time in IF-FTL is TIF−FTL= 1.06 ms. Considering the settling time of testing
FSK-IC, the total operation time is TFTL= 3.06 ms, which
can be minimized if the FSK synthesizer is controllable by our IF-FTL chip. Note that the exact resolution of each DCO
Fig. 10. Measured FTL convergence accuracy and its required operation time. TABLE I
COMPARISONSWITHRELATEDFTL DESIGNS
control bit εnis uncertain due to PVT variations. Therefore, the
CBST scheme is applied to three DCO tuning stages (coarse, first, and second fine-tuning) sequentially and separately. Op-timal TACC for three tuning stages is obtained from (4) with
εStage= fO· tuning stage least significant bit delay.
Moreover, the convergence clock is applied to an orthogonal frequency-division multiplexing baseband chipset in [10] to confirm overmegabits-per-second transmissions in crystalless. For continuous 9.6 kb/s electrocardiogram signal monitoring, the system requires±100-ppm accuracy to maintain 4.85 Mb/s data link during a burst 3.45-ms active period in every 0.84-s cycle. By measuring the slope of fDCOcurve related to variant
voltage and temperature conditions, the slope shows the variant rate of fDCOaround 5 MHz is 1.16%/0.1 V and 0.07%/◦C. The
test chip enables our demo case under the variation rate slower than 0.25 V/s and 41.8◦C/s. Eventually, at least 79% RF front-end operation time and power is reduced [4]–[6] to improve system energy efficiency.
Table I lists the comparisons with related FTL designs. In addition, with ultralow integrated power and area, the IF-FTL, which occupied 0.5× 0.55 mm2, consumes 11.3 μW
in tracking mode, and the always-on P2-DCO consumes 7.6 μW in 5 MHz. Fig. 11 shows the chip microphotograph and layout view.
V. CONCLUSION
This brief has presented an FTL to realize energy-efficient crystalless WSN integrations. By tracking a wireless reference for system clock calibration, the FTL allows WSNs to tolerate
Fig. 11. Microphotograph of the test IF-FTL chip and layout view. a large-frequency error from on-chip oscillators. In addition, to reduce system duty cycle in crystalless for energy saving, an accurate clock frequency is certainly required for enabling overmegabits-per-second throughput. Thus, a CBST scheme is further proposed to control FTL operations for accurate and robust convergence. As a result, a miniature WSN solution with low-power and low-cost features becomes available for WBAN applications.
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