不同元件尺寸對傳導路徑之影響

接下來我們想要知道 On State 時的電流改變，是因為 Filament 的數量抑或是 形狀改變造成的，圖 3-15 是 Cu/30-nm -Si/p⁺⁺Si 元件，元件工作區域面積 25

m²(Device Diameter 5 m)，共 20 組電流電壓在 On State 的量測結果，如果是 Filament 的數量改變造成 On State 時的電流改變，當我們增加元件工作區域的大 小時，Filament 應該會隨著面積變大而變多，而導通電阻(on-Resistance)會變小，

所以我們改變元件大小，元件工作區域從 25 m² (Device Diameter 5 m)增加到 4x10⁴m² (Device Diameter 200 m)，共取 3 組不同大小元件作統計，每一種大 小 元 件 量 測 20 次 On State 電 阻 大 小 ， 然 後 取 帄 均 當 作 此 元 件 大 小 的 on-Resistance，關係如圖 3-16，為了比較方便，我們將 on-Resistance 歸一化和 Device Diameter 作圖，圖 3-17 可以得到當元件工作區域大小增加了 3 orders 電 阻 變 化 只 有 不 到 百 分 之 七 ， 和 文 獻 中 提 到 元 件 工 作 區 域 變 化 6 orders 而 on-Resistance 只增加 2.5 倍相呼應[60]，表示 Filament 數量並沒有隨著元件工作 區 域 變 大 而 明 顯 的 增 加 ， 所 以 我 們 推 論 在 電 阻 轉 換 區 應 該 是 形 成 單 根 的 Filament，而電流改變可能是 Filament 形狀變化造成。

當電流通過時，由焦耳定律得知產生的熱能和電流及電阻有關，Joule’s law of heating ，因為 Filament 和整個 Metallic Region 比較起來占-Si 轉換層很小 的部份，所以熱能對發生在局部區域的 Filament 影響較大，我們假設 Filament 形狀近似於半徑為 ，長度為 的圓柱體，如圖 3-18，圓柱體一方面受到焦耳熱 提供的能量，另一方面也經由黑體輻射將能量散失，當累積在圓柱體的熱能多過 於散失掉的熱能，Filament 會被破壞掉，因為 Filament 是由一連串的 Cu 粒子形 成，推測當 Filament 被燒斷時的臨界溫度應該要高於 Cu 的熔點，利用以下公式 推算：

為當 Filament 被燒斷時的臨界電流， 為電阻率(Cu： Ω-cm)，

為 Stefan’s 常數( W/m²K⁴)， 為圓柱體的半徑，我們可以從電性 量測結果，藉由低電阻態轉變為高電阻態時的臨界電流和 Cu 的熔點反推圓柱體 半徑，臨界電流 如圖 3-19 表示，加上 Filament 的改變主要應該是受形狀而不是 數量的影響，所以我們藉由四組不同的元件，以及同一個元件不同次數量測的結 果估算出 Filament 半徑的改變範圍，如表 3-2，其中 STD1 及 STD2 是同一個元 件不同次的量測結果，而 device2~4 則為和 STD 不同的元件，在半徑約 0.02 m 及 0.2 m 都有計算出的臨界溫度 T 略高於 Cu 的熔點溫度 Tm，歸納出 Filament 的半徑變化應該介於在 0.02 m 到 0.2 m 之間，和一些文獻作比較，其中有文 獻提到在-Si 中形成 Filament diameter 約 0.2~0.5m[67]，也有文獻利用奈米線 結構，金屬奈米線和-Si 奈米線交叉部份形成元件，控制奈米線金屬寬度來改變 上電極(銀電極)的大小，量測認為 Filament diameter 約 20 nm，甚至小於 20 nm[59]。最後圖 3-20 是我們的元件在 OM 下作觀測，圖 3-20(a)及(b)是元件量 測前的情形，圖 3-20(c)及(d)是元件經過量測後的情形，發現銅上電極有出現黑 點，可能是因為置於空氣中所以出現氧化現象，參考 CMOS 製程中會將銅的部 份上下左右包覆起來作為保護，之後我們在元件製程上可以在銅電極上再增加一 層 TaN 來改良。

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Device Diameter 5m On-state Current

Device diameter (m) 20 cycles Mean

圖 3-16、Device Diameter 為 5、10、200 m 的元件，每一種大小元件量測 20 次然後取帄均當作此元件大小的 on-Resistance。

0 1x10⁴ 2x10⁴ 3x10⁴ 4x10⁴ 0.93

0.94 0.95 0.96 0.97 0.98 0.99 1.00

area ： 3 orders on-R ： 1.065 times

Normalized on-Resistance

Device Area (m^2)

圖 3-17、低電阻態歸一化電阻與元件工作區域大小關係圖。元件工作區域大小 增加了 3 級數，而電阻變化只有一倍多，表示導通路徑式只有單根 Filament。

圖 3-18、將導通燈絲路徑比擬成半徑為 r 長度為 l 的圓柱體。

58

-4 -3 -2 -1 0

0.0 2.0x10^-5 4.0x10^-5 6.0x10^-5 8.0x10^-5 1.0x10^-4

|Current| (A)

Voltage (V) Turn off

圖 3-19、紅色虛線部份標示為元件從低電阻態回到高電阻態的臨界電流(I)。

表 3-2、紅色部份為圓柱體半徑 r 0.02m 計算得到的臨界溫度，藍色部份為半 徑 r 0.2m 計算得到的臨界溫度，當臨界溫度(T)高於銅的熔點溫度(Tm)，電阻

態從低電阻態回到高電阻態。

Critical current ：I

圖 3-20、(a)~(d)為元件在 OM 下從 Top View 方向觀測圖。(a)及(b)是不同大小元 件工作區域在尚未經過電阻轉換之前的原始情形，(c)及(d)是元件在施加電壓後 經過 100 次 DC Cycle 操作之後的情形。

60 換層內是由固定的 Metallic Region 以及在改變的 Filament 組成。元件在耐久性及 穩定性表現良好，Endurance 可以達到 10³，Retention 在室溫及高溫下(85℃)也能 夠維持超過 10⁴秒，而電阻轉換的高低電阻比例可以達到 10⁶，在眾多材料中表 現優異。

非晶矽薄膜轉換層內部在 Forming Process 形成 Metallic Region，此部份區域 大小和電極材料及薄膜厚度有關，我們並利用三種不同厚度的非晶矽薄膜得到銅 電極的銅擴散進入非晶矽層中形成 Metallic Region 的區域隨厚度變化；另外，轉 換層靠近底電極部份會形成或是燒斷 Filament 來造成元件高低電阻態的不同，

電流電壓曲線經過 Fitting 之後得到，在高電阻態電流傳導一開始是 Ohmic，

隨著電壓增加開始在約 0.4 V 左右進入 SCLC，然後因為 Filament 開始形成造成 電流快速上升至設定的限制電流 100 A，在低電阻態電流經由 Filament 是 Direct Tunneling 傳導機制，在正負電壓區間電流和電壓曲線為對稱性且呈一次線性關 係；而導通路徑受熱能影響造成 Filament 燒斷回到高電阻態，在高電壓下電流傳 導是 Schottky，而低電壓下電流傳導回到 SCLC，如圖 4-2 所示。

Cu/-Si/p⁺⁺Si 元件的臨界轉換電壓 Von及 V_off大約在 4.6 V 及-2 V，以文獻中 方面已有相當的經驗，如圖 4-4，利用氮化矽(Nitride)作遮蔽，垂直向下乾蝕刻 非晶矽薄膜製作出矽奈米線結構，此奈米線尺寸可以下降到 100 nm 以下，如圖 4-5 所示；未來，希望能夠利用此一技術結合 RRAM 設計出 cross-bar 的結構，

並且更進一步能夠利用 round 及 sharp 的 Nanowire 來討論 Corner Effect 對於此結 構的影響；此外，目前文獻上使用-Si 作為轉換層的研究仍然不是相當廣泛，已 知使用 Cu、Ag 及 Al 作為上電極都能夠達到電阻轉換之效果，未來也希望藉由 比較不同材料電極對於-Si 薄膜轉換相同或是相異之處，有助於電阻轉換機制解 釋更為統整化。

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圖 4-2、Cu/-Si/p⁺⁺Si 元件轉換電性圖。經過 Forming Process 後元件在低電阻態 (LRS)和高電阻態(HRS)之電流傳導機制。

圖 4-1、Cu/-Si/p⁺⁺Si 元件轉換示意圖。經過 Forming Process 後從高電阻態到低 電阻態(Turn On)再回到高電阻態(Turn Off)。

圖 4-4、利用 Nitride 作為 Spacer 製備矽奈米線。

圖 4-3、電阻式記憶體利用點交叉設計和 CMOS 元件形成高密度堆積結構 [62]。

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圖 4-5、小於 100-nm 之矽奈米線在 In-line SEM 觀測圖。

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