其他處理器比較

如表 5-14 所示，與其他處理器比較 256 點 FFT 效能與速度。

表 5-14：多級向量量化效能比較表[33]

Device Speed MHz

256-point FFT benchmark

ADSP-218X 75

DSP16410 170

TMS320C54X 160

`320VC549 100

ARM7TDMI/

Piccolo

70

DSP1620 120

This work 125

Execution time Execution cycle

20 40 60 80 100 120 140 160 180 200 (us) 2K 4K 6K 8K 10K 12K 14K 16K 18K 20K (cycles) 另外與 TIC54x 的規格比較如表 5-15。

表 5-15：與 TI 的規格比較表 TIC54X Proposed

Design S-P –Com MAC 8 cycle 1 cycle S-P –Real MAC 1 cycle 1/2 cycle R2 Butterfly 8 cycle 9 cycle * S-P Com Bit-Revise 3 cycle 2 cycle Convolution 1 cycle 1/2 cycle Hardware

Accelerators

Image/Video Extension

MSVQ Paths

External RAM Type Support

Async SDRAM

SRAM

*：include Scale shift & load/store memory

與其他 paper[2]比較，處理器加上智慧型 DMA 後效能已逼近且成本非常低。

表 5-16：效能與成本比較表 ITEM 50-taps FIR

100 samples

50-taps complex FIR,

100 samples

1K Complex FFT

Gate Count

This Work 11200 (cycles)

24000 (cycles)

53427 (cycles)

136K (Include

VQ IP) A 32-b RISC/DSP

Microprocessor[2]

12200 (cycles)

22000 (cycles)

45000 (cycles)

210K

第六章 結論

通用的 32-bit RISC 處理器與平行的 16-bit/32-bit DSP 整合，為一個兼顧 成本與效能單核心處理器的解決方案，本論文提出語音導向的智慧型 DMA 搭配處 理器可成為 RISC/DSP 平行處理的架構，掛載的語音向量量化加速器符合 IP 重覆 使用的特性，對特定運算可大幅提升處理器的效能。智慧型 DMA 擁有傳輸與運算 的模式，傳輸方面從周邊到記憶體擁有多種傳輸組合，並有多種的定址模式提升 傳輸效率；在運算方面內建 ALU，能處理複數乘法、柱狀位移等資料路徑，且指 令集模式符合 RISC 架構，不影響處理器管線的運作。

智慧型 DMA 的特色在於能結合傳輸與運算的功能，在計算中有效率的安排資 料與運算，提高處理器的處理的效率。以下說明三種合作方式：

(1)利用智慧型 DMA 傳輸資料的定址法，與 ALU 的乘加器合作，可進行固定迴圈 的乘累加運算。

(2)利智慧型 DMA 的位元反轉傳輸模式，在進行快速複立葉轉換前先安排好係 數，再經由智慧型 DMA 裡 ALU 的資料路徑作蝴蝶運算。

(3)進行編碼簿搜尋時，利用智慧型 DMA 對外部記憶體周邊的溝通能力，協助向 量量化加速器傳輸編碼簿，進行加權均方誤差的計算。

本論文提出的 RISC/DSP 處理器特別適合於語音的運算，語音的運算常需要 對訊號做頻譜轉換來進行分析；另外也常用線性預測模型來合成語音的訊號，對 此，這個處理器特別適合作以上兩個動作，如 FFT 及 FIR 的實現，可用在語音壓 縮、語音辨識等。

為了應付其他語音應用或影像處理，智慧型 DMA 可以針對演算法掛載特定的 硬體加速器 IP，因此未來可增加一條高速的匯流排如 AHB bus，各種加速 IP 與 外部記憶體皆可透過匯流排與處理器內部作溝通，由智慧型 DMA 掌管優先權順 序。另外在智慧型 DMA 與記憶體處理能力上，為了成本導向的目標，未來在智慧

型 DMA 內可增加處理動態隨機存取記憶體的單元(DRAM)，相較於靜態隨機存取記 憶體(SRAM)，需支援高低位址的資料交互讀取的機制，雖然在速度上不如 SRAM，

但擁有高密度成本低的優點。

本論文設計與一顆通用 RISC 處理器做整合，並應用在 MELP 語音壓縮演算法 上，能解決 MELP 三個運算集中的地方，成功減少運算量 70%以上。本設計將在 國家晶片中心（CIC）下線，未來此顆晶片可用做低成本的單核心 RISC/DSP 處理 器來使用，也可以 IP 的方式，將系統整合起來，成為一個 SOC 的系統。

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