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1. http://www.cts.com.tw/tvc/dtv.htm 2. http://www.cts.com.tw/tvc/dtv/twdtv.htm 3. http://www.idc.com

4. http://www.itis.org.tw/forum/content2/99if38c.htm 5. http://www.cts.com.tw/tvc/dtv/standard/endrep-idx.htm 6. http://www.hitopcomm.com/main.html

7. http://www.meluk-panasonic.co.uk 8. http://www.sony.co.uk/digitaltelevision/

9. http://www.hitachi-eu.com/

10. http://www.samsungelectronics.com/digital_settop_box/digital_cable_receiver/

dcatv2300rc.html

11. http://www.digitallworld.com/

12. http://www.fujitsu-siemens.com/rl/products/broadband/audiographics300.html 13. http://www.Motorola.com

14. http://products.zarlink.com/product_profiles/ZL10310.htm 15. http://www.semiconductors.philips.com

16. http://www.oaktech.com/press_room/press_releases/1999/051799.html 17. http://www.lsilogic.com/news/product_news/pr20020520.html

18. Motorola, Inc., “2K Integrated DVB-T Demodulator,“ Data sheet, 1998

19. http://www.sony.net/Products/SC-HP/Product_List_E/TV_E/d_broad_E.html 20. Infineon Technologies, “ Terrestrial Receiver of DVB-T,” Data Sheet : SQC

6100, June 21, 1999.

21. Philips Semiconductors, “TDA10045H DVB-T channel receiver, ” Nov., 2001 22. http://www.dvb.org/dvb_compliance/framesets/dvb_compliance.html

23. R. Mackowitz, et al., “A single-chip DVB-T receiver,” IEEE Trans. on Consumer Electronics, vol. 44, no. 3, pp. 990-993, Aug. 1998.

24. S. A. Fechtel, et al., “Advanced receiver chip for terrestrial digital video broadcasting : architecture and performance,” IEEE Trans. on Consumer Electronics, vol. 44, no. 3, pp. 1012-1018, Aug. 1998.

25. A. Menkhoff, et al., “Performance of an advanced receiver chip for DVB-S and DSS,” IEEE Trans. on Consumer Electronics, vol. 45, no. 3, pp. 965-969, Aug.

1999.

26. M. Haas, et al., “Flexible two IC chipset for DVB in cable reception,” IEEE Trans. on Consumer Electronics, vol. 42, no. 3, pp. 335-340, Aug. 1996.

27. D.-S. Han, J.-J. Kim, “Adaptive frame selection algorithm for DVB-T,” IEEE

Trans. on Consumer Electronics, vol. 48, Issue 3, pp. 617-623, Aug. 2002.

28. S.L. Linfoot, R.S. Sherratt, “Analysis of a DVB-T compliant receiver simulation under various multipath conditions,” IEEE Trans. on Consumer Electronics, vol. 46, Issue 1, pp. 201-206, Feb. 2000.

29. S.L. Linfoot, R.S. Sherratt, “Correcting for local oscillator phase offset in a DVB-T compliant receiver under multipath conditions,” IEEE Trans. on Consumer Electronics, vol. 46, Issue 2, pp. 306-312, May 2002.

30. F. Sanzi, J. Speidel, “An adaptive two-dimensional channel estimator for wireless OFDM with application to mobile DVB-T,” IEEE Trans. on Broadcasting, vol. 46, Issue 2, pp. 128-133, Jun. 2000

31. G. Baruffa, et al., “DSP based OFDM demodulator and equalizer for

professional DVB-T receivers,” IEEE Trans. on Broadcasting, vol. 45, Issue 3, pp. 323-332, Sep. 1999

32. P. Combelles, et al., “0.5-µm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T

standard,” IEEE J. of Solid-State Circuits, Vol. 33, Issue 11, pp. 1781 –1792, Nov. 1998

33. U. Reimers, “DVB-T: the COFDM-based system for terrestrial television,”

Electronics & Communication Engineering Journal, vol. 9, Issue 1, pp. 28-32, Feb. 1997.

34. S. O'Leary, “Hierarchical transmission and COFDM systems,” IEEE Trans. on Broadcasting, vol. 43, Issue 2, pp. 166-174, Jun. 1997.

35. S. Anikhindi, “DVB-T decoder ICs,” IEEE Trans. on Consumer Electronics, vol. 43, Issue 3, pp. 438 -442, Aug. 1997.

36. http://www.asiamoney.com.tw/research/stocknew/8009.htm 37. http://www.ccl.itri.org.tw/products/transfer/wireless/11t_041.htm 38. http://www.ccl.itri.org.tw/products/transfer/wireless/11t_043.htm

39. ETSI European Telecommunication Standard ETS EN 300 744, Mar. 2001 40. ETSI European Telecommunication Standard ETS TR 101 190, Mar. 1998 41. P. C. Skerlos, et. al., “All channel television tuning system,” US patent

4598425, 1986.

42. Infineon Technologies, “2-band TV tuner,” TUA6020 Data Sheet, 2000.

43. Philips, “Cable TV and VCR 2-band tuner”, TDA6502 Data Sheet, 2002.

44. G. M. Maier, et. al., “Double conversion tuner a must for the future?,” IEEE Trans. Consumer Electronics, vol. 38, pp. 384-388, 1992.

45. S. Birleson, et. al., “Silicon single-chip television tuner technology,” proc. in IEEE ICCE, pp. 38-39, 2000.

46. Microtune, Inc., “RF silicon tuner,” MT2032 Data Sheet, 2001.

47. Conexant, “Digital cable tuner RFIC,” CN2811 Data Sheet, 2001.

48. Broadcom Corporation, “Digital cable tuner,” BCM3415 Data Sheet, 2001.

49. 周致遠,陸地數位電視廣播系統調諧器射頻模組之研製,國立中山大學電 機工程學系碩士論文,中華民國九十三年七月。

50. 周致遠,應用於 DVB-T 系統射頻調諧器之低雜訊可變增益放大器,CIC 測 試報告(編號:SiG-92D-08b)。

51. 韓府義,應用於數位電視廣播射頻調諧器之 550 860 MHz 低雜訊可變增益 放大器,CIC 測試報告(編號:M25-92E-12b)。

52. European Telecommunications Standards Institute (ETSI), EN 300744: Digital Broadcasting Systems for Television, Sound and Data Services; Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, 1997.

53. European Telecommunications Standards Institute (ETSI), TR101190:

Implementation Guideline for DVB-T Transmission Aspects, 1998.

54. A. R. Shahani, D. K. Shaeffer, and T. H. Lee, “A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver,” IEEE J. Solid-State Circuits, vol.32, pp. 2061-2070, Dec. 1997.

55. F. Ellinger, R. Vogt, and W. Bächtold, “Compact monolithic integrated resistive mixers with low distortion for HIPERLAN,” IEEE Trans. Microwave Theory and Techniques, vol.50, pp. 178-185, Jan. 2002.

56. F. D. Flaviis and S. A. Mass, “X-band doubly balanced resistive FET mixer with very low intermodulation” IEEE Trans. Microwave Theory and Techniques, vol.43, pp. 457-460, Feb. 1995.

57. W.-C. Cheng, C.-F. Chan, C.-S. Choy, K.-P. Pun, “A 1.5V 900 MHz CMOS current folded-mirror mixer,” in Proc. 5th Inter. Conf. on ASIC, vol. 2, pp.

1050-1053, Oct. 2003.

58. B. Pham, “A 1.9 GHz Gilbert mixer in 0.18u CMOS For a cable tuner,”

Carleton University Press, 2003.

59. K. Su, “Analog Filters,” Reading: second edition, Kluwer Academic Publishers, 2002.

60. B. Nauta, “A CMOS transconductance-C filter technique for very high

frequencies,” IEEE J. of Solid-State Circuits, vol. 27, no. 2, pp. 142-153, Feb.

1992.

61. R. Schaumann, and M. E. V. Valkenburg, “Design of Analog Filters,” Reading:

published by Oxford University Press, Inc, 2001.

62. B. Razavi, ”Principles of Data Conversion System Design,” Reading:

WILEY-INTERSCIENCE, 1995.

63. H. Kondoh, H. Yoshimura, H. Shibata and Y. Matsuda, “A 1.5-V 250-MHz to

3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase-detector,” IEICE Transaction on Electron, vol. 78-C, pp. 381-388, April 1995.

64. K. Yoon, and W. Kim, “Charge Pump Boosting Technique for power noise immune high-speed PLL implementation,” Electronics Letters, vol. 34, no. 15, pp. 1445-1446, 23, July 1998.

65. C. Kim, I. Hwang and S. Kang, “A Low-Power Small-Area ±7.28 ps Jitter 1GHz DLL-Based Clock Generator,” IEEE J. of Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002.

66. M. Mostafa, H. Elwan, A. Bellaour, B. Kramer, and S. H. K. Embabi, “A 110 MHz 70 dB CMOS variable gain amplifier,” 1999 IEEE Inter. Symp. on Circuits and Systems (ISCAS'99), vol. 2, pp. 628-631, May 1999.

67. C. S. G. Conroy, D. W. Cline, P. R. Gray, “A high-speed parallel pipelined ADC technique in CMOS”, Digest of Technical Papers, VLSI Circuits, pp. 96-97, Jun.

1992.

68. Sumanen, L.; Waltari, M.; Halonen, K.A.I., “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE J. Solid-State Circuits, Vol.36, pp.1048-1055, July.

69. E.H. World, A.M. Despain, “Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementation,” IEEE Trans, Comput, Vol 33, No.5, May 1984.

70. M. Hsieh and C. Wei, “Channel estimation for OFDM systems based on comb-type pilot arrangement in frequency selective fading channels” IEEE Trans. On Consumer Electron., vol. 46, pp. 931-939, July 1998.

71. S. M. Kay, “Fundamentals of Statistical Signal Processing: Estimation Theory,”

Prentice Hall, New Jersey, 1993.

72. Gordon L. Stuber. Principles of Mobile Communication. Kluwer Academic Publishers, Boston, 2nd edition, 2001.

73. “Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for digital terrestrial television,” ETSI EN 300 744 V1.4.1, Jan.

2001.

74. Shung, Bernard C, Paul H S, and etc., “VLSI architectures for metric normalization in the Viterbi algorithm,” IBM Corp, pp.1723-1728, 1990.

75. E. Boutillon, N. Demassieux, “High speed low power architecture for memory management in a Viterbi Decoder,” IEEE Int. Symp. On Circuits and Systems, vol. 4, pp.284-287, 1996.

76. P. J. Black, T. H. Y. Meng, “Hybrid survivor path architectures for Viterbi decoders,” IEEE Int. Conf. on ICASSP, vol. 1, pp.433-436, 1993.

77. J.B. Kim, Y.J. Lim, M.H. Lee, “A low complexity FEC Design for DAB,” in

Proc. ISCAS, vol. 4 , pp. 522 – 525, May 6-9, 2001.

78. H.C. Chang, C.B. Shung, and C.Y. Lee, “A Reed-Solomon product-code (RS-PC) decoder chip for DVD application,” IEEE J. Solid-State Circuits. vol.

36, pp. 229-238, Feb. 2001.

79. I.S. Reed, M.T. Shih, T.K. Truong, “VLSI design of inverse-free

Berlekamp-Massey algorithm,” IEE Proc., vol. 138, pp. 295-298, Sep. 1991.

80. S.K. Jain, L. Song, K.K. Parhi, “Efficient semisystolic architectures for

finite-field arithmetic,” IEEE Trans. VLSI Syst., vol. 6, pp. 101-113, Mar. 1998.

81. J.H. Jeng, J.M. KUO and T.K. Truong, “A high efficient multiplier for the RS decoder,” IEEE Int. Symp. VLSI Technology, Systems, and Applications, pp.

116-118, June 8-10, 1999.

82. I.S. Reed, M.T. Shih, T.K. Truong, “VLSI design of inverse-free

Berlekamp-Massey algorithm,” IEE Proc., vol. 138, pp. 295-298, Sep. 1991.

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