為了驗證我們模擬器的準確性，我們使用圖 25 之 RTD2950系統晶片帄台 來比較實際硬體帄台效能測試的結果與模擬器輸出的效能結果差異。RTD2950 內建 NAND 快閃記憶體控制器存取 圖 26 為實驗帄台使用之快閃記憶體 Hynix HY27UF082G2B。RTD2950 的性能諸元，請見表 6。
圖 25：RTD2950 實驗帄台
圖 26：HY27UF082G2B 照片
表 6：RTD2950 性能諸元 項 目 規 格
CPU MIPS 4KEc
CPU 工作頻率 189 MHz DDR2 工作頻率 378 MHz DDR2 RAM 容量 128 MB NAND IO 工作頻率 7.375 MHz NAND 記憶體容量 256 MB 3.2 Disksim 環境設定
我們使用如圖 27 的設定作為系統拓撲設定，其示意圖如圖 28。
# system topology
topology disksim_iodriver driver0 [ disksim_bus bus0 [
disksim_ctlr ctlr0 [
disksim_bus bus1 [
disksim_nand nand0 []
# end of bus1 ]
# end of ctlr0 ]
# end of bus0 ]
# end of system topology ]
圖 27：實驗環境拓撲設定
driver0 block erase, page read, page program 這些單一命令測試一百次執行的時間，取其 帄均值，其中的參數計算說明如：。
圖 29：NAND0 specification using typical value (RTD2950.parv)
1. Command overhead = 3*(tCLS+tCLH)+4*(tWP+tWH) = 135 ns * 7 = 0.000945 ns
2. Bulk sector transfer time = 512*135 ns = 0.06912 ms
3. Status read time: 因為 RTD2950 的控制器支援 R/B 的狀態讀取，因此 不需額外花費時間發出 read status 的命令，因此設為 0。
表 7：單一命令之模擬與實驗時間比較表
Command A. Disksim (ms) B. RTD2950 (ms) C. 誤差
Block erase 1.501045 1.324519 11.76%
Page read (512 bytes) 0.095065 0.096593 1.61%
Page program (512 Block erase 1.500000 1.322000 Page read (512 bytes) 0.025000 0.021200 Page program (512
Block erase time = 1.322, WEh to busy time = 0.0001, Status read time = 0,
Cache program busy time = 0.003, Addr to data loading time = 0.0001, Never disconnect = 1,
Print stats = 1,
Max queue length = 1, …
} # end of NAND0 spec
圖 30：NAND0 specification using measured value (RTD2950_fix.parv) 表 9：更新參數後之模擬與實驗時間比較表
Command A. Disksim (ms) B. RTD2950 (ms) C. 誤差
Block erase 1.323045 1.324519 0.11%
Page read (512 bytes) 0.091265 0.096593 5.84%
Page program (512 bytes)
0.253185 0.259259 2.40%
我們分析 Page read 仍有較大的誤差原因在於：使用 Disksim 模擬時，並 未加計軟體的運算時間，而在 RTD2950 上測得的數值包含設定控制器與讀取 計時器的軟體運算時間，此部份難以排除。由於 Page read 所耗時間相對地少，
所以前述之軟體運算時間所佔比例便相對地提高了。
不過另一做法是將驗證帄台的軟體運算時間加至 Disksim 的 iodriver 模 擬，這樣也可以改善誤差，進而提高本研究的精確度。
四、結論
Disksim 在研究儲存系統效能上被廣泛運用，而且被證明是精確、彈性、
有效率的工具。我們沿用其既有之架構、功能，加入快閃記憶體的裝置與控制 器模組，除了保有其優點外，使其功能支援 NAND 快閃記憶體儲存系統，並在 一系統晶片帄台驗證其基本命令的正確性。本研究之彈性設計即使不同的控制 器、記憶體也能適用，並可隨著新世代記憶體演進之規格而擴充，提高其可用 性。
經過實驗證明，實際硬體帄台效能測試的結果與模擬器輸出的效能結果差 異在 5.84% 以內，因此本研究可以作為快閃記憶體儲存系統研究（例如：FTL，
Flash 檔案系統研究）的實驗與效能評估帄台。
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